DATASHEET
Frequency Timing Generator for Peripherals
9FGP205
VDDRMII
RMII1
RMII0
VDDRGMII
GNDRGMII
RGMII1
RGMII0
SMBCLK
Vtt_PWRGD/WOL_STOP#
Output Features:
•
1 - 0.7V current-mode differential CPU output
•
6 - 50MHz RMII outputs
•
2 - 125MHz RGMII outputs
•
1 - 0.7V current-mode differential DOT 96MHz output
•
1 - 33.33MHz output
•
1 - 32.768KHz output
•
2 - 25MHz REF outputs
SMBDAT
Pin Configuration
Recommended Application:
Peripheral Clock for Intel Servers with Wake-On-Lan support
40 39 38 37 36 35 34 33 32 31
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
Key Specifications:
•
Exact synthesis on CPU, RGMII, RMII & 33.33MHz
clocks
•
+/- 100ppm frequency accuracy on other clocks
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
9FGP205
GNDRMII
RMII2
RMII3
GNDRMII
VDDRMII
RMII4
RMII5
VDD33
33.33MHZ/**SMBADR
GND33
X2_25
X1_25
GNDREF
25MHZ_1
25MHz_0
VDDREF
GND32K
32.768KHz
IREF
VDD32K
11 12 13 14 15 16 17 18 19 20
Features/Benefits:
•
Selectable SMBus Address - D0/D1 or C0/C1
•
Spread Spectrum capability on CPU and DOT 96MHz
clocks
•
SMBus Control:
- M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
- Differential outputs can be disabled via pins or SMBus
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Dow n Resistor
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
MHz
MHz
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0
0
0
0
266.67
96.00
0
0
1
133.33
96.00
0
1
0
200.00
96.00
0
1
1
166.67
96.00
1
0
0
333.33
96.00
1
0
1
100.00
96.00
1
1
0
400.00
96.00
1
1
1
Reserved
96.00
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
RGMII
MHz
125.00
125.00
125.00
125.00
125.00
125.00
125.00
125.00
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
Power up default is highlighted.
SMBus Address Selection
SMBADR
SMBADR = 0
D0/D1
SMBADR = 1
C0/C1
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
1
9FGP205
Frequency Timing Generator for Peripherals
Pin Description
1
2
GND
VDD96
PIN
TYPE
PWR
PWR
3
DOT96SST
OUT
4
DOT96SSC
OUT
5
OE_96
IN
6
OE_CPU
IN
7
CPUCLKT0
OUT
8
CPUCLKC0
OUT
9
10
VDDCPU
GNDCPU
PWR
PWR
11
IREF
OUT
12
13
14
15
16
17
18
19
20
21
22
VDD32K
32.768KHz
GND32K
VDDREF
25MHz_0
25MHZ_1
GNDREF
X1_25
X2_25
GND33
33.33MHZ/**SMBADR
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
Ground pin.
Power pin for the DOT96 clocks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are
current mode outputs. External resistors are required for voltage bias.
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
These are current mode outputs. External resistors are required for voltage bias.
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 = tri-state output(s)
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current.
475 ohms is the standard value.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs.
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz.
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
VDD33
RMII5
RMII4
VDDRMII
GNDRMII
RMII3
RMII2
GNDRMII
VDDRMII
RMII1
RMII0
VDDRGMII
GNDRGMII
RGMII1
RGMII0
SMBCLK
SMBDAT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
Power pin for the 33.33MHz outputs, nominal 3.3V
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the RMII outputs
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
Ground pin for the RMII outputs
3.3V power pin for the RMII clocks.
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RGMII clocks and PLL
Ground pin for the RGMII outputs
3.3V 125MHz RGMII clock output
3.3V 125MHz RGMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
40
CKPWRGD_WOL_STOP#
PIN #
PIN NAME
IN
DESCRIPTION
Notifies clock to sample latched inputs on first low to high transition. After first power up, a low
stops all outputs except those designated to run in power down mode (WOL_STOP# mode)
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
2
9FGP205
Frequency Timing Generator for Peripherals
General Description
The 9FGP205 is a peripheral clock for Intel Servers. It is driven with a 25MHz crystal and generates a variety of clocks,
including 125MHz RGMII. An SMBus interface allows full control of the device.
Block Diagram
25MHz(1:0)
X1_25
X2_25
XTAL
CPU PLL
(SPREAD
CAPABLE)
CPUCLK
DOT PLL
(SPREAD
CAPABLE)
DOT96SS
CKPWRGD_
WOL_STOP#
33.33MHz
OE_CPU
OE_96
SMBADR
CONTROL
LOGIC
FIXED
PLL
DIVIDERS
SMBDAT
SMBCLK
DIVIDERS
2
RGMII(1:0)
6
RMII(5:0)
32.768KHz
Power Supply Pins
Pin Number
Description
VDD
GND
9
10
CPUCLK output and PLL
2
1
DOT96SS output and PLL
34
35
125 MHz RGMII outputs and PLL
26,31
27,30
50 MHz RMII outputs
23
21
33.33MHz output
12
14
32.768KHz output
15
18
XTAL, REF outputs
Note: All VDD should be connected to a common power rail with proper
filtering and decoupling. Pins 2, 9 and 34 should be treated as analog pins for
decoupling purposes.
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
3
9FGP205
Frequency Timing Generator for Peripherals
ICS9FGP202A
ICS9FGP205
Zo
Rs
CL=5pF
Test Load
SEPP Output Buffer
(Single Ended
Push Pull)
L1
Zo
Rs
CL=5pF
L2
Zo
Rs
SEPP Output Buffer
(Single Ended
Push Pull)
CL=5pF
NOTE: L1 must equal L2 +/- 25 mils
Drive Strength for all the single-ended outputs can be controlled by the SMBus Bytes 4 and 5 as shown in the Default Drive Strength Table.
Default Drive Strength Table
Default Drive
RGMII
1 Load
RMII
1 Load
33.33MHz
2 Loads
25Mhz
2 Loads
32.768KHz
2 Loads
Series Termination Resistor Values EXCEPT RGMII
Series Resistor Series Resistor
Output Drive (Rs) for driving 1 (Rs) for driving 2
Loads
Load
Strength
1 Load
22 ohms
N/A
2 Loads
33 ohms
8.2 ohms
Note: All values are for Zo = 50Ω
Series Termination Resistor Values - RGMII
Series Resistor Series Resistor
(Rs)
for driving 1 (Rs) for driving 2
Output Drive
Loads
Load
Strength
1 Load
27 ohms
N/A
Note: All values are for Zo = 50Ω
Optional Drive
NA
2 Loads
1 Load
1 Load
1 Load
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
4
9FGP205
Frequency Timing Generator for Peripherals
Truth Table1: CKPWRGD_WOL_STOP#, OE_96 and OE_CPU
CKPWRGD_WOL_STOP#
OE_96
DOT96SSC OE_CPU
0
X
X
X
0
1
0
Disabled
0
1
1
Enabled
1
CPUCLK
X
Disabled
Enabled
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Truth Table 2: CKPWRGD_WOL_STOP# Single-ended outputs
Other
Pin 16, 29,
Pin 22
CKPWRGD_WOL_STOP#
outputs
32, 33
0
Running
Hi-Z
Low
1
Running
Running
Running
*Assuming SMBus at default value.
Table: CPU Spread and Frequency Selection
CPU
SS_EN
Byte 0
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPU
FS2
Byte 0
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPU
FS1
Byte 0
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CPU
FS0
Byte 0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
Down
Spread %
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
5
9FGP205
Frequency Timing Generator for Peripherals
Table: DOT96 Spread and Frequency Selection Table
DOT96
SS_EN
Byte 0
bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
FS2
FS1
FS0
Byte 3
bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Byte 3
bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Byte 3
bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Byte 3
bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DOT96SS
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
IDT® Frequency Timing Generator for Peripherals
Spread %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
+/-0.25
+/-0.5
+/-0.75
+/-1.0
-0.25
-0.50
-0.75
-1.0
-1.25
-1.50
-1.75
-2.0
-2.25
-2.5
-2.75
-3.00
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
1664—07/16/14
6
9FGP205
Frequency Timing Generator for Peripherals
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Supply Voltage
VDDxxx
-
VDDdelta
-
Maximum difference across all
VDD pins
Storage Temperature
MIN
GND 0.5
TYP
3.3V
MAX
GND +
4.5
UNITS
Notes
V
1
0.5
V
1
°
Ts
-
-65
150
C
1
Tambient
-
0
70
°C
1
Junction Temperature
Tj
-
125
°C
1
Input ESD protection HBM
ESD prot
-
V
1
Ambient Operating Temp
2000
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
Input High Voltage
VIH
3.3 V +/-5%
1.8
Input Low Voltage
VIL
3.3 V +/-5%
Input High Current
I IH
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
IIL1
Input Low Current
IIL2
VDD +
0.3
V
1
1.4
V
1
5
uA
1
-5
uA
1
-200
uA
1
VSS 0.3
-5
0.7
VDD +
0.3
V
1
VIL_FS
3.3 V +/-5%
VSS 0.3
0.35
V
1
IDD3.3OP
all outputs driven, CPU@100M
WOL_STOP mode (default)
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
225
75
30
8
7
4
5
5
mA
mA
mA
mA
MHz
nH
pF
pF
pF
1
1
1
1
2
1
1
1
1
2.5
ms
1
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
1
1
1
1
mA
1
1000
ns
1
300
ns
1
IDD3.3PD
Input Frequency
Pin Inductance
Fi
Lpin
CIN
COUT
CINX
TSTAB
Modulation Frequency
Tdrive_PD
Tfall_PD
Trise_PD
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
UNITS Notes
3.3 V +/-5%
Powerdown Current
Clk Stabilization
MAX
VIH_FS
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Operating Current
Input Capacitance
TYP
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or deassertion of PD to 1st clock
Triangular Modulation
CPU output enable after
PD de-assertion
PD fall time of
PD rise time of
30
260
@ I PULLUP
4
IPULLUP
TFI2C
0.5
2.7
VDD
VOL
TRI2C
25.00
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
5
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
7
9FGP205
Frequency Timing Generator for Peripherals
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
PARAMETER
Current Source Output
Impedance
Voltage High
SYMBOL
CONDITIONS*
MIN
Zo
VO = Vx
3000
VHigh
731
VLow
Statistical measurement on single
ended signal
660
Voltage Low
-150
70
Max Voltage
Vovs
800
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vx
Long Accuracy
ppm
Measurement on single ended
signal using absolute value.
MAX
UNITS NOTES
Ω
1
850
mV
1,3
150
mV
1,3
1150
mV
1
mV
1
-300
8
250
366
550
mV
1
16
140
mV
1
Variation of crossing over all
edges
see Tperiod min-max values
-100
0
100
ppm
1,2
100.00MHz nominal
9.9990
10.0000
10.0001
ns
2
100.00MHz spread
10.0240
10.0250
10.0251
ns
2
Average period
Tperiod
Absolute min/max period
Tabsmin/max
100.00MHz nominal/spread
9.9490
10.1011
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
376
700
ps
1,4
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
335
700
ps
1,4
d-tr
VOL = 0.175V, VOH = 0.525V
104
125
ps
1
92
125
ps
1
12.7
20
%
1
1
2
4
V/ns
1,5
45
49.8
55
%
1
45
50
ps
1
Rise Time Variation
VOH = 0.525V VOL = 0.175V
Single-ended measurement,
Rise/Fall Matching
tRFM
averaging on
Differential Measurment
Slew Rate
tSLEW
Measurement from differential
Duty Cycle
dt3
wavefrom
Measurement from differential
Jitter, Cycle to cycle
tjcyc-cyc
wavefrom, CPUCLK
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω
Fall Time Variation
1
TYP
d-tf
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4
Rise/fall time measured on single-ended waveform per CK410 specification.
5
Slew rate measured on differential waveform per CK505 specification.
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
8
9FGP205
Frequency Timing Generator for Peripherals
Electrical Characteristics - DOT96SS 0.7V Current Mode Differential Pair
PARAMETER
Current Source Output
Impedance
Voltage High
SYMBOL
CONDITIONS*
MIN
Zo
VO = Vx
3000
VHigh
660
Voltage Low
VLow
Statistical measurement on single
ended signal
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Measurement on single ended
signal using absolute value.
725
-150
MAX
850
UNITS
Notes
Ω
1
mV
1,3
51
150
mV
1,3
764
1150
mV
1
-300
5
250
372
mV
1
550
mV
1
140
mV
1
1,2
Variation of crossing over all
edges
see Tperiod min-max values
-100
-41
100
ppm
96.00MHz nominal
10.4156
10.4166
10.4176
ns
2
96.00MHz -0.5% spread
10.4417
10.4427
10.4437
ns
2
10.1917
10.6937
ns
1,2
Average period
Tperiod
Absolute min period
Tabsmin
96.00MHz nominal/-0.5% spread
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
361
700
ps
1,4
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
375
700
ps
1,4
Rise Time Variation
d-tr
VOL = 0.175V, VOH = 0.525V
107
125
ps
1
107
125
ps
1
15
20
%
1
1
2
4
V/ns
1,5
45
51.3
55
%
1
54
250
ps
1
VOH = 0.525V VOL = 0.175V
Single-ended measurement,
Rise/Fall Matching
tRFM
averaging on
Differential Measurment
Slew Rate
tSLEW
Measurement from differential
Duty Cycle
dt3
wavefrom
Measurement from differential
Jitter, Cycle to cycle
tjcyc-cyc
wavefrom
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω
Fall Time Variation
1
TYP
d-tf
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4
Rise/fall time measured on single-ended waveform per CK410 specification.
5
Slew rate measured on differential waveform per CK505 specification.
Electrical Characteristics - REF - 25MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Long Accuracy
Clock period
ppm
Tperiod
see Tperiod min-max values
25.00MHz output nominal
-50
39.998
0
40.000
50
40.002
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
Output High Current
I OH
Output Low Current
I OL
Rise Time
Fall Time
Skew
Duty Cycle
Jitter, Cycle-cycle
tr1
tf1
IOH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
V OL @ MIN = 1.95 V
V OL @ MAX = 0.4 V
V OL = 0.4 V, VOH = 2.4 V
V OH = 2.4 V, VOL = 0.4 V
V T = 1.5 V
V T = 1.5 V
V T = 1.5 V
t sk1
dt1
tjcyc-cyc
0.4
-29
-23
29
0.5
0.5
45
1.14
1.32
16
53.2
75
27
2
2
500
55
200
UNITS Notes
ppm
ns
1,2
2
V
V
mA
mA
mA
mA
ns
ns
ps
%
ps
1
1
1
1
1
1
1
1
1
1
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1Guaranteed
2 All
by design and characterization, not 100% tested in production.
Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
9
9FGP205
Frequency Timing Generator for Peripherals
Electrical Characteristics - RGMII - 125MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
Long Accuracy
ppm
see Tperiod min-max values
0
Clock period
Tperiod
125.00MHz output nominal
-50
7.9996
50
8.0004
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
Output Low Current
IOL
Rise Time
tr
VOL=20%xVdd, VOH=80%xVdd
0.66
Fall Time
tf
VOL=20%xVdd, VOH=80%xVdd
0.70
0.75
V OH @MIN = 1.0 V
8.000
UNITS NOTES
1,2
ppm
V
1
V
1
mA
1
-33
mA
1
mA
1
38
mA
1
0.75
ns
1
ns
1
-33
30
VOL @ MAX = 0.4 V
45
1
0.4
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
ns
Duty Cycle
dt1
VT = 1.5 V
52.9
55
%
1
Group Skew
tskew_RGMII
VT = 1.5 V,
15
100
ps
1
Jitter, Long Term
tjabs
VT = 1.5 V, 10 sec interval
141
500
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
75
250
ps
1
Jitter, Peak
tjpeak
VT = 1.5 V
68
100
ps
1,3
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz
3
1/2 of the peak-to-peak jitter. (Lg+ + |Lg-|)/2
Electrical Characteristics - RMII - 50MHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS*
see Tperiod min-max values
Clock period
Output High Voltage
Output Low Voltage
Tperiod
V OH
V OL
Output High Current
I OH
Output Low Current
I OL
Rise Time
Fall Time
Duty Cycle
tr
tf
dt1
50.00MHz output nominal
I OH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
V OL = 0.4 V, V OH = 2.4 V
V OH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Group Skew
t skew_RMII(
5:0)
Jitter, Long Term
Jitter, Peak
tjabs
tjpeak
V T = 1.5 V,
across all 6 outputs
VT = 1.5 V, 10 sec interval
VT = 1.5 V
MIN
-50
19.9990
TYP
0
20.0000
MAX
50
20.001
NOTES
1,2
1
1.1
1.1
51.5
38
3
3
65
ns
V
V
mA
mA
mA
mA
ns
ns
%
60
200
ps
1
127
88
500
100
ps
ps
1
1,3
2.4
0.4
-33
-33
30
0.5
0.5
35
UNITS
ppm
1
1
1
1
1
1
1
1
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz_x is tuned to exactly 25.000MHz
3
1/2 of the peak-to-peak jitter. (Lg+ + |Lg-|)/2
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
10
9FGP205
Frequency Timing Generator for Peripherals
Electrical Characteristics - 33.33MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
Long Accuracy
ppm
see Tperiod min-max values
Clock period
Tperiod
33.33MHz output non-spread
-100
29.9970
0
30.0000
100
30.0030
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
0.4
V OH @MIN = 1.0 V
IOH
-33
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
-33
30
UNITS NOTES
1
ppm
ns
1
V
1
V
1
mA
1
mA
1
mA
1
Output Low Current
IOL
38
mA
1
Rise Time
tr
VOL = 0.4 V, VOH = 2.4 V
0.5
0.87
2
ns
1
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
0.5
1.35
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
50.7
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
104
350
ps
1
VOL @ MAX = 0.4 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - 32.768KHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS*
see Tperiod min-max values
Clock period
Output High Voltage
Output Low Voltage
Tperiod
VOH
V OL
Output High Current
I OH
Output Low Current
I OL
Rise Time
Fall Time
Duty Cycle
Jitter, Cycle to cycle
tr
tf
dt1
32.768KHz output nominal
IOH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
V OL @ MAX = 0.4 V
V OL = 0.4 V, V OH = 2.4 V
V OH = 2.4 V, V OL = 0.4 V
V T = 1.5 V
V T = 1.5 V
t jcyc-cyc
MIN
-100
TYP
-79
MAX
100
30.5149 30.5180 30.5211
2.4
0.4
-33
-33
30
38
0.5
1.39
4
0.5
1.6
4
45
49.5
55
220
500
UNITS
ppm
NOTES
us
V
V
mA
mA
mA
mA
ns
ns
%
ps
1
1
1
1
1
1
1
1
1
1
1
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
11
9FGP205
Frequency Timing Generator for Peripherals
General SMBus serial interface information for the 9FGP205
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address *D0(H)
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address *D0(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address *D1(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
IDT® Frequency Timing Generator for Peripherals
Not acknowledge
stoP bit
1664—07/16/14
12
9FGP205
Frequency Timing Generator for Peripherals
SMBus Table: CPU Frequency Select and Spread Spectrum Control Register
Pin #
Byte 0
Name
Control Function
WOL_STOP_EN
Enables 25M in Power Down
Bit 7
Reserved
Reserved
Bit 6
Reserved
Reserved
Bit 5
DOT96 SS_EN
DOT96 Spread Spectrum Enable
Bit 4
CPU SS_EN
CPU Spread Spectrum Enable
Bit 3
CPU FS2
CPU Freq Select Bit 2
Bit 2
CPU FS1
CPU Freq Select Bit 1
Bit 1
CPU FS0
CPU Freq Select Bit 0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: RMII Output Control Register
Pin #
Byte 1
Name
24
RMII_5 Enable
Bit 7
RMII_4 Enable
25
Bit 6
RMII_3 Enable
28
Bit 5
29
RMII_2 Enable
Bit 4
32
RMII_1 Enable
Bit 3
RMII_0 Enable
33
Bit 2
36
RGMII_1 Enable
Bit 1
37
RGMII_0 Enable
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register
Pin #
Byte 2
Name
Control Function
Type
7,8
RW
CPUCLK PD Drive Mode
Driven in power down
Bit 7
DOT96SS PD Drive Mode
Driven in power down
RW
3,4
Bit 6
33.33MHz Enable
33.33MHz Output Control
22
RW
Bit 5
17
25MHz_1 Enable
25MHz_1 Output Control
RW
Bit 4
16
25MHz_0 Enable
25MHz_0 Output Control
RW
Bit 3
13
32.768kHz Enable
32.768KHz Output Control
RW
Bit 2
CPUCLK Enable
CPUCLK Output Control
6
RW
Bit 1
5
DOT96SS Enable
DOT96SS Output Control
RW
Bit 0
0
Driven
Driven
Disable
Disable
Disable
Disable
Disable
Disable
1
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
0
Off
Off
Off
Off
1
Runs
Runs
Runs
Runs
PWD
0
0
0
1
0
0
0
0
Control Function
RMII_7 Output Control
RMII_6 Output Control
RMII_5 Output Control
RMII_4 Output Control
RMII_3 Output Control
RMII_2 Output Control
RGMII_1 Output Control
RGMII_0 Output Control
SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register
Pin #
Byte 3
Name
Control Function
24
RMII_5 WOL_STOP
RMII_5 runs in power down
Bit 7
25
RMII_4 WOL_STOP
RMII_4 runs in power down
Bit 6
28
RMII_3 WOL_STOP
RMII_3 runs in power down
Bit 5
29
RMII_2 WOL_STOP
RMII_2 runs in power down
Bit 4
DOT96SS FS3
DOT96 Freq Select Bit 3
Bit 3
DOT96SS FS2
DOT96 Freq Select Bit 2
Bit 2
DOT96SS FS1
DOT96 Freq Select Bit 1
Bit 1
DOT96SS FS0
DOT96 Freq Select Bit 0
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: RMII Strength Control Register
Pin #
Byte 4
Name
24
RMII_5 Str
Bit 7
25
RMII_4 Str
Bit 6
28
RMII_3 Str
Bit 5
RMII_2 Str
29
Bit 4
RMII_1 Str
32
Bit 3
33
RMII_0 Str
Bit 2
32
RMII_1 WOL_STOP
Bit 1
33
RMII_0 WOL STOP
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Control Function
RMII_5 Strength Control
RMII_4 Strength Control
RMII_3 Strength Control
RMII_2 Strength Control
RMII_1 Strength Control
RMII_0 Strength Control
RMII_1 runs in power down
RMII_0 runs in power down
IDT® Frequency Timing Generator for Peripherals
0
1
Disable
Enabled
Reserved
Reserved
Disable
Enable
See Table 1:
CPU Frequency Selection
Table
See Table 2:
DOT Frequency Selection
Table
0
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
Off
Off
1
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
Runs
Runs
PWD
1
0
0
0
0
1
0
1
PWD
0
0
0
0
0
0
1
1
1664—07/16/14
13
9FGP205
Frequency Timing Generator for Peripherals
SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register
Pin #
Byte 5
Name
Control Function
Reserved
Reserved
Bit 7
Reserved
Reserved
Bit 6
22
33.33MHz Str
33.33MHz Strength Control
Bit 5
17
25MHz_1 Str
25MHz_1 Strength Control
Bit 4
16
25MHz_0 Str
25MHz_1 Strength Control
Bit 3
13
32.768kHz Str
32.768kHz Strength Control
Bit 2
17
25MHz_1_WOL_STOP
25MHz_1 runs in power down
Bit 1
16
25MHz_0_WOL_STOP
25MHz_0 runs in power down
Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Reserved
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
Off
Off
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
Runs
Runs
SMBus Table: Vendor & Revision ID Register
Pin #
Byte 6
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
1
SMBus Table: Device ID
Byte 7
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0 (LSB)
SMBus Table: Byte Count Register
Pin #
Byte 8
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
SMBus Table: Reserved
Pin #
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID
Control Function
Writing to this register configures
how many bytes will be read back.
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® Frequency Timing Generator for Peripherals
1
A rev = 0000
B rev = 0001
ICS/IDT = 0001
Type
R
R
R
R
R
R
R
R
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
PWD
0
0
1
1
1
1
0
1
PWD
X
X
X
X
0
0
0
1
1
PWD
0
0
1
0
0
1
0
1
0
-
1
-
PWD
0
0
0
0
1
0
0
1
0
1
PWD
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1664—07/16/14
14
9FGP205
Frequency Timing Generator for Peripherals
SMBus Table: PLLs M/N Programming Enable Register
Pin #
Byte 10
Name
Control Function
Bit 7
M/N_EN
PLLs M/N Programming Enable
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Bit 0
Reserved
Type
RW
0
Disable
1
Enable
PWD
0
0
0
0
0
0
0
0
SMBus Table: CPU PLL VCO Frequency Control Register
Pin #
Byte 11
Name
Control Function
Bit 7
N Div8
N Divider Prog bit 8
Bit 6
N Div 9
N Divider Prog bit 9
Bit 5
M Div5
Bit 4
M Div4
Bit 3
M Div3
M Divider Programming bits
Bit 2
M Div2
Bit 1
M Div1
Bit 0
M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
VCO frequency. Default at
power up = latch-in or Byte 0
Rom table. VCO Frequency
= 25 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 12
Pin #
Name
Control Function
Bit 7
N Div7
Bit 6
N Div6
Bit 5
N Div5
Bit 4
N Div4
N Divider Programming b(7:0)
Bit 3
N Div3
Bit 2
N Div2
Bit 1
N Div1
Bit 0
N Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation
of M and N Divier in Byte 11
and 12 will configure the
VCO frequency. Default at
power up = latch-in or Byte 0
Rom table. VCO Frequency
= 25 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Pin #
Byte 13
Name
Control Function
Bit 7
SSP7
Bit 6
SSP6
Bit 5
SSP5
Spread Spectrum Programming
Bit 4
SSP4
b(7:0)
Bit 3
SSP3
Bit 2
SSP2
Bit 1
SSP1
Bit 0
SSP0
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte 14
Name
Control Function
Pin #
Reserved
Bit 7
Bit 6
SSP14
Bit 5
SSP13
Bit 4
SSP12
Spread Spectrum Programming
Bit 3
SSP11
b(14:8)
Bit 2
SSP10
Bit 1
SSP9
Bit 0
SSP8
IDT® Frequency Timing Generator for Peripherals
Type
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits
in Byte 13 and 14 will
program the spread
pecentage. It is
recommended to use ICS
Spread % table for spread
programming.
0
1
These Spread Spectrum bits
in Byte 13 and 14 will
program the spread
pecentage. It is
recommended to use ICS
Spread % table for spread
programming.
PWD
X
X
X
X
X
X
X
X
PWD
0
X
X
X
X
X
X
X
1664—07/16/14
15
9FGP205
Frequency Timing Generator for Peripherals
SMBus Table: DOT PLL VCO Frequency Control Register
Pin #
Byte 15
Name
Control Function
Bit 7
N Div8
N Divider Prog bit 8
Bit 6
N Div9
N Divider Prog bit 9
Bit 5
M Div5
Bit 4
M Div4
Bit 3
M Div3
M Divider Programming bits
Bit 2
M Div2
Bit 1
M Div1
Bit 0
M Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation
of M and N Divier in Byte 17
and 18 will configure the
VCO frequency. Default at
power up = Byte 0 Rom
table. VCO Frequency = 25
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: DOT PLL VCO Frequency Control Register
Pin #
Byte 16
Name
Control Function
Bit 7
N Div7
Bit 6
N Div6
Bit 5
N Div5
Bit 4
N Div4
N Divider Programming b(7:0)
Bit 3
N Div3
Bit 2
N Div2
Bit 1
N Div1
Bit 0
N Div0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
The decimal representation
of M and N Divier in Byte 17
and 18 will configure the
VCO frequency. Default at
power up = Byte 0 Rom
table. VCO Frequency = 25
x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: DOT PLL Spread Spectrum Control Register
Byte 17
Pin #
Name
Control Function
Bit 7
SSP7
Bit 6
SSP6
Bit 5
SSP5
Spread Spectrum Programming
Bit 4
SSP4
b(7:0)
Bit 3
SSP3
Bit 2
SSP2
Bit 1
SSP1
Bit 0
SSP0
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBus Table: DOT PLL Spread Spectrum Control Register
Pin #
Byte 18
Name
Control Function
Reserved
Bit 7
Bit 6
SSP14
Bit 5
SSP13
Bit 4
SSP12
Spread Spectrum Programming
Bit 3
SSP11
b(14:8)
Bit 2
SSP10
Bit 1
SSP9
Bit 0
SSP8
Type
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits
in Byte 19 and 20 will
program the spread
pecentage. It is
recommended to use ICS
Spread % table for spread
programming.
0
1
These Spread Spectrum bits
in Byte 19 and 20 will
program the spread
pecentage. It is
recommended to use ICS
Spread % table for spread
programming.
PWD
X
X
X
X
X
X
X
X
PWD
0
X
X
X
X
X
X
X
Bytes 19:21 are reserved.
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
16
9FGP205
Frequency Timing Generator for Peripherals
(Ref.)
Seating Plane
(N D -1)x e
(Ref.)
A1
Index Area
ND & NE
Even
A3
N
L
N
1
Anvil
Singulation
1
2
E2
(Ref.)
b
(Ref.)
A
D
(NE -1)x e
E2
2
Sawn
Singulation
Top View
are Even
2
or
E
(Typ.)
e
2 If N & N
D
E
e
Thermal
Base
D2
2
ND & NE
Odd
D2
0.08
C
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
DIMENSIONS
(JEDEC
reference only)
MIN.
A
0.8
1.0
SYMBOL
VJJD-2 / -5
TOLERANCE
A1
0
0.05
N
40
40
ND
10
10
NE
10
10
D x E BASIC
6.00 x 6.00
6.00 x 6.00
A3
b
MAX.
(IDT package)
SYMBOL
40L
0.25 Reference
0.1 8
e
0.3
0.50 BASIC
D2 MIN. / MAX.
1.75 / 4.80
2.75 / 3.0
E2 MIN. / MAX.
1.75 / 4.80
2.75 / 3.0
L MIN. / MAX.
0.30 / 0.50
0.3 / 0.5
Ordering Information
Part / Order Number
9FGP205AKLF
9FGP205AKLFT
Shipping Packaging
Trays
Tape and Reel
Package
40-pin MLF
40-pin MLF
Temperature
0 to +70° C
0 to +70° C
“LF” to the suffix are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
IDT® Frequency Timing Generator for Peripherals
1664—07/16/14
17
9FGP205
Frequency Timing Generator for Peripherals
DATASHEET
Revision History
Rev.
Issue Date
Who
A
7/16/2014
D.C.
Description
1. Updated VIH/VIL to 1.8 and 1.4V respectively
2. Updated Rise/Fall times from 1ns to 0.5ns
Page #
7,9,10,11
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