9LPR501SGLF

Datasheet ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Recommended Application: Key Specifications: CK505 compliant clock with fully integrated voltage regulator, PCIe Gen 1 compliant • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on CPU & SRC clocks Output Features: • 2 - CPU differential low power push-pull pairs • 10 - SRC differential low power push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 5 - PCI, 33MHz • 1 - PCI_F, 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz 2 FS LC B0b7 0 0 0 0 1 1 1 1 1 FS LB B0b6 0 0 1 1 0 0 1 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 • Does not require external pass transistor for voltage regulator • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • One differential push-pull pair selectable between SRC and two single-ended outputs Pin Configuration SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 SRCC11/CR#_G Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9LPR501 Table 1: CPU Frequency Select Table Features/Benefits: 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H 64-pin TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 1 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Pin Description PIN # PIN NAME 1 PCI0/CR#_A 2 VDDPCI 3 PCI1/CR#_B TYPE DESCRIPTION I/O 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PWR I/O 4 PCI2/TME I/O 5 PCI3 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 GNDPCI VDD48 10 USB_48MHz/FSLA 11 12 GND48 VDD96_IO PWR PWR 13 DOTT_96/SRCT0 OUT 14 DOTC_96/SRCC0 OUT 15 16 GND VDD PWR PWR OUT PWR PWR I/O Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 37 and 38). The latched value controls the pin function on pins 37 and 38 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 2 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Pin Description (continued) PIN # PIN NAME TYPE 17 SRCT1/SE1 OUT 18 SRCC1/SE2 OUT 19 20 21 22 23 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC PWR PWR OUT OUT PWR 24 SRCT3/CR#_C 25 SRCC3/CR#_D 26 27 28 29 30 31 VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 32 SRCC11/CR#_G DESCRIPTION True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. I/O True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair I/O Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair PWR I/O I/O PWR OUT OUT I/O Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 3 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Pin Description (Continued) PIN # PIN NAME 33 SRCT11/CR#_H 34 35 36 SRCT10 SRCC10 VDDSRC_IO 37 CPU_STOP#/SRCC5 TYPE I/O OUT OUT PWR I/O 38 PCI_STOP#/SRCT5 I/O 39 40 41 42 VDDSRC SRCC6 SRCT6 GNDSRC 43 SRCC7/CR#_E I/O 44 SRCT7/CR#_F I/O 45 VDDSRC_IO PWR 46 CPUC2_ITP/SRCC8 OUT 47 CPUT2_ITP/SRCT8 OUT 48 NC N/A PWR OUT OUT PWR DESCRIPTION SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3 bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC internal circuits, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 4 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION 49 VDDCPU_IO PWR 50 CPUC1_F OUT 51 CPUT1_F OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. 52 53 54 55 56 GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# PWR OUT OUT PWR IN 57 FSLB/TEST_MODE 58 59 60 61 GNDREF X2 X1 VDDREF 62 REF0/FSLC/TEST_SEL I/O 63 64 SDATA SCLK I/O IN Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. IN PWR OUT IN PWR Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. Fully Integrated Regulator Connection for Desktop/Mobile Applications ICS9LPR501 VDDCPU_IO, Pin 49 1.05V to 3.3V (+/-5%) CPU_IO Decoupling Network 96_IO Decoupling Network NC PIN 48 PLL3_IO Decoupling Network SRC_IO Decoupling Network VDDSRC_IO Pin 45,36,26 VDDPLL3_IO, Pin 20 VDD96_IO, Pin 12 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 5 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information General Description ICS9LPR501 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation Intel processors and Intel chipsets. ICS9LPR501 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Functional Block Diagram X1 REF R EF X2 OSC CPU(1:0) SRC8/ITP CPU CPU PLL1 SS SRC SRC(11-9,7:3) SR C _M A IN PCI33MHz SRC PLL3 SS PCI PCI33MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# SRC1/SE(2:1) CPU_STOP# CR#_(A:H) SRC5_EN Control Logic Differential Output ITP_EN SE Outputs 7 FSLC/TESTSEL FSLB/TESTMODE SRC0/DOT96 SATA PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD GND 49 52 55 52 26, 36, 45 23, 29, 42 39 23, 29, 42 20 19 16 19 12 11 9 11 61 58 2 8 Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 6 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Absolute Maximum Ratings - DC Parameters PARAMETER SYMBOL CONDITIONS Maximum Supply Voltage VDDxxx Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply Maximum Supply Voltage 3.3V Inputs Maximum Input Voltage V IH V IL Any Input Minimum Input Voltage Case Temperature Tcase Thermal Resistance from Die to Ambient JA Air Thermal Resistance from Die to Package JC Case Storage Temperature Ts ESD prot Human Body Model Input ESD protection 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied, nor guaranteed. 3 Maximum input voltage is not to exceed VDD MIN TYP MAX 4.6 3.8 4.6 GND - 0.5 115 -65 2000 UNITS V V V V ° C 32.5 °C/W 68.2 °C/W 150 Notes 7 7 4,5,7 4,7 ° C V 4,7 6,7 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Rising Edge Slew Rate tSLR Averaging on 2.5 3.35 4 V/ns 2, 3 Falling Edge Slew Rate tFLR Averaging on 2.5 3.30 4 V/ns 2, 3 Slew Rate Variation tSLVAR Averaging on 20 % 1, 10 Differential Voltage Swing VSWING Averaging off 300 mV 2 Crossing Point Voltage VXABS Averaging off 300 405.5 550 mV 1,4,5 VXABSVAR Averaging off 60 140 mV 1,4,9 Crossing Point Variation Maximum Output Voltage VHIGH Averaging off 894 1150 mV 1,7 Minimum Output Voltage VLOW Averaging off -300 59.5 mV 1,8 45 51.0 55 % 2 Duty Cycle DCYC Averaging on CPU[1:0] Skew CPUSKEW10 Differential Measurement 47 100 ps 1 CPU[2_ITP:0] Skew CPUSKEW20 Differential Measurement 125 150 ps 1 SRC[10:0] Skew SRCSKEW Differential Measurement 704 3000 ps 1,6 NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Measurement taken for single ended waveform on a component test board (not in system) 2 Measurement taken from differential waveform on a component test board. (not in system) 3 Slew rate emastured through V_swing voltage range centered about differential zero 4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) 5 Only applies to the differential rising edge (Clock rising, Clock# falling) 6 Total distributed intentional SRC to SRC skew. 7 The max voltage including overshoot. 8 The min voltage including undershoot. 9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute. 10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. Clock Jitter Specs - Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN TYP MAX CPU Jitter - Cycle to Cycle CPUJC2C Differential Measurement 58.1 85 SRC Jitter - Cycle to Cycle SRCJC2C Differential Measurement 36.2 125 SATA Jitter - Cycle to Cycle SATAJC2C Differential Measurement 46.8 125 DOT Jitter - Cycle to Cycle DOTJC2C Differential Measurement 73.0 250 NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). UNITS NOTES ps ps ps ps 1 1,2 1 1 1 JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the insystem performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver jitter specs as measured in a real system. 2 Phase jitter requirement: The SRC outputs will meet the reference clock jitter requiremernts from the PCI Express Gen1 Base Spec. The test is performed on a component test board under quiet condittions with all outputs on. Jitter analysis is performed using the standardized tool provided by the PCI SIG. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 7 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Electrical Characteristics - Input/Supply/Common Output DC Parameters PAR AMETER Ambient Operating Temp Supply Voltage Supply Voltage Input H igh Voltage Input Low Voltage Low Threshold InputHigh Voltage FSC = Test Mode Low Threshold InputFSC = '1' Voltage Low Threshold InputFSA,FSB = '1' Voltage Low Threshold InputLow Voltage Input Leakage Current SYMBOL Tambient VDDxxx VDDxxx_IO V IHSE V ILSE CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended 3.3V inputs Single-ended 3.3V inputs MIN 0 3.135 0.9975 2.2 V SS - 0.3 V IH_FSC_ TEST 3.3 V +/-5% 2 VIH _FSC _1 3.3 V +/-5% 0.7 V IH_F SAB_1 3.3 V +/-5% 0.7 V IL_F S 3.3 V +/-5% V SS - 0.3 0.35 V IIN V IN = VD D , V IN = GND Inputs with pull up or pull down resistors V IN = VD D , V IN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Full Active, CL = Full load; IDD 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V R ail M1 Mode, IO Rail Power down mode, 3.3V Rail, B63b0 = '1' Power down mode, IO Rail VD D = 3.3 V -5 5 uA -200 200 uA 0.4 200 80 65 10 25 0.1 15 7 5 6 6 V V mA mA mA mA mA mA MHz nH pF pF pF 1.8 ms 400 0 ns us 10 ns 10 10 5.5 0.4 ns ns V V Input Leakage Current IINR ES Output High Voltage Output Low Voltage VOHSE V OL SE Operating Supply Current iAMT Mode Current Powerdown C urrent Input Frequency Pin Inductance Input Capacitance ID DOP3.3 IDD OPIO ID DiAMT3 .3 ID DiAMTIO IDD PD3.3 IDD PDIO Fi Lpin CIN COUT CINX Clk Stabilization T STAB Tdrive_CR_off Tdrive_CR_on T DR CR OF F T DR CR ON Tdrive_CPU T DR SRC Tfall_SE Trise_SE SMBus Voltage Low-level Output Voltage C urrent sinking at V OL SMB = 0.4 V SCLK/SD ATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time T FALL T RISE VD D V OL SMB Maximum SMBus Operating Frequency F SMBU S Spread Spectrum Modulation Frequency fSSMOD Logic Inputs Output pin capacitance X1 & X2 pins From VDD Pow er-U p or de-assertion of PD to 1st clock Output stop after C R deasserted Output run after CR asserted CPU output enable after PCI_STOP# de-assertion Fall/rise time of all 3.3V control inputs from 2080%. Inputs must be monot onic IPUL LUP T RI2 C T F I2C TYP 25 3.3 1.05 1.5 2.4 135 72 53 7 22 0.01 14.31818 1.5 1.2 2.7 4 30 Notes V 8 V 8 10 3 3 2 1 1 mA (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Triangular Modulation UNITS °C V V V V V @ IPULL UP SMB Data Pin MAX 70 3.465 3.465 VD D + 0.3 0.8 32.54 1000 ns 300 ns 100 kHz 33 kHz NOTES on D C Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors 3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN , ITP_EN, SCLKL, SDATA, TESTMOD E, TESTSEL, CKPWRGD and CR# inputs if selected. 4 Intentionally blank 5 Maximum VIH is not to exceed VDD 6 H uman Body Model 7 Operation under these conditions is neither implied, nor guaranteed. 8 Frequency Select pins which have tri-level input 1 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 8 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy SYMBOL ppm Clock period Tper io d Absolute min/max period Ta bs Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay Duty C ycle Jitter, Cycle to cycle tSLR tF LR tske w tske w dt1 t jcyc- cyc CONDITION S see Tperiod min-max values 33.33MHz output no spread 33.33MHz output spread 33.33MHz output no spread 33.33MH z output nominal/spread Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V V T = 1.5 V V T = 1.5 V MIN -100 29.99700 30.08421 29.49700 29.56617 1 1 100 45 TYP 0 1.71 1.78 187 51 103 MAX 100 30.00300 30.23459 30.50300 30.58421 4 4 250 300 55 500 UNITS ppm ns ns ns ns V/ns V/ns ps ps % ps MAX 100 20.83542 21.18542 11.15198 10.95198 2 2 55 350 UNITS ppm ns ns V V V/ns V/ns % ps MAX 100 69.86224 70.84800 38.46654 38.26654 4 4 55 1000 UNITS ppm ns ns V V V/ns V/ns % ps NOTES 1,2 2 2 2 2 1 1 2 2 2 2 Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period C LK High Time CLK Low time Rising Edge Slew Rate Falling Edge Slew Rate Duty C ycle Jitter, Cycle to cycle SYMBOL ppm Tper io d Ta bs THI GH T LOW tSLR tF LR dt1 t jcyc- cyc CONDITION S see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V MIN -100 20.83125 20.48125 8.216563 7.816563 1 1 45 TYP 0 1.2 1.3 50.8% 132.2 NOTES 2,4 2,3 2 1 1 2 2 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period C LK High Time CLK Low time Rising Edge Slew Rate Falling Edge Slew Rate Duty C ycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs THIGH TLOW tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator MIN -100 69.82033 69.83400 29.97543 29.57543 1 1 45 TYP 0 1.4 1.7 53.1 138 Notes 2, 4 2, 3 2 1 1 2 2 1118N—05/19/11 9 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Electrical Characteristics - SE1/2=25MHz PARAMETER Long Accuracy Clock period Absolute min/max period Rising Edge Slew Rate Falling Edge Slew Rate Duty C ycle Jitter, Cycle to cycle Jitter, Long Term SYMBOL ppm Tper io d Ta bs tSLR tF LR dt1 t jcyc- cyc tLT J CONDITION S see Tperiod min-max values 25.00MHz output nominal 25.00MHz output nominal Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V V T = 1.5 V V T = 1.5 V V T = 1.5 V @ 10us delay MIN -100 39.99600 39.32360 1 1 45 TYP 0 1.2 1.3 50.8 60 780 MAX 100 40.00400 40.67640 2 2 55 500 1000 UNITS ppm ns ns V/ns V/ns % ps ps NOTES 1,2 1 1 1 1 1 1 1 NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 Edge rate in system is measured from 0.8V to 2.0V. Duty cycle, Peroid and Jitter are measured with respect to 1.5V 3 The average period over any 1us period of time 4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz 2 Table 1: CPU Frequency Select Table 2 1 1 FSLB B0b6 0 0 1 1 0 0 1 1 FSLC B0b7 0 0 0 0 1 1 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 CPU MHz SRC MHz PCI MHz REF MHz USB MHz DOT MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: PLL3 Quick Configuration Pin 17 Pin 18 MHz MHz 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A 1 N/A N/A B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 Spread Comment % PLL 3 disabled 0.5% Down Spread SRCCLK1 from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator N/A 1118N—05/19/11 10 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1 Table 4: Device ID table B8b7 B8b6 B8b5 B8b4 Comment 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 56 pin TSSOP/QFN 64 pin TSSOP/QFN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 11 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information PCI_STOP# Power Management Single-ended Clocks SMBus OE Bit PCI_STOP# 1 Stop Drive Mode X Stoppable Running Free running Running Low Low 0 Enable 0 1 Disable X Low X Differential Clocks (Except CPU) Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low CK= Pull down, CK# = Low CPU_STOP# Power Management SMBus OE Bit PCI_STOP# Stop Drive Mode 1 X 0 Enable 0 1 Disable X X CR# 1 0 X Stop Drive Mode Differential Clocks Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low Low CR# Power Management SMBus OE Bit Enable Disable X Differential Clocks Stoppable Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low PD# Power Management Differential Clocks (Except CPU1) CPU1 Latches Open CK= Pull down, CK# = Low CK= Pull down, CK# = Low Power Down CK= Pull down CK# = Low CK= Pull down CK# = Low M1 CK= Pull down CK# = Low Running Virtual Power Cycle to Latches Open CK= Pull down, CK# = Low CK= Pull down, CK# = Low Single-ended Clocks Device State w/o Latched input w/Latched input Low Hi-Z IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 12 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information General SMBus serial interface information for the ICS9LPR501 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator Not acknowledge stoP bit 1118N—05/19/11 13 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 Pin - Name FSLC FSLB FSLA Type R R R Reserved SRC_Main_SEL Description CPU Freq. Sel. Bit (Most Significant) CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main 4 - iAMT_EN 3 2 - 1 - SATA_SEL Select source for SATA clock 0 1 See Table 1 : CPU Frequency Select Table RW Legacy Mode iAMT Enabled RW RW SRC Main = PLL1 RW SATA = SRC_Main SRC Main = PLL3 SATA = PLL2 See Note 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold 0 PD_Restore RW Configuration Not Saved power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. Note: If setting Byte 0, bit 1 to 1 to make SATA non-spreading, Byte63, bit 1 must be set to '1' first to turn on the SATA PLL. Default Latch Latch Latch 0 0 0 0 Configuration Saved 1 1 DOT96 Center spread Center spread Default 0 0 0 0 0 0 1 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 - Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down spread Down spread PCI from PLL1 Description Output enable for REF, if disabled output is Hi-Z Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from SRC_MAIN Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 14 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 5 Clock Request Enable/Configuration Register Bit Pin Name 7 CR#_A_EN 6 5 4 3 2 1 0 CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type 0 1 Default RW Disable CR#_A Enable CR#_A 0 RW RW RW RW RW RW RW CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 0 0 0 0 0 0 0 1 Enable CR#_E Enable CR#_F Enable CR#_G Enable CR#_H Default 0 0 0 0 0 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 Pin 1 0 Name CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved Type RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_H If set, SSCD (SRC1) stops with PCI_STOP# RW Free Running If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running Type R R R R R R R R 0 Type R R R R RW RW RW RW 0 Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Vendor ID ICS is 0001, binary 1 Default X X X X 0 0 0 1 1 Default 0 0 0 1 0 0 0 0 Vendor specific Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Output enable for SE2 See Device ID Table Disabled Disabled Enabled Enabled Type 0 Free running R RW RW normal operation 1X (2Loads) Outputs HI-Z 1 Stops with PCI_STOP# assertion no overclocking 2X (3 Loads) Outputs = REF/N Default RW RW Normal operation Test mode 0 Byte 9 Output Control Register Bit Pin Name 7 PCIF5 STOP EN 6 5 4 TME_Readback REF Strength Test Mode Select 3 Test Mode Entry 2 1 0 IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator RW RW RW See Table 3: V_IO Selection (Default is 0.8V) 0 0 1 0 1 0 1 1118N—05/19/11 15 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 10 CK505 Rev 0.85 Functions (ICS Rev H Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running 1 SRC5 Enabled TBD TBD TBD TBD TBD Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Type RW RW RW RW RW RW R RW 0 TBD TBD TBD TBD Off in iAMT Off in iAMT PCIe Gen1 compliant Free Running 1 TBD TBD TBD TBD Free running in iAMT Free running in iAMT PCIe Gen2 compliant Stoppable Default 0 0 0 0 0 1 0 1 Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW 0 - 1 - Default X X X X X X X X 0 - 1 - Default X X X X X X X X Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved CPU2_iAMT_EN CPU1_iAMT_EN PCIe-Gen2 CPU2 Stop Enable Description Reserved Enables CPU2(ITP) output in iAMT state (M1) Enables CPU1 output in iAMT state (M1) PCIe-Gen2 status Enables control of CPU2(ITP) with CPU_STOP# Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Read Back byte count register Byte 13 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 Byte 14 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Byte 15 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator Type RW RW RW RW RW RW RW RW 0 - 1 - Default X X X X X X X X 1118N—05/19/11 16 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 16 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 x X X X X X X Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW 0 - 1 - Default X X X X X X X X 0 - 1 - Default X X X X X X X X Type RW RW RW RW RW RW RW RW 0 - 1 - Default X X X X X X X X Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 Disable Disable Enable Enable Default 0 0 0 0 0 0 0 0 These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 17 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Description N Divider 8 N Divider 9 Byte 18 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Description Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Byte 19 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 20 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 21 M/N Enables Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved M/N Enable CPU M/N Enable SRC/PCI Description IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 17 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 22 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 8 N Div bit 9 M Div Bit 5 M Div Bit 4 M Div Bit 3 M Div Bit 2 M Div Bit 1 M Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 - 1 - Default X X X X X X X X Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 - 1 - Default X X X X X X X X 0 1 off off on on Default 0 0 0 0 0 0 Note 1 Byte 23 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 7 N Div bit 6 N Div bit 5 N Div bit 4 N Div bit 3 N Div bit 2 N Div bit 1 N Div Bit 0 Bytes 24-62 Reserved Byte 63 Special Power Management Features (Rev P Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved SATA PLL XTAL PD Control Description Power Management Feature Controls XTAL on/off in legacy PD RW RW RW RW RW RW RW RW RW Note: Default is "off" for Rev P Silicon and higher. *Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N—05/19/11 18 ICS9LPR501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Test Clarification Table Comments HW SW FSLB/ TEST TEST_MOD FSLC/ ENTRY BIT E TEST_SEL B9b3 HW PIN HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control REF/N or HI-Z B9b4 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N