ICS1524AM

Integrated Circuit Systems, Inc. ICS1524A Dual Output Phase Controlled SSTL_3/PECL Clock Generator General Description Features The ICS1524A is a low-cost, very high-performance • frequency generator and phase controlled clock synthesizer. It is perfectly suited to phase controlled clock • synthesis and distribution as well as line-locked and • genlocked applications. • The ICS1524A offers two channels of clock phase controlled outputs; CLK and DPACLK. These two output channels have both 250 MHz PECL differential and 150 MHz SSTL_3 single-ended output pins. The CLK output channel has a fixed phase relationship to the PLL’s input • and the DPACLK uses the Dynamic Phase Adjust cir• cuitry to allow control of the clock phase relative to input • signal. Optionally, the CLK outputs can operate at half the clock rate and phase aligned with the DPACLK channel, enabling deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. • Dynamic Phase Adjust (DPA) for DPACLK outputs • Software controlled phase adjustment • 360o Adjustment down to 1/64 clock increments External or internal loop filter selection Uses 3.3 VDC Inputs are 5 volt tolerant. I2C-bus serial interface runs at either low speed (100 kHz) or high speed (400 kHz). Hardware and Software PLL Lock detection • Generic Frequency Synthesis • LCD Monitors and Projectors • Genlocking Multiple Video Systems VDDD VSSD SDA SCL PDEN EXTFB HSYNC EXTFIL XFILRET VDDA VSSA OSC 1 2 3 4 5 6 7 8 9 10 11 12 ICS1524A DPACLK DPACLK+/FUNC I2C 150 MHz single-ended SSTL_3 clock outputs Pin Configuration CLK CLK+/- OSC 250 MHz balanced PECL differential outputs NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Loop Filter HSYNC • 8 kHz to 100 MHz Applications The advanced PLL uses either its internal programmable feedback divider or an external divider and is programmed by a standard I2C-bus™ serial interface. Block Diagram Wide input frequency range 24 23 22 21 20 19 18 17 16 15 14 13 IREF CLK+ (PECL) CLK– (PECL) DPACLK+ (PECL) DPACLK– (PECL) VSSQ VDDQ DPACLK (SSTL) CLK (SSTL) FUNC (SSTL) LOCK/REF (SSTL) I2CADR 24 Pin 300-mil SOIC 2 I C-bus is a trademark of Philips Corporation. ICS1524A Rev E 08/10/09 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS1524A Document Revision History Rev A ICS1523 Rev T Datasheet used as a starting template New Block Diagram substituted for old 1523 one Removed reference to CLK / 2 Functionality Created a set of clock outputs that bypass the DPA External PDEN is now the IN-SEL MUX control bit Text descriptions changed to support new 1524 block diagram Rev B Replaced page 15 “Layout Guidelines” Replaced SIOC Package diagram on page 22 “Advanced Status” removed Redrew front page graphics for clairity Rev C Corrected Chip Revision and Chip Version values on page 5 Changed Title on Page 1 Minor format changes to pages 8 and 21 Corrected pin names on page 10 Rev D Miscellaneous updates to Block Diagram on page 3 Changed reference from “Phase Detector” to “Charge Pump”. Pages 4-7, 10 ICS1524A Rev E 08/10/09 2 Fbk_Sel Reg 0x0:4 Ref_Pol Reg 0x0:2 In_Sel Reg 0x7:7 Fbk_Pol Reg 0x0:3 Osc_Div Reg 0x7:0-6 LOCK/REF PDEN Reg 0x0:0 3 Fill_Sel Reg 0x4:7 Func_Sel Reg 0x0:5 FBD DPA_Res Reg 0x3:0-3 Reg 0x5:0-1 FBD Reg 0x2:0-7 DPA_OS Reg 0x4:0-5 DPA_LOCK REG 12:0 PFD Reg 0x1:0-2 PD_Pol Reg 0x0:1 PDEN PLL_LOCK REG 12:1 EnDLS Reg 0:7 EnPLS Reg 0:6 Ck2_Inv Reg 6:5 DPACLK CLK DPACLKOE_Pck Reg 0x6:0 DPACLK+ OE_Tck Reg 0x6:1 OE_F Reg 0x6:4 OE_P2 Reg 0x6:2 CLK- OE_T2 Reg 0x6:3 CLK+ PSD Reg 0x1:4-5 Out_Scl Reg 0x6:6-7 MUX Divider POST SCALER ICS1524A Block Diagram ICS1524A Rev E 08/10/09 ICS1524A Pin Descriptions PIN NO. P I N NA M E TYPE DESCRIPTION COMMENTS 1 VDDD PWR Digital supply 2 VSSD PWR Digital ground 3.3V to digital sections Ground for digital sections 3 S DA IN/OUT Serial data I 2 C - bu s 1 4 SCL IN Serial clock I 2 C - bu s 1 5 PDEN IN C h a rg e P u m p S u s p e n d s c h a rg e p u m p 1 6 EXTFB IN External feedback External divider input to P F D 1 7 HSYNC IN Horizontal sync Clock input to PLL1 8 EXTFIL IN External filter External PLL loop filter 9 XFILRET IN External filter return External PLL loop filter return 10 V D DA PWR Analog supply 3.3V for analog circuitry PWR 11 VSSA Analog ground Ground for analog circuitry 12 OSC IN Oscillator I n p u t f r o m c r y s t a l o s c i l l a t o r p a c k a g e 1, 2 13 I 2C A D R IN I 2C a d d r e s s C h i p I 2C a d d r e s s s e l e c t Low = 4Dh read, 4Ch write High = 4Fh read, 4Eh write 14 LOCK/REF SSTL Lock indicator/reference Displays PLL or DPA lock or REF input 15 FUNC SSTL Function output SSTL_3 selectable HSYNC output 16 CLK SSTL P i xe l c l o c k t Non-Delayed SSTL_3 Clock 17 D PAC L K SSTL DPA Delayed Clock DPA Delayed SSTL_3 Clock 18 VDDQ PWR Output driver supply 3.3V VDD for output drivers 19 VSSQ PWR Output driver ground Ground for output drivers 20 D PAC L K – PECL DPA Delayed PECL clock - DPA Delayed Inverted PECL Clock Open drain. 21 D PAC L K + PECL DPA Delayed PECL clock + DPA Delayed PECL Clock 22 CLK– PECL PECL clock - Non-Delayed Inverted PECL Clock Open drain. 23 CLK+ PECL PECL clock + Non-Delayed PECL Clock Open drain. 24 IREF IN Reference current Reference current for PECL outputs Notes: 1. These LVTTL inputs are 5 V-tolerant. 2. Connect to ground if unused. ICS1524A Rev E 08/10/09 4 Open drain. ICS1524A I2C Register Map Summary Register Index 0h 1h Name Input Control Loop Control Access R/W R/W* 2h FdBk Div 0 R/W* 3h FdBk Div 1 R/W* 4h 5h DPA Offset DPA Control R/W Bit Name Bit # Reset Value PDen 0 1 Charge Pump Enable PD_Pol 1 0 Charge Pump Enable Polarity 7h 8h Output Enables Ref_Pol 2 0 External Reference Polarity (0=Positive Edge, 1=Negative Edge) 3 0 External Feedback Polarity (0=Positive Edge, 1=Negative Edge) Fbk_Sel 4 0 External Feedback Select Func_Sel 5 0 Function Out Select Osc_Div Reset R/W Write (0=Internal Feedback, 1=External) (0=Recovered HSYNC, 1=Input HSYNC) EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable) EnDLS 7 0 Enable DPA Lock/Ref Status Output (0=Disable 1=Enable) PFD0-2 0-2 0 Charge Pump Gain Reserved 3 0 Reserved PSD0-1 4-5 0 Post-Scaler Divider Reserved 6-7 0 Reserved FBD0-7 0-7 FF (0 = /2, 1 = /4, 2 = /8, 3 = /16) PLL FeedBack Divider LSBs (bits 0-7) * FBD8-11 0-3 F PLL Feedback Divider MSBs (bits 8-11) * Reserved 4-7 0 Reserved DPA_OS0-5 0-5 0 Dynamic Phase Aligner Offset Reserved 6 0 Reserved Fil_Sel 7 1 Loop Filter Select R / W ** DPA_Res0-1 R/W (0=Disable 1=Enable) Fbk_Pol Metal_Rev 6h Description (0=External, 1=Internal) 0-1 3 DPA Resolution 2-7 0 Metal Mask Revision Number (0=16 delay elements, 1=32, 2=Reserved, 3=64) OE_Pck 0 1 Output Enable for PECL DPACLK ( 0=High Z, 1=Enabled) OE_Tck 1 1 Output Enable for STTL_3 DPACLK ( 0=High Z, 1=Enabled) OE_P2 2 1 Output Enable for PECL CLK ( 0=High Z, 1=Enabled) OE_T2 3 1 Output Enable for STTL_3 CLK ( 0=High Z, 1=Enabled) ( 0=High Z, 1=Enabled) OE_F 4 1 Output Enable for STTL_3 FUNC Ck2_Inv 5 0 Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins Out_Scl 6-7 0 SSTL DPACLK (Pin 17) Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8) Osc_Div 0-6 0-6 0 Osc Divider modulus In-Sel 7 1 RESERVED DPA 0-3 x Writing xA hex resets DPA and loads working register 5 PLL 4-7 x Writing 5x hex resets PLL and loads working registers 1-3 10h Chip Ver Read Chip Ver 0-7 18 Chip Version 17 hex 11h Chip Rev Read Chip Rev 0-7 01 Chip Revision C2 hex 12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked) PLL_Lock 1 N/A PLL Lock Status (0=Unlocked, 1=Locked) Reserved 2-7 0 Reserved * Identifies double-buffered registers. Working registers are loaded during software PLL reset. ** Identifies double-buffered register. Working registers are loaded during software DPA reset. ICS1524A Rev E 08/10/09 5 ICS1524A Detailed Register Description Name: Register: Index: Input Control 0h Read / Write Bit Name Bit # Reset Value Description PDen PD_Pol Ref_Pol Fbk_Pol Fbk_Sel Func_Sel EnPLS EnDLS 0 1 2 3 4 5 6 7 1 0 0 0 0 0 1 0 Charge Pump Enable Charge Pump Enable Polarity External Reference Polarity External Reference Feedback Polarity External Feedback Select Function Output Select Enable PLL Lock Status Output on LOCK/REF pin Enable DPA Lock Status Output on LOCK/REF pin Bit Name Description 0 PDen 1 PD_Pol 2 Ref_Pol Charge Pump Enable 0 = External Enable via PDEN pin 1 = Always Enable Charge Pump Enable Polarity 0 = Active High 1 = Active Low External Reference Polarity — Edge of input signal on which Phase/Frequency Detector triggers. 0 = Rising Edge (default) 1 = Falling Edge 3 Fbk_Pol External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default) 1 = Negative Edge 4 Fbk_Sel External Feedback Select 0 = Internal Feedback (default) 1 = External Feedback 5 Func_Sel Function Output Select — Selects re-clocked output to FUNC (pin 15). 0 = Recovered HSYNC (default). Regenerated HSYNC output. 1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7). 6 EnPLS Enable LOCK/REF (pin14) Output 7 EnDLS ICS1524A Rev E 08/10/09 EnPLS EnDLS IN_SEL LOCK/REF(14) 0 0 N/A 0 0 1 N/A 1 if DPA locked, 0 otherwise 1 0 N / A 1 i f P L L l o c ke d , 0 o t h e r w i s e Post Schmitt trigger 1 1 0 HSYNC(7) XOR Ref_Pol 1 1 1 Fosc ÷ Osc_Div 6 ICS1524A Name: Register: Index: Loop Control Register 1h Read / Write* Bit Name Bit # Reset Value Description PFD0-2 Reserved PSD 0-1 Reserved 0-2 3 4-5 6 -7 0 0 0 0 Charge Pump Gain Reserved Post-Scaler Divider Reserved Bit Name Description 0-2 PFD0-2 Charge Pump Gain 3 Reserved 4-5 PSD 0-1 6-7 Bit 2 Bit 1 Bit 0 CP Ga i n ( µ A/ 2 π r a d ) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider. Bit 5 Bit 4 PSD Divider 0 0 1 1 0 1 0 1 2 (default) 4 8 16 Reserved * Double-buffered register. Actual working registers are loaded during software PLL reset. See register 8h for details. ICS1524A Rev E 08/10/09 7 ICS1524A Name: Register: Index: Feedback Divider 0 Register / Feedback Divider 1 Register 2h, 3h Read / Write* Bit Name Index Bit # Reset Value FBD 0-7 2 0 -7 FF FBD 8 -11 Reserved 3 3 0 -3 4 -7 F Description PLL Feedback Divider LSBs (0 -7).* When Bit 0 = 0, then the total number of clocks per line is even. When Bit 0 = 1, then the total number of clocks is odd. PLL Feedback Divider MSBs (8 -11)* Reserved The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS 1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8. Reg 3 2 1 3 Feedback Divider Modulus 0 7 6 5 Reg 2 4 3 2 1 0 +8 = 12 ≤ Feedback Divider Modulus ≤ 4103 * Double-buffered registers. Actual working registers are loaded during software PLL reset. See Register 8h for details. Name: Register: Index: DPA Offset Register 4h Read / Write Bit Name Bit # Reset Value DPA_OS0-5 Reserved Fil_Sel Bit 0-5 6 7 Name 0 0 0 Description Dynamic Phase Adjust Offset Reserved Loop Filter Select Description 0-5 DPA_OS0-5 Dynamic Phase Adjust Offset. Selects clock edge offset in discrete steps from zero to one clock period minus one step. Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1). Note: Offsets equal to or greater than one clock period are neither recommended nor supported. Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps. 7 Fil_Sel Selects external loop filter (0) or internal loop filter (1). The use of an external loop filter is strongly recommended for all designs. Typical loop filter values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. ICS1524A Rev E 08/10/09 8 ICS1524A Name: Register: Index: Bit Name DPA Control Register 5h Read / Write* Bit # Reset Value 0-1 2- 7 3 0 DPA_Res 0-1 Metal_Rev Description Dynamic Phase Adjust Resolution Select. Metal Mask Revision Number. Bit Name Description 0-1 DPA_Res 0 -1 Dynamic Phase Adjust (DPA) Resolution Select. It is not recommended to use the DPA above 160 MHz. Bit 1 0 0 1 1 2-7 Metal_Rev Bit 0 0 1 0 1 CLK Range, MHz 48 24 80 Delay Elements 16 32 Reserved 64 12 160 40 Metal Mask Revision Number. After power-up, register bits 7:2 must be written with 111111. After this write, a read indicates the metal mask revision, as below. Revision Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 A B C1 C2 D E F G 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 * Double-buffered register. Actual working registers are loaded during software DPA reset. See register 8h for details. ICS1524A Rev E 08/10/09 9 ICS1524A Name: Register: Index: Output Enable Register 6h Read / Write Bit Name Bit # Reset Value Description OE_Pck OE_Tck OE_P2 OE_T2 OE_F CK2_Inv Out_Scl 0 1 2 3 4 5 6-7 0 0 0 0 0 0 0 Output Enable for DPACLK Outputs (PECL, Pins 21, 20 ) Output Enable for DPACLK Output (SSTL_3 Pin 17) Output Enable for CLK Outputs (PECL, Pins 23, 22) Output Enable for CLK Output (SSTL_3, Pin 16) Output Enable for FUNC Output (SSTL_3, Pin 15) Select CLK Output Source (Pins 23, 22, 16) DPACLK Output Scaler (SSTL_3, Pin 17) Bit Name Description 0 OE_Pck Output Enable for DPACLK Outputs (PECL) 0 = High Z 1 = Enabled 1 OE_Tck Output Enable for DPACLK Output (SSTL_3) 0 = High Z 1 = Enabled 2 OE_P2 Output Enable for CLK Outputs (PECL) 0 = High Z 1 = Enabled 3 OE_T2 Output Enable for CLK Output (SSTL_3) 0 = High Z 1 = Enabled 4 OE_F Output Enable for FUNC Output (SSTL_3) 0 = High Z 1 = Enabled 5 Ck2_Inv Select CLK Output Source (Pins 23, 22, 16) 0 = Half Speed DPA Delayed clock to CLK outputs 1 = Full Speed non-DPA Delayed clock to CLK outputs 6 -7 Out_Scl Clock (DPACLK, pin 17) Scaler ICS1524A Rev E 08/10/09 Bit 7 Bit 6 0 0 1 1 0 1 0 1 DPACLK Divider 1 2 4 8 10 ICS1524A Name: Register: Index: Oscillator Divider Register 7h Read / Write Bit Name Bit # Reset Value Osc_Div 0-6 In_Sel 0-6 7 0 1 Description Osc Divider Modulus Input Select Bit Name Description 0-6 Osc_Div 0-6 Oscillator Divider Modulus. Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. 7 In_Sel Input Select — Selects the input to the Phase/Frequency Detector 0 = HSYNC 1 = Osc Divider Name: Register: Index: RESET Register 8h Write Bit Name Bit # Reset Value DPA Reset PLL Reset 0 -3 4 -7 x x Description Writing xAh to this register resets DPA working register 5 Writing 5xh to this register resets PLL working registers 1-3 Bit Name Description 0 -3 DPA Writing xAh to this register resets DPA working register 5 4 -7 PLL Writing 5xh to this register resets PLL working registers 1-3 Value Resets xA 5x 5A DPA PLL DPA and PLL ICS1524A Rev E 08/10/09 11 ICS1524A Name: Register: Index: Bit Name Chip Version Register 10 h Read Bit # Reset Value 0-7 17 Chip Ver Name: Register: Index: Bit Name Chip Rev Name: Register: Index: Bit Name DPA_Lock PLL_Lock Reserved Description Chip Version 24 (18h ) Chip Revision Register 11h Read Bit # Reset Value 0 -7 01+ Description Initial value 01h. +Value increments with each all-layer change. Status Register 12 h Read Bit # Reset Value 0 1 2 -7 N/A N/A 0 Description DPA Lock Status PLL Lock Status Reserved Bit Name Description 0 DPA_Lock DPA Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked 1 PLL_Lock PLL Lock Status. (Refer to Register 0h, bits 6 and 7.) 0 = Unlocked 1 = Locked 2 -7 Reserved ICS1524A Rev E 08/10/09 12 ICS1524A I2C Data Characteristics Bit transfer on the I2C-bus START and STOP conditions Acknowledge on the I2C-bus These waveforms are from "The I2 C-bus and how to use it," published by Philips Semiconductor. The document can be obtained from http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf ICS1524A Rev E 08/10/09 13 ICS1524A I2C Data Format RANDOM REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 x W A 7 bit address START condition A register address Acknowledge WRITE command A P data Acknowledge STOP condition Acknowledge RANDOM REGISTER READ PROCEDURE S 0 1 0 0 1 1 X W A 7 bit address START condition register address Acknowledge WRITE command A S 0 1 0 0 1 1 X R A 7 bit address data Repeat START Acknowledge Acknowledge READ command A P STOP condition NO Acknowledge SEQUENTIAL REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 X W A 7 bit address START condition A register address Acknowledge WRITE command A A data Acknowledge data Acknowledge A P Acknowledge Acknowledge STOP condition SEQUENTIAL REGISTER READ PROCEDURE S 0 1 0 0 1 1 X W A 7 bit address START condition Direction: register address Acknowledge WRITE command From bus host to device A S 0 1 0 0 1 1 X R A 7 bit address data Repeat START Acknowledge Acknowledge READ command A A P data NO Acknowledge Acknowledge STOP condition From device to bus host Note: 1. All values are transmitted with the most-significant bit first and the least-significant bit last. 2. The value of the X bit equals the logic state of pin 13 (I2CADR). 3. R = READ = 1 and W = WRITE = 0 ICS1524A Rev E 08/10/09 14 ICS1524A General Layout Guidelines • Use a PC board with at least four layers: one power, one ground, and two signal. • Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling. • All supply voltages must be supplied from a common source and must ramp together. • Any flux or other board surface debris can degrade the performance of the external loop filter. • Ensure that the 1524A area of the board is free of contaminants. Specific Layout Guidelines 1. Digital Supply (VDD) – Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-µF capacitor, located as close as possible to the pins. A 0.01-µF capacitor may be added for additional high frequency rejection. 2. External Loop Filter – Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9 (EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful to isolate this section from the rest of the board. 3. Analog PLL Supply (VDDA) – Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7-µF. Bypass pin 10 to pin 11 (VSSA) with a 0.1-µF capacitor. A 0.01-µF capacitor may be added for additional high frequency rejection. Locate these components as close as possible to the pins. 4. PECL Current Set Resistor – Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1 -µF capacitor. . 5. PECL Outputs – Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Ohm characteristic impedance. Locate any optional series “snubbing” resistors as close as possible to the source pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes. [These termination resistors are omitted if the load device implements them internally. For details, see the ICS application note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing a Custom Interface for the ICS1523 (1523AN4.)] 6. Output Driver Supply – Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-µF capacitor, located as close as possible to the pins. A 0.01-µF capacitor may be added for additional high frequency rejection. 7. SSTL_3 Outputs – SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, “PECL Outputs” apply. See JEDEC documents JESD8-A and JESD8-8. ICS1524A Rev E 08/10/09 15 ICS1524A PECL Outputs For information on using the ICS1524A’s PECL output pins, please refer to Application Note 4: Designing a Custom PECL Interface for the ICS1523 SSTL_3 Outputs Unterminated Outputs In the ICS1524A, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these single-ended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz. Terminated Outputs SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1524A SSTL outputs are only slightly improved by termination in a low impedance. The ICS1524A SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Ohms reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs. VDD ICS1524A SSTL-3 Output 330Ω 150Ω Single LVTTL Load For more information on using the ICS1524A’s SSTL output pins, please refer to Application Note 3: Using SSTL_3 Outputs with CMOS or LVTTL Inputs ICS1524A Rev E 08/10/09 16 ICS1524A Power Supply Considerations The ICS1524A incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1524A, the supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms should be sufficient. Supply Voltage Vmin td Vt h = 1.8V Absolute Maximum Ratings VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 V VSS – 0.3V to 5.5V VSSA – 0.3V to VDDA +0.3V VSSQ – 0.3V to VDDQ +0.3V – 65°C to +150°C 175°C 260°C ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV (*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.) ICS1524A Rev E 08/10/09 17 ICS1524A Recommended Operating Conditions VDD, VDDQ, VDDA (measured to VSS) . 3.0 to 3.6 V Operating Temperature (Ambient) . . . . . . 0 to +70°C DC Supply Current MI N MAX UNI TS Supply Current, Digital PA R A ME T E R S YMB OL I DDD VDDD = 3.6V CONDI TI ONS — 25 mA Supply Current, Output Drivers I DDQ VDDQ = 3.6V, no output drivers enabled. — 6 mA Supply Current, Analog I DDA VDDA = 3.6V — 5 mA Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I 2C ADR) MI N MA X UNI T S Input High Voltage PA R A ME T E R S YMB OL VI H CONDI TI ONS 2 5. 5 V Input Low Voltage VI L VS S - 0 . 3 0. 8 V Input Hysteresis 0. 2 0. 6 V IIH VIH = VDD — ± 10 µA Input Low Current IIL VIL = 0 — ± 200 µA Input Capacitance Ci n — 10 pF MI N MA X UNI T S 0. 4 V MI N MA X UNI T S IOUT = 0 — VDD V VDDD = 3.3V — 250 MH z IOUT = programmed value 1. 0 — V Input High Current SDA (In Output Mode: SDA is Bidirectional) PA R A ME T E R Output Low Voltage S YMB OL VOL CONDI TI ONS IOUT = 3 mA. VOH = 6.0V maximum as determined by the external pull-up resistor. PECL Outputs (DPACLK+, DPACLK–, CLK+, CLK -) PA R A ME T E R Output High Voltage Maximum Output Frequency Output Low Voltage (Note: VOL must not fall below the level given so that the correct value for IOUT can be maintained.) S YMB OL VOH Fp MAX VOL CONDI TI ONS SSTL-3 Outputs (DPACLK, CLK, FUNC, LOCK/REF) PA R A ME T E R Output Resistance Maximum Output Frequency S YMB OL RO Fs MAX MI N MA X UNI T S 1