ICS873039AM

PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS873039 is a low skew, high performance LVPECL-to-3.3V LVPECL / ECL Clock GeneraHiPerClockS™ tor/Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS873039 has one LVPECL differential clock input pair. The PCLK, nPCLK pair can accept LVPECL, LVDS, CML, SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 2 divide by 2/4 differential 3.3V LVPECL outputs; 2 divide by 4/6 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS873039 ideal for clock distribution applications demanding well defined performance and repeatability. • Output skew: 20ps (typical) ICS • 1 differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum input frequency: 3.2GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nPCLK input • Part-to-part skew: 85ps (typical) • Propagation delay: 690ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V • -40°C to 85°C ambient operating temperature • Compatible with MC100LVEL39 BLOCK DIAGRAM PIN ASSIGNMENT DIV_SELA PCLK nPCLK ÷2, ÷4 R VCC nEN DIV_SELB PCLK nPCLK VBB MR VCC nc DIV_SELA QA0 nQA0 QA1 nQA1 nEN ÷4, ÷6 R MR 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC QA0 nQA0 QA1 nQA1 QB2 nQB2 QB3 nQB3 VEE ICS873039 QB2 nQB2 20-Lead SOIC, 300MIL M Package 7.5mm x 12.8mm x 2.25 package body Top View QB3 nQB3 DIV_SELB V BB The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 873039AM www.icst.com/products/hiperclocks.html REV. A MAY 3, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 8, 20 VCC Power Type 2 nEN Input Description Positive supply pins. Pulldown Clock enable. Selects divide value for Bank B outputs as described in Table 3. 3 DIV_SELB Input Pulldown LVCMOS / LVTTL interface levels. 4 PCLK Input Pulldown Non-inver ting differential LVPECL clock input. Pullup/ 5 nPCLK Input Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Output Bias voltage. 6 VBB Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low, and the inver ted outputs 7 MR Input Pulldown (nQX) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 9 nc Unused No connect. Selects divide value for Bank A outputs as described in Table 3. 10 DIV_SELA Input Pulldown LVCMOS / LVTTL interface levels. Power Negative supply pin. 11 VEE 12, 13 nQB3, QB3 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. 14, 15 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output 18, 19 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units KΩ RVCC/2 Pullup/Pulldown Resistors 50 KΩ TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs Outputs MR nOE DIV_SELA DIV_SELB QA0, QA1 nQA0, nQA1 QB2, QB3 nQB2, nQB3 1 X X X LOW HIGH LOW HIGH 0 1 X X Not Switching Not Switching Not Switching Not Switching 0 0 0 0 ÷2 ÷2 ÷4 ÷4 0 0 0 1 ÷2 ÷2 ÷6 ÷6 0 0 1 0 ÷4 ÷4 ÷4 ÷4 0 0 1 1 ÷4 ÷4 ÷6 ÷6 NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge. 873039AM www.icst.com/products/hiperclocks.html 2 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Negative Supply Voltage, VEE 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5 V Inputs, VI (ECL mode) 0.5V to VEE - 0.5V Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- 50mA 100mA istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA (Junction-to-Ambient) 46.2°C/W (0 lfpm) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.8 V 65 mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VIH Input High Voltage(Single-Ended) VIL Input Low Voltage(Single-Ended) Min Min 25°C Typ 1.545 Output Voltage Reference; NOTE 2 1.86 150 1.52 1.2 150 3.3 1.2 V V 1.765 V 1200 mV 3.3 V 150 µA 1.86 800 150 1200 150 3.3 1.2 150 Units V 1.535 1.765 1200 Max 2.075 1.86 800 Min 85°C Typ 2.33 2.075 1.765 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current PCLK Input Low Current nPCLK Max 2.295 2.075 VPP IIH Max 2.275 VBB VCMR -40°C Typ V 800 -10 µA -150 -150 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. µA IIL 873039AM -10 -10 www.icst.com/products/hiperclocks.html 3 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V -40°C 25°C 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 1.475 1.495 1.53 V VOL Output Low Voltage; NOTE 1 0.745 0.72 0.735 V Min VIH Input High Voltage(Single-Ended) VIL Input Low Voltage(Single-Ended) VPP IIH Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK High Current nPCLK IIL Input Low Current VCMR Typ Max Min 1.275 Typ 1.275 PCLK 800 1.2 Min Typ 150 2.5 1.2 800 150 1200 150 2.5 1.2 800 150 -10 -10 Units V 0.965 1200 Max 1.275 0.965 150 Max 0.965 V 1200 mV 2.5 V 150 µA -10 µA -150 -150 -150 nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. µA TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V -40°C Symbol Parameter VOH Output High Voltage; NOTE 1 Min VOL Output Low Voltage; NOTE 1 VIH Input High Voltage(Single-Ended) VIL Input Low Voltage(Single-Ended) Min Typ -1.755 Output Voltage Reference; NOTE 2 -1.44 150 IIH IIL Input Low Current Max -1.78 VEE+1.2V 1200 150 0 VEE+1.2V 1200 150 0 VE E + 1 . 2 V -10 -150 -150 -150 nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. 873039AM www.icst.com/products/hiperclocks.html 4 Units V V V -1.535 V 1200 mV 0 V 150 µA -1.44 800 150 -10 Max -1.765 -1.535 150 -10 Typ -1.225 -1.44 800 Min -0.97 -1.225 -1.535 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current 85°C -1.005 -1.225 VPP PCLK Max -1.025 VBB VCMR Typ 25°C V 800 µA µA REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V Symbol Parameter -40°C Min Typ 25°C Max Min Typ Max Min Typ Input Frequency Propagation Delay; NOTE 1 690 690 690 ps tsk(o) Output Skew; NOTE 2, 4 20 20 20 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section 85 85 85 ps 0.03 0.03 0.03 ps 200 200 200 ps Output Rise/Fall Time 20% to 80% 3.2 Units fMAX tR/tF 3.2 Max tPD tjit 3.2 85°C GHz All parameters are measured ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 873039AM www.icst.com/products/hiperclocks.html 5 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V VCC V CC Qx SCOPE nPCLK V LVPECL V Cross Points PP CMR PCLK nQx VEE VEE -0.375V to -1.8V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy t sk(pp) t sk(o) OUTPUT SKEW PART-TO-PART SKEW nPCLK 80% 80% PCLK nQAx, nQBx QAx, QBx VSW I N G Clock Outputs t tR tF PD PROPAGATION DELAY 873039AM 20% 20% OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 6 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 1A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 1B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. VCC(or VDD) CLK_IN PCLK VBB nPCLK FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 873039AM www.icst.com/products/hiperclocks.html 7 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR 3.3V LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 873039AM 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 873039AM www.icst.com/products/hiperclocks.html 9 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 3.3V 2.5V 3.3V 3.3V SSTL R2 125 FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V R3 120 Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 873039AM HiPerClockS PCLK/nPCLK HiPerClockS PCL K/n PC LK R2 1K FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 10 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS873039. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873039 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 65mA = 247mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW Total Power_MAX (3.8V, with all outputs switching) = 247mW + 120.8mW = 367.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 85°C + 0.368W * 39.7°C/W = 99.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN SOIC FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 873039AM www.icst.com/products/hiperclocks.html 11 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CC_MAX • -V OH_MAX OL_MAX -V Pd_H = [(V – (V CCO_MAX OH_MAX CCO_MAX – 0.935V ) = 0.935V For logic low, VOUT = V (V =V OL_MAX =V CCO_MAX – 1.67V ) = 1.67V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO _MAX L -V OH_MAX )= [(2V - 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW 873039AM www.icst.com/products/hiperclocks.html 12 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJA VS. AIR FLOW TABLE FOR 20 LEAD SOIC θ by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W 200 500 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS873039 is: 434 873039AM www.icst.com/products/hiperclocks.html 13 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR FOR 20 LEAD SOIC TABLE 8 PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 20 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 873039AM www.icst.com/products/hiperclocks.html 14 REV. A MAY 3, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS873039 LOW SKEW, ÷2/4,÷4/6, LVPECL-TO-3.3V LVPECL / ECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number ICS873039AM ICS873039AMT Marking ICS873039AM ICS873039AM Package 20 lead SOIC 20 lead SOIC on Tape and Reel Count 38 per Tube 1000 Temperature -40°C to 85°C -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 873039AM www.icst.com/products/hiperclocks.html 15 REV. A MAY 3, 2004