ICS527R-04

DATASHEET ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB Description Features The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. • • • • • • • • • • • • • • The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers. For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02. For CMOS in and PECL out with zero delay, use the ICS527-03. Packaged as 28-pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out PECL in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5 MHz - 200 MHz Output clock frequencies up to 160 MHz Very low jitter Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram R6:R0 7 PECLIN Divide by 2 1 0 VDD 1 0 560 ohm VDD VDD 68 ohm PECLO Phase Comparator, Charge Pump, and Loop Filter Divide by 2 RES Reference Divider PECLIN FBPECL 2 180 ohm VCO Output Divider Feedback Divider VDD 68 ohm PECLO FBPECL 180 ohm IRANGE 7 F6:F0 IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 2 GND 2 S1:S0 1 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER Pin Assignment Output Frequency and Output Divider Table R5 1 28 R4 R6 2 27 R3 IR A N G E 3 26 R2 S0 4 25 S1 5 24 VDD 6 23 FBPECL 7 22 PECLO FBPECL 8 21 PECLO GND 9 20 GND P E C L IN 10 19 RES P E C L IN 11 18 F6 F0 12 17 F5 F1 13 16 F4 IRANGE Criteria F2 14 15 F3 0 if (FBPECL < 80 MHz) and (PECLIN < 80 MHz) 1 if (FBPECL > 80 MHz) or (PECLIN > 80 MHz) R1 S1 Pin 5 S0 Pin 4 Output Frequency (MHz) PECLO Output Pair R0 0 0 10 - 80 VDD 0 1 5 - 40 1 0 2.5 - 20 1 1 20 -160 IRANGE Setting Table 28-pin (150 mil) SSOP Pin Descriptions Pin Number Pin Name Pin Type 1-2 24 - 28 R5, R6, R0-R4 Input Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up. 3 IRANGE Input Set for proper frequency range of input clocks. See table above. 4-5 S0, S1 Input Select pins for output frequency range. See table above. Internal pull-up. 6, 23 VDD Power Connect to +3.3 V. 7 FBPECL Input PECL feedback input to PLL. 8 FBPECL Input PECL feedback input to PLL. 9, 20 GND Power Connect to ground 10 PECLIN Input PECL input clock. 11 PECLIN Input Complementary PECL input clock. 12 - 18 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up 19 RES BIAS Resistor connection to VDD for setting level of PECL outputs. 21 PECLO Output Complementary PECL output. 22 PECLO Output PECL output. Rising edge aligns with PECLIN when connected directly to FBPECL. Pin Description IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 2 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER External Components Decoupling Capacitors set. The ICS527-04 requires two 0.01µF decoupling capacitors to be connected between VDD and GND, one on each side of the chip. They must be connected close to the device to minimize lead inductance. The output levels can be adjusted for different output and load impedances. Refer to application note MAN09 for more information on the RES and resistor network values for the output clocks. Determining ICS527-04 Divider Settings The user has full control in setting the desired output clock over the range shown in the table on page 2. The user should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout, so that the ICS527-04 automatically produces the correct clock when all components are soldered. It is also possible to connect the inputs to parallel I/O ports in order to switch frequencies. The configuration inputs: IRANGE, S1, S0, R6...0, F6...0 are compatible with CMOS or TTL levels. PECL Termination Networks The PECLO to FBPECL and PECLO to FBPECL connections should be made directly underneath the device, unless feedback is being routed through other devices. The resistor divider networks should be placed as close to the outputs as possible. The output of the ICS527-04 can be determined by the following simple equation: Typical 50 Ω termination is shown in the Block Diagram on page 1. For other termination schemes, see MAN09.pdf. FDW + 2 FB Frequency = Input Frequency × ------------------------ RDW + 2 Eliminating the Delay Through Buffers or Other Components Where: More complicated feedback schemes can be used, such as incorporating low skew, multiple output buffers in the feedback path. An example of this is given later in the datasheet. The fundamental property of the ICS527-04 is that it aligns rising edges on CLKIN and FBPECL at a ratio determined by the reference and feedback dividers. This means that any delay in the feedback path will cause the PECL output edge to lead PECLIN by the delay amount. So, by taking the PECL output from another device as the input to FBPECL, the delay through the other device can be eliminated. Reference Divider Word (RDW) = 0 to 127 Feedback Divider Word (FDW) = 0 to 127 FB Frequency is the same as the output frequency Additionally, the following operating ranges should be observed: Input Frequency 300kHz < ------------------------------------------RDW + 2 Setting the Clock Slicer Use IRANGE to select the input frequency range. If either the PECLIN or FBPECL pair frequencies are greater than (or equal to) 80 MHz, connect IRANGE to VDD, or let it float. If both frequencies are less than 80 MHz, connect IRANGE to ground. S1 and S0 should be selected depending on the output frequency. The table on page 2 gives the ranges. The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a 40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider word (FDW) should be 3 which gives the required 5/4 multiplication. If multiple choices Choose S1 and S0 from the table on page 2, depending on the output frequency. Finally, the divider settings should be selected. Following is a description of how the dividers should be IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 3 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER If you need assistance determining the optimum divider settings, please send an e-mail to ics-mk@icst.com with the desired input clock and the desired output frequency. of dividers are available, then the lowest numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0 is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Typical Example The following connection diagram shows the implementation of the example from the previous section. This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will produce the waveforms shown on the bottom of the example. VDD 0.01 F R5 R4 R6 R3 IRANGE R2 S0 R1 S1 R0 VDD FBPECL FBPECL 0.01 F VDD VDD PECL 50 MHz PECL GND GND 40 MHz PECLIN RES 40 MHz PECLIN F6 F0 F5 F1 F4 F2 F3 180 PECL output resistor network (50 ohm) is not shown, but is identical to PECL 560 40 MHz (PECLIN shown) 50 MHz PECL 50 MHz PECL IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 4 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER Multiple Output Example VDD R4 R6 R3 IRANGE R2 S0 R1 S1 R0 FBPECL 50 MHz NC VDD VDD 0.01 F RN Q0 Q0 VDD FBPECL ICS527-04 VDD OE PECLO RN RN PECLO RN 0.01 F GND GND 125 MHz PECLIN RES 125 MHz PECLIN F6 F0 F5 F1 F4 F2 F3 ICS554-01A 0.01 F R5 Q3 RN Q3 RN 0.01 F RN Q1 Q2 RN RN Q1 Q2 RN 560 GND IN GND IN The layout design above produces the waveforms shown below. 125 MHz, PECLIN 50 MHz, PECLO (Complementary outputs are not shown) 50 MHz = 125 MHz * (FDW + 2) (RDW + 2) FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and FBPECL pins. In this example, the resistor network needed for each PECLO output is represented by the RN boxes. IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 5 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER PCB Layout Recommendations 2) PECL termination networks should be located as close to the outputs as possible. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS527-04. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS527-04. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature 0 Power Supply Voltage (measured in respect to GND) IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB Typ. 6 +3.15 +3.3 Max. Units +70 °C +3.45 V ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Max. Units 3.3 3.45 V Operating Voltage VDD 3.15 Input High Voltage VIH 2 Input Low Voltage VIL V 0.8 V Peak to Peak Input Voltage Pins 7, 8, 10, 11 0.3 1 V Common Mode Range Pins 7, 8, 10, 11 VDD-1.4 VDD-0.6 V Output High Voltage VOH IOH = -12 mA 2.4 Output Low Voltage VOL IOL = 12 mA Operating Supply Current IDD 15 MHz in, 60 MHz out, no load Input Capacitance CIN On-chip pull-up resistor RPU V 0.4 configuration inputs V 8 mA 4 pF 270 kΩ AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Input Frequency Output Frequency, CLK1 Symbol Conditions FIN FOUT 0 to +70° C Output Duty Cycle tOD Absolute Clock Period Jitter tja One sigma Clock Period Jitter tjs Input to output skew tIO PECLIN to PECLO, Note 1 Device to device skew tpi Common CLKIN, measured at FBPECL Min. Max. Units 1.5 200 MHz 4 160 MHz 55 % 45 Deviation from mean Typ. 50 ± 90 ps 40 ps -250 250 ps 500 ps Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Conditions Min. Typ. Max. Units θJA Still air 100 ° C/W θJA 1 m/s air flow 80 ° C/W θJA 3 m/s air flow 67 ° C/W 60 ° C/W θJC IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 7 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body, 0.025 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 28 Symbol E1 A A1 A2 b C D E E1 e L α aaa E INDEX AREA 1 2 D A 2 Min Inches Max 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° -0.10 Min Max .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° -0.004 A A 1 c -Ce SEATING PLANE b L aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature 527R-04* ICS527R-04 Tubes 28-pin SSOP 0 to +70° C 527R-04T* ICS527R-04 Tape and Reel 28-pin SSOP 0 to +70° C 527R-04LF 527R-04LF Tubes 28-pin SSOP 0 to +70° C 527R-04LFT 527R-04LF Tape and Reel 28-pin SSOP 0 to +70° C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 “LF” denotes Pb free packaging, RoHS compliant While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB 8 ICS527-04 REV E 092209 ICS527-04 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB PECL ZDB AND MULTIPLIER/DIVIDER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA