DATASHEET
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
Description
Features
The ICS601-21 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise and low jitter. It is ICS’ lowest
phase noise multiplier. Using ICS’ patented analog and
digital Phase Locked Loop (PLL) techniques, the chip
accepts a 10 - 27 MHz crystal or clock input, and produces
output clocks up to 220 MHz at 3.3 V.
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This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
Fully integrated PLL, no external loop filter required
Differential 3.3 V LVPECL outputs
Uses fundamental 10 - 27 MHz crystal or clock
Output clocks up to 220 MHz at 3.3 V
Low phase noise: -122 dBc/Hz at 10 kHz
Low jitter - 15 ps one sigma typ.
Powerdown mode lowers power consumption
Packaged in 16-pin TSSOP
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Commercial temperature range available
Available in Pb (lead) free package
Block Diagram
VDD
Reference
Divider
Loop
Filter
Charge
Pump
Phase
Comparator
VCO
CLK
nCLK
X1/ICLK
Crystal or
clock input
VCO
Divide
Crystal
Oscillator
X2
ROM Based
Multipliers
4
GND
S2:0
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
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LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Multiplier Select Table
X1
1
16
X2
VD D
2
15
GND
VD D
3
14
C LK
VD D
4
13
nC LK
GND
5
12
VD D
VD D
6
11
S0
GND
7
10
S1
GND
8
9
S2
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Multiplier
x1
x2
x3
x4
x5
x6
x8
x16
16 Pin (173 m il) TSSOP
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
X1
XI
2-4
VDD
Power
Connect to +3.3 V.
5
GND
Power
Connect to ground.
6
VDD
Power
Connect to +3.3 V.
7-8
GND
Power
Connect to ground.
9
S2
Input
Select pin 2. Internal pull-up resistor.
10
S1
Input
Select pin 1. Internal pull-up resistor.
11
S0
Input
Select pin 0. Internal pull-up resistor.
12
VDD
Power
Connect to +3.3 V.
13
nCLK
Output
Inverted differential clock output.
14
CLK
Output
Differential clock output.
15
GND
Power
Connect to ground.
16
X2
XO
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
Pin Description
Crystal or clock input. Connect to a 10-27 MHz fundamental parallel mode
crystal or clock input.
Crystal connection. Connect to 10-27MHz fundamental parallel mode crystal
or leave unconnected for clock input.
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LOW PHASE NOISE CLOCK MULTIPLIER
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External Components
The ICS601-21 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as possible. A 50 Ω
terminating resistor should be used on each clock output. (See termination diagram on page 5). The crystal must
be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not
use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground
and X2 to ground. In general, the value of these capacitors is given by the following equation, where CL is the
crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF
caps can be used. For any given board layout, ICS can measure the board capacitance and recommend the exact
capacitance value to use.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-21. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial version
0 to +70 ° C
Storage Temperature
-65 to +150 ° C
Junction Temperature
125 ° C
Soldering Temperature
260 ° C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
+3.0
+3.6
V
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to +70° C
Parameter
Symbol
Conditions
Operating Voltage
VDD
Input High Voltage
VIH
X1/ICLK pin only
Input Low Voltage
VIL
X1/ICLK pin only
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
Min.
3.0
3
Typ.
Max.
Units
3.6
V
VDD/2+1
V
VDD/2-1
ICS601-21
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LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min.
Typ.
Units
VDD
V
0.8
V
Input High Voltage
VIH
Input select pins
Input Low Voltage
VIL
Input select pins
Output High Voltage
VOH
Note 1
VDD-1.4
VDD-1.0
V
Output Low Voltage
VOL
Note 1
VDD-2.0
VDD-1.7
V
0.6
0.95
V
45
mA
Output Voltage Swing
Vswing
2
Max.
Peak to Peak
Operating Supply Current
IDD
Note 1, 125 MHz
30
Input Capacitance
CIN
Input select pins
5
pF
On Chip Pull-up Resistor
RPU
Input select pins
510
kΩ
Note 1: Outputs terminated with 50Ω to VDD-2V
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C
Parameter
Symbol
Crystal Input Frequency
Fin
Conditions
Note 2
Output Frequency
Min.
Typ.
Max.
Units
10
27
MHz
10
220
MHz
Output Rise Time
tOR
20% to 80%, no load
600
900
ps
Output Fall Time
tOF
80% to 20%, no load
900
1200
ps
50
55
%
Output Clock Duty Cycle
at VDD/2
45
Maximum Absolute Jitter, short
term, 125 MHz
No load
±50
±75
ps
Maximum Jitter, one sigma,
125 MHz (x5)
No load
12
20
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
-90
-94
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
1 kHz
-116
-120
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
-118
-122
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
100 kHz offset
-115
-119
dBc/Hz
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x, maximum input
frequency is 13.75 MHz).
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
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CLOCK MULTIPLIER
Parameter Measurement Information
V D D = 3.3V
V D D = 3.3V
Z = 50 Ω
SCOPE
Z = 50 Ω
Qx
LV P E C L
Qx
50 Ω
LV P E C L
Z = 50 Ω
Z = 50 Ω
nQ x
50 Ω
nQ x
50 Ω
50 Ω
G N D =0V
G N D =0V
V D D-2V = 1.3V
3.3V O utput Load A C Test C ircuit
3.3V LV P E C L D river Term ination
VOH
nFOUT
VREF
VOL
FOUT
Reference Point
tcycle(n)
tcycle(n+1)
HISTOGRAM
Mean Period
(First edge after trigger)
tjit(cc) = tcycle(n) - tcycle(n+1)
1s contains 68.26% of all measurements
2s contains 95.4% of all measurements
3s contains 99.73% of all measurements
4s contains 99.99366% of all measurements
6s contains (100-1.973x10-7)% of all measurements
1000 Cycles
Period Jitter
CYCLE-TO-CYCLE JITTER
nFOUT
80%
80%
VSWING
FOUT
Clock
Outputs
Pulse Width
tPERIOD
ODC =
20%
20%
tOR
tPW
tOF
tPERIOD
OUTPUT DUTY CYCLE AND tPERIOD
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
OUTPUT RISE/FALL TIME
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CLOCK MULTIPLIER
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
*For reference only. Controlling dimensions in mm.
A
A2
Min
Inches*
A1
c
-Ce
b
SEATING
PLANE
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
601G-21
601G-21T
601G-21LF
601G-21LFT
ICS601G-21
ICS601G-21
601G-21LF
601G-21LF
Tubes
Tape and Reel
Tubes
Tape and Reel
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +70°
0 to +70°
0 to +70°
0 to +70°
C
C
C
C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for
either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are
implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to
change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LOW PHASE NOISE CLOCK MULTIPLIER
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CLOCK MULTIPLIER
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www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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