DATASHEET
ICS601-02
LOW PHASE NOISE CLOCK MULTIPLIER
Description
Features
The ICS601-02 is a low cost, low phase noise, high
performance clock synthesizer for any application that
requires low phase noise and low jitter. The ICS601 is IDT’s
lowest phase noise multiplier. Using IDT’s patented analog
and digital Phase Locked Loop (PLL) techniques, the chip
accepts a 10–27 MHz crystal or clock input, and produces
output clocks up to 170 MHz at 3.3 V. A separate supply pin
is provided so that the output can be 2.5 V.
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•
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This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed. For
applications which require defined input to output timing,
use the ICS670-01.
Packaged in 16-pin SOIC (Pb free)
Uses fundamental 10 - 27 MHz crystal or clock
Patented PLL with the lowest phase noise
Output clocks up to 170 MHz at 3.3 V
Output Enable function tri-states outptus
Low phase noise: -132 dBc/Hz at 10 kHz
Low jitter - 18 ps one sigma
Full swing CMOS outputs with 25 mA drive capability at
TTL levels
• Advanced, low power, sub-micron CMOS process
• Industrial temperature range (-40 to +85°C)
• 3.3 V or 5 V core VDD. Output clock can operate down to
2.5 V.
Block Diagram
VDDP
VDD
Reference
Divider
Phase
Comparator
Charge
Pump
X1/ICLK
CLK
VCO
VCO
Divide
Crystal
Oscillator
Crystal or
clock input
Loop
Filter
X2
Optional crystal
capacitors needed
for accurate tuning
(not shown)
ROM Based
Multipliers
4
GND
S3:0
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
1
OE
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LOW PHASE NOISE CLOCK MULTIPLIER
SYNTHESIZERS
Pin Assignment
Multiplier Select Table
S3
S2
S1
S0
CLK
CLK
1
16
GND
0
0
0
0
Input x4/3
VDDP
2
15
GND
0
0
0
1
Input x4
VDD
3
14
GND
0
0
1
0
Input x25/4
0
1
1
Input x3
VDD
4
13
GND
0
VDD
5
12
OE
0
1
0
0
Input x7.5
0
1
0
1
Input x5
0
1
1
0
Input x6
0
1
1
1
Input x8
1
0
0
0
Input x8/3
1
0
0
1
Input x8
1
0
1
0
Input x12.5
1
0
1
1
Input x6
1
1
0
0
Input x15
1
1
0
1
Input x10
1
1
1
0
Input x12
1
1
1
1
Input x16
X2
6
11
S0
S1
7
10
S3
X1/ICLK
8
9
S2
16-pin SOIC
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
CLK
Output
Clock output from VCO. Output frequency equals the input frequency times multiplier.
2
VDDP
Power
Supply pin for CLK output buffer. Sets output clock amplitude. Connect to 2.5V or 3.3V.
3
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
4
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
5
VDD
Power
Connect to +3.3V or +5V. Must match other VDDs.
6
X2
XO
7
S1
Input
8
X1/ICLK
XI
9
S2
Input
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
10
S3
Input
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
11
S0
Input
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
12
OE
Input
Output Enable. Tri-states the output clock when low. Internal pull-up.
13
GND
Power
Connect to ground.
14
GND
Power
Connect to ground.
15
GND
Power
Connect to ground.
16
GND
Power
Connect to ground.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
Pin Description
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock.
2
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LOW PHASE NOISE CLOCK MULTIPLIER
SYNTHESIZERS
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that can be
taken to achieve these levels of phase noise from the ICS601-02. Variations in VDD will increase the phase noise,
so it is important to have a stable, low noise supply voltage at the device. Use decoupling capacitors of 0.1 µF in
parallel with 0.01 µF. It is important to have these capacitors as close as possible to the ICS601-02 supply pins.
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this can
reduce the phase noise by as much as 10 dBc/Hz.
Figure 1: Phase Noise of ICS601-02 at 125 MHz out, 25 MHz crystal input, VDD=3.3 V.
External Components
The ICS601-02 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as possible. A series
termination resistor of 33 Ω may be used for the clock output. The crystal must be connected as close to the chip as
possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning
when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the
value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps
(pF) = (CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
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SYNTHESIZERS
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-02. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD (referenced to ground)
7V
All Inputs and Outputs (referenced to ground)
-0.5 V to VDD+0.5 V
Storage Temperature
-65 to +150° C
Soldering Temperature
260° C
Ambient Operating Temperature (industrial)
-40 to +85°C
DC Electrical Characteristics
Unless stated otherwise, VDD = VDDP = 3.3 V, Ambient Temperature -40 to +85° C
Parameter
Symbol
Operating Voltage
Output Buffer Voltage
Conditions
Min.
Typ.
Max.
Units
VDD
3.0
5.5
V
VDDP
2.375
VDD
V
Input High Voltage
VIH
XI/ICLK pin only, Note 1
Input Low Voltage
VIL
XI/ICLK pin only, Note 1
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage,
CMOS level
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
Opertating Supply Current
IDD
No load, 125 MHz
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
OE, select pins
(VDD/2)+1
V
(VDD/2)-1
2
V
0.8
9
±40
V
V
0.4
V
20
mA
±60
mA
5
pF
Note 1: Switching occurs nominally at VDD/2.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
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SYNTHESIZERS
AC Electrical Characteristics
Unless stated otherwise, VDD = VDDP = 3.3 V, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Symbol
Conditions
Typ.
MHz
At 3.3 V or 5 V
170
MHz
Output Clock Rise Time
0.8 to 2.0 V, no load
1.5
ns
Output Clock Fall Time
0.8 to 2.0 V, no load
1.5
ns
Output Clock Duty Cycle
At VDD/2
50
55
%
Maximum Absolute Jitter, short
term, 125 MHz
No load
±50
±75
ps
Maximum Jitter, one sigma, 125
MHz (x5)
No load
18
25
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
-108
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
1 kHz offset
-123
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
-132
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
100 kHz offset
-125
dBc/Hz
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
fOUT
10
Max. Units
27
Output Frequency
fIN
Min.
5
45
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LOW PHASE NOISE CLOCK MULTIPLIER
SYNTHESIZERS
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
SOIC
Symbol
E
A
A1
B
C
D
E
e
H
L
α
H
I N D E X
A R E A
1
2
D
Min
Max
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.40
1.27
0°
8°
A
A1
C
-C e
S E A TIN G
P LA N E
B
L
.1 0 (.0 0 4 )
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
ICS601M-02I
ICS601M-02IT
ICS601M-02ILF
ICS601M-02ILFT
ICS601M-02I
ICS601M-02I
601M-02ILF
601M-02ILF
Tubes
Tape and Reel
Tubes
Tape and Reel
16-pin SOIC
16-pin SOIC
16-pin SOIC
16-pin SOIC
Temperature
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
C
C
C
C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
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SYNTHESIZERS
Revision History
Rev.
E
Originator
Date
02/10/09
Description of Change
Converted to IDT document template.
IDT™ LOW PHASE NOISE CLOCK MULTIPLIER
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LOW PHASE NOISE CLOCK MULTIPLIER
SYNTHESIZERS
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For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
www.idt.com/go/clockhelp
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Integrated Device Technology, Inc.
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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