ICS650R-21

DATASHEET ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE Description Features The ICS650-21 is a low cost, low-jitter, high-performance clock synthesizer for system peripheral applications. Using analog/digital Phase Locked Loop (PLL) techniques, the device accepts a parallel resonant 25 MHz crystal input to produce up to eight output clocks. The device provides clocks for PCI, SCSI, Fast Ethernet, Ethernet, USB, and AC97. The user can select one of three USB frequencies and also one of two AC97 audio frequencies. The OE pin puts all outputs into a high-impedance state for board level testing. All frequencies are generated with less than one ppm error, meeting the demands of SCSI and Ethernet clocking. • • • • • • • • • • • • • • • • Packaged in 20-pin SSOP (QSOP) Available in Pb (lead) free package Lower jitter version of ICS650-01 Operating voltage of 3.3 V or 5 V Zero ppm synthesis error in all clocks Inexpensive 25 MHz crystal or clock input Provides Ethernet and Fast Ethernet clocks Provides SCSI clocks Provides PCI clocks Selectable AC97 audio clock Selectable USB clock OE pin tri-states the outputs for testing Selectable frequencies on three clocks Duty cycle of 45/55 for Processor clock and Audio clock Advanced, low-power CMOS process Industrial temperature range available NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram VDD 3 PSEL1:0 2 3 ASEL Audio Clock Clock Synthesis Circuitry USEL USB Clock 20 MHz X1/ICLK 25 MHz Crystal or Clock Processor Clocks Crystal Oscillator 25 MHz X2 2 Optional crystal capacitors IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE GND 1 OE (all outputs) ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Pin Assignment Processor Clock (MHz) USEL 1 20 PSEL1 X2 2 19 PSEL0 X1/ICLK 3 18 PCLK2 VDD 4 17 PCLK3 PSEL1 PSEL0 PCLK1 PCLK2, 3 0 0 25 50 0 M TEST MODE 1 TEST MODE VDD 5 16 VDD 0 GND 6 15 ASEL M 0 40 80 UCLK 7 14 GND M M 33.3333 66.6667 20M 8 13 OFF/14.318M M 1 20 40 ACLK 9 12 PCLK1 1 0 20 33.3333 10 11 OE 1 M 20 66.6667 1 1 50 100 25M 20-pin (150 mil) SSOP Audio Clock (MHz) USB Clock (MHz) ASEL ACLK USEL UCLK 0 12 0 49.152 M 24 M 24.576 1 48 1 14.318 0 = connect directly to ground 1 = connect directly to VDD M = leave unconnected (floating) Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 USEL Input 2 X2 XO Crystal connection. Connect to parallel mode 25 MHz crystal. Leave open for clock. 3 X1/ICLK XI Crystal connection. Connect to parallel mode 25 MHz crystal or clock. 4 VDD Power Connect to VDD. Must be same value as other VDD. Decouple with pin 6. 5 VDD Power Connect to VDD. Must be same value as other VDD. 6 GND Power Connect to ground. 7 UCLK Output USB clock output per table above. 8 20M Output Fixed 20 MHz output for Ethernet. 9 ACLK Output AC97 audio clock output per table above. 10 25M Output Fixed 25 MHz reference output for Fast Ethernet. 11 OE Input 12 PCLK1 Output UCLK select pin. Determines frequency of USB clock per table above. Output enable. Tri-states all outputs when low. PCLK output number 1 per table above. IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE 2 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Pin Number Pin Name Pin Type Pin Description 13 OFF/14.318M Output 14.31818 MHz clock output only when ASEL = VDD. 14 GND Power Connect to ground. 15 ASEL Input ACLK select pin. Determines frequency of audio clock per table above. 16 VDD Power Connect to VDD. Must be same value as other VDD. Decouple with pin 14. 17 PCLK3 Output PCLK output number 3 per table above. 18 PCLK2 Output PCLK output number 2 per table above. 19 PSEL0 Input Processor select pin #0. Determines frequencies on PCLKs 1-3 per table above. 20 PSEL1 Input Processor select pin #1. Determines frequencies on PCLKs 1-3 per table above. External Components impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. The ICS650-21 requires a minimum number of external components for proper operation. Decoupling Capacitor Crystal Information Decoupling capacitors of 0.01µF must be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 6) x 2 Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE In the equation, CL is the crystal load capacitance. So, for a crystal with a 16pF load capacitance, two 20 pF [(16-6) x 2] capacitors should be used. 3 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-21. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +5.5 V 0 Power Supply Voltage (measured in respect to GND) +3.0 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Typ. Units 5.5 V Operating Voltage VDD Supply Current IDD No load, Note 1 Input High Voltage VIH Select inputs, OE Input Low Voltage VIL Select inputs, OE Output High Voltage VOH IOH = -8 mA VDD-0.4 V Output High Voltage VOH IOH = -8 mA 2.4 V Output Low Voltage VOL IOL = 8 mA Short Circuit Current IOS CLK output ±50 mA Except X1 5 pF Input Capacitance, inputs 3.0 Max. 30 mA 2 V 0.8 0.4 V V Note 1: With all clocks at highest frequencies. IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE 4 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. Units 25 Output Clocks Accuracy (synthesis error) All clocks MHz 1 ppm Output Rise Time tOR 0.8 to 2.0 V, Note 2 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, Note 2 1.5 ns Output Clock Duty Cycle One Sigma Jitter UCLK, at VDD/2 40 50 60 % PCLCK, ACLCK, at VDD/2 45 50 55 % Except ACLK 75 ps ACLK 120 ps Absolute Clock Period Jitter UCLK, 20M Power-up Time PLL lock time from power-up to 1% of final value -500 1 500 ps 4 ms Note 1: Values dependent on programming. Note 2: Measured with 15 pF load. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE Symbol Conditions Min. Typ. Max. Units θ JA Still air 135 ° C/W θ JA 1 m/s air flow 93 ° C/W θ JA 3 m/s air flow 78 ° C/W 60 ° C/W θ JC 5 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 20 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α E INDEX AREA 1 2 D A 2 A Min Inches* Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° Max .053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° *For reference only. Controlling dimensions in mm. A 1 c -Ce b SEATING PLANE L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package 650R-21* 650R-21T* 650R-21LF 650R-21LFT 650R-21I* 650R-21IT* 650R-21ILF 650R-21ILFT ICS650R-21 ICS650R-21 ICS650R-21L ICS650R-21L ICS650R-21I ICS650R-21I 650R-21ILF 650R-21ILF Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Temperature 0 to +70° 0 to +70° 0 to +70° 0 to +70° -40 to 85° -40 to 85° -40 to 85° -40 to 85° C C C C C C C C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE 6 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Revision History Rev. Originator Date G P. Griffith 02/15/06 Added “Power-up Time” spec in AC chars. 11/04/09 Added EOL note for non-green parts. H Description of Change IDT™ / ICS™ SYSTEM PERIPHERAL CLOCK SOURCE 7 ICS650-21 REV H 110409 ICS650-21 SYSTEM PERIPHERAL CLOCK SOURCE CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA