ICS680G-01

DATASHEET NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER Description Features The ICS680-01 generates four high-frequency clock outputs and a reference from a 25 MHz crystal or clock input. The device includes a low-skew, single input to four output zero delay clock buffer. It can replace multiple crystals and oscillators, saving board space and cost. • • • • • • • • • • The device has a power-down tri-state (PDTS) pin that place the clock outputs in a high-impedance state when pulled low. The PDTS pin includes an internal pull-up resistor. ICS680-01 Packaged in 24-pin TSSOP Available in Pb (lead) free package Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Five output driver driven by external clock Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low-power CMOS process Fixed output frequencies of 25 MHz and 48 MHz Selectable output frequencies of 24 MHz, 48 MHz, 50 MHz and 66.6666 MHz • Qx outputs replace costly discrete buffer • Low-skew buffer outputs (250 ps) NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram VDD 5 S0 CLK1 S1 CLK2 PLLA Divide Logic and Output Enable Control PLLB 25 MHz Crystal or Clock PLLC 48M 25M X1/ICLK X2 Crystal Oscillator QFB External capacitors may be required. Q0 Q1 ICLK PLL/Buffer Q2 Q3 2 GND IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 1 PDTS ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER Pin Assignment ZDB AND SYNTHESIZER Output Clock Select Table S0 S1 VDD M M OFF 48 0 0 50 48 0 1 66.6666 48 X1/ICLK 1 24 X2 GND 2 23 CLK1 (MHz) CLK2 (MHz) S0 3 22 PDTS VDD 4 21 S1 CLK1 5 20 25M GND 6 19 ICLK 1 0 50 24 GND 7 18 VDD 1 1 66.6666 24 Q1 8 17 QFB Q2 9 16 VDD VDD 10 15 48M Q3 11 14 CLK2 Q4 12 13 GND 24-pin TSSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK XI 2 GND Power Connect to ground. 3 S0 Input Select pin 0. See table above. 4 VDD Power Connect to voltage supply. 5 CLK1 Output Selectable output clock. See table above. Weak internal pull-down when tri-state. 6 GND Power Connect to ground. 7 GND Power Connect to ground. 8 Q1 Output Clock output 1. Weak internal pull-down when tri-state. 9 Q2 Output Clock output 2. Weak internal pull-down when tri-state. 10 VDD Power Connect to voltage supply. 11 Q3 Output Clock output 3. Weak internal pull-down when tri-state. 12 Q4 Output Clock output 4. Weak internal pull-down when tri-state. 13 GND Power Connect to ground. 14 CLK2 Output Selectable output clock. See table above. Weak internal pull-down when tri-state. 15 48M Output 48 MHz output clock. Weak internal pull-down when tri-state. 16 VDD Power Connect to voltage supply. 17 QFB Output Feedback pin. Internally connected. Crystal input. Connect this pin to a crystal or external clock source. IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 2 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER Pin Number Pin Name Pin Type Pin Description 18 VDD Power Connect to voltage supply. 19 ICLK Input Zero Delay Buffer Input. Weak Internal pull-up. 20 25M Output 21 S1 Input Select pin 1. See table above. 22 PDTS Power Power-down tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 23 VDD Power Connect to voltage supply. 24 X2 XO 25 MHz reference output clock. Weak internal pull-down when tri-state. Crystal output. Connect this pin to a crystal. Float for clock input. External Components The ICS680-01 requires a minimum number of external components for proper operation. Decoupling Capacitor PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. A decoupling capacitor of 0.01µF must be connected between VDD (pins 5 and 16) and GND (pins 6 and 15), as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. 1) The 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Series Termination Resistor 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation crystal caps (pF) = (CL-6)x2 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS680-01. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. In the equation, CL is the crystal load capacitance. So for a crystal with a 16 pF load capacitance, two 20 pF[(16-6)x2] capacitors should be used IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 3 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS680-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70° C Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. 0 +3.13 IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 4 +3.3 Max. Units +70 °C +3.46 V ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Operating Voltage VDD Supply Current IDD Conditions Min. Typ. Max. Units 3.13 3.3 3.46 V No load,PDTS=1 32 mA No load,PDTS=0 300 µA Input High Voltage, binary inputs VIH PDTS, ICLK Input High Voltage, trinary inputs VIH S0, S1 Input Low Voltage, binary inputs VIL PDTS, ICLK 0.8 V Input Low Voltage, trinary inputs VIL S0, S1 0.5 V Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA 0.8 V IOL = 4 mA 0.4 V Short Circuit Current IOS Input Capacitance, Inputs CLK output 2 V VDD-0.5 V ±50 mA CIN 5 pF Nominal Output Impedance ZOUT 20 Ω On-Chip Pull-up Resistor, Inputs RPU PDTS, SEL 250 kΩ On-Chip Pull-down Resistor, Outputs RPD CLK outputs 250 kΩ IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 5 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Input Frequency fIN Conditions Min. Typ. Max. Units X1 25 MHz ICLK 33 MHz Output Frequency fOUT Q0 to Q3, QFB, Note 1 33 MHz Output Rise Time tOR 20% to 80%, Note 1 1.5 ns Output Fall Time tOF 80% to 20%, Note 1 1.5 ns Output Clock Duty Cycle tD at VDD/2, Note 2 Power-up Time One Sigma Clock Period Jitter 40 60 % PLL lock-time from power-up to 1% of final frequency 10 ms PDTS goes high until stable CLK outputs at 1% of final frequency 2 ms Configuration dependent 50 ps ±200 ps Maximum Absolute Jitter tja Deviation from mean. Configuration dependent. QFB to ICLK Skew tPD Measured at VDD/2, Note 3 -350 350 QFB, Q0 to Q3, Note 3 -250 250 Pin-to-pin Skew ps Note 1: Measured with a 15 pF load. Note 2: Duty cycle is configuration dependent. Most configurations are min 45% / max 55%. Note 3: Skew is measured at 1.4 V on rising edges with a 33 MHz ICLK. IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 6 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER Package Outline and Package Dimensions (24-pin TSSOP, 173 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 24 Symbol E1 INDEX AREA A1 A2 b C D E E1 e L α E 1 2 D Min Inches Max Min — 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 7.70 7.90 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° Max — .047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.303 0.311 0.252 BASIC 0.169 0.177 0.0256 Basic .018 .030 0° 8° A A2 A1 c - Ce b SEATING PLANE .10 (.004) L C Ordering Information Part / Order Number Marking Shipping Packaging Package 680G-01* 680G-01T* 680G-01LF 680G-01LFT 680G-01 680G-01 680G-01LF 680G-01LF Tubes Tape and Reel Tubes Tape and Reel 24-pin TSSOP 24-pin TSSOP 24-pin TSSOP 24-pin TSSOP Temperature 0 to +70° 0 to +70° 0 to +70° 0 to +70° C C C C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 7 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER Revision History Rev. Originator Date D P.Griffith 10/01/04 Removed power supply ramp-up time spec; added trinary input specs to DC chars; added a second Output Low Voltage spec; updated Supply Current specs from 50 to 32 mA, and 50 to 300 uA; changed pull-down resistor value from 525 to 250 kohms; changed Output Rise/Fall times from 1 to 1.5 ns E P.Griffith 12/21/04 Released as standard product from custom device. F J. Sarma 02/03/05 Add LF ordering info. 11/04/09 Added EOL note for non-green parts. G Description of Change IDT™ / ICS™ NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER 8 ICS680-01 REV G 110409 ICS680-01 NETWORKING CLOCK SYNTHESIZER AND ZERO DELAY BUFFER ZDB AND SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA