FEMTOCLOCK® NG
Crystal-to-LVDS/HCSL Clock Synthesizer
ICS841N254I
DATA SHEET
General Description
Features
The ICS841N254I is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates four
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with excellent phase jitter performance. The four outputs
are organized in two banks of two LVDS and two HCSL ouputs.The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The synthesized clock frequency and
the phase-noise performance are optimized for driving RIO 1.3 and
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V
voltage supplies and is packaged in a small 32-lead VFQFN
package. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
•
•
Fourth generation FemtoClock® (NG) technology
•
•
Four differential clock outputs (two LVDS and two HCSL outputs)
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
•
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
•
•
•
•
Power supply noise rejection PSNR: -50dB (typical)
•
-40°C to 85°C ambient operating temperature
Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
Crystal interface designed for 25MHz,
parallel resonant crystal
LVCMOS interface levels for the frequency select input
Full 3.3V or 2.5V supply voltage
Available in both standard (RoHS 5) and Lead-free (RoHS 6)
packages
0
1
125MHz
1
0
100MHz
1
1
250MHz
GND
nQB1
156.25MHz
QB1
0 (default)
VDDOB
0 (default)
nQB0
F_SEL0
Pin Assignment
GND
F_SEL1
Output Frequency with
fXTAL = 25MHz
VDD
Inputs
QB0
Function Table
32 31 30 29 28 27 26 25
VDD
1
nc
2
VDDA 3
nc 4
NOTE: F_SEL[1:0] are asynchronous controls.
GND
5
REF_CLK
6
24 IREF
23 GND
ICS841N254I
32-lead VFQFN
K Package
5mm x 5mm x 0.925mm
package body
Top View
nOEA 7
XTAL_IN
1
OSC
0
XTAL_OUT
REF_CLK
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
nOEB
IREF
Pulldown
PFD
&
LPF
1
Pulldown
÷N
FemtoClock® NG
VCO
625MHz
0
÷25
21 QA0
20 VDDOA
19 nQA1
18 QA1
VDD 8
QA0
nQA0
LVDS
QA1
nQA1
LVDS
QB0
nQB0
HCSL
QB1
nQB1
HCSL
F_SEL1
F_SEL0
BYPASS
VDD
XTAL_OUT
XTAL_IN
10 11 12 13 14 15 16
REF_SEL
17 GND
9
nOEB
Block Diagram
22 nQA0
Pulldown
Pulldown
2
Pulldown
Pulldown
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 8, 13, 32
VDD
Power
2, 4
nc
Unused
3
VDDA
Power
Analog power supply.
5, 17,
23, 25, 31
GND
Power
Power supply ground.
6
REF_CLK
Input
Pulldown
Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.
7
nOEA
Input
Pulldown
Output enable input. See Table 3D for function. LVCMOS/LVTTL interface levels.
9
nOEB
Input
Pulldown
Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels.
10
REF_SEL
Input
Pulldown
Reference select input. See Table 3B for function.
LVCMOS/LVTTL interface levels.
11,
12
XTAL_IN,
XTAL_OUT
Input
14
BYPASS
Input
Pulldown
Bypass mode select pin. See Table 3C for function.
LVCMOS/LVTTL interface levels.
15,
16
F_SEL0,
F_SEL1
Input
Pulldown
Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
18, 19
QA1, nQA1
Output
Differential clock output. LVDS interface levels.
20
VDDOA
Power
Output supply pin for QAx outputs.
21, 22
QA0, nQA0
Output
Differential clock output. LVDS interface levels.
24
IREF
Input
26, 27
nQB1, QB1
Output
Differential clock output. HCSL interface levels.
28
VDDOB
Power
Output supply pin for QBx outputs.
29, 30
nQB0, QB0
Output
Differential clock output. HCSL interface levels.
Core supply pins.
No connect.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
External fixed precision resistor (475Ω) from this pin to ground provides a reference
current used for differential current-mode QBx, nQBx clock outputs.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ICS841N254AKI REVISION A APRIL 18, 2011
Test Conditions
2
Minimum
Typical
Maximum
Units
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Function Tables
Table 3A. Output Divider and Output Frequency
Inputs
F_SEL1
F_SEL0
Operation
fOUT with fREF = 25MHz
0 (default)
0 (default)
fOUT = fREF * 25 ÷ 4
156.25MHz
0
1
fOUT = fREF * 5
125MHz
1
0
fOUT = fREF * 4
100MHz
1
1
fOUT = fREF * 10
250MHz
NOTE: F_SEL[1:0] are asynchronous controls.
Table 3B. PLL Reference Clock Select Function Table
Input
REF_SEL
Operation
0 (default)
The crystal interface is selected as reference clock
1
The REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
Table 3C. PLL BYPASS Function Table
Input
BYPASS
Operation
0 (default)
PLL is enabled. The reference frequency fREF is multiplied by the PLL
feedback divider of 25 and then divided by the selected output divider N.
1
PLL is bypassed. The reference frequency fREF is divided by the selected
output divider N. AC specifications do not apply in PLL bypass mode.
NOTE: BYPASS is an asynchronous control.
Table 3D. nOEA Output Enable Function Table
Input
nOEA
Operation
0 (default)
QA0, nQA0 and QA1, nQA1 outputs are enabled
1
QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
NOTE: nOEA is an asynchronous control.
Table 3E. nOEB Output Enable Function Table
Input
nOEB
Operation
0 (default)
QB0, nQB0 and QB1, nQB1 outputs are enabled
1
QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
NOTE: nOEB is an asynchronous control.
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VDD + 0.5V
Outputs, VO (HCSL)
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
37.7°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
VDD – 0.30
3.3
VDD
V
VDD – 0.30
2.5
VDD
V
VDDOA&B
Output Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
V
IDDA
Analog Supply Current
30
mA
IDD
Power Supply Current
113
mA
IDDOA&B
Output Supply Current
72
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
VDD = VIN = 2.625V or
3.465V
IIL
Input Low Current
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
VDD = 2.625V or 3.465V,
VIN = 0V
ICS841N254AKI REVISION A APRIL 18, 2011
Test Conditions
Minimum
VDD = 3.3V
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
4
-5
Typical
µA
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 4C. LVDS 3.3V DC Characteristics, VDD = VDDOA = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
200
1.1
Maximum
Units
550
mV
50
mV
1.3
V
50
mV
Maximum
Units
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Minimum
Typical
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
80
Ω
Shunt Capacitance
7
pF
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 6. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
fREF
Reference Frequency
tjit(Ø)
ΦN
Test Conditions
RMS Phase Jitter (Random);
NOTE 1
Single-Side Band Noise Power
Minimum
Units
MHz
F_SEL [1:0] = 01
125
MHz
F_SEL [1:0] = 10
100
MHz
F_SEL [1:0] = 11
250
MHz
REF_CLK
25
MHz
156.25MHz, Integration Range:
1MHz – 20MHz
0.27
ps
156.25MHz, Integration Range:
12kHz – 20MHz
0.32
ps
125MHz, Integration Range:
1MHz – 20MHz
0.33
ps
125MHz,Integration Range:
12kHz – 20MHz
0.37
ps
156.25MHz, Offset: 100Hz
-91.6
dBc/Hz
156.25MHz, Offset: 1kHz
-120.8
dBc/Hz
156.25MHz, Offset: 10kHz
-132.2
dBc/Hz
156.25MHz, Offset: 100kHz
-135.0
dBc/Hz
From DC to 50MHz
-50
dB
Between QAx/nQAx & QBx/nQBx
1.8
Power Supply Noise Rejection
tsk(o)
Output Skew
NOTE 2, 3, 4
tsk(b)
Bank Skew
NOTE 2, 4, 5
tR / tF
Output Rise/Fall
Time
tLOCK
PLL Lock Time
VRB
Ring-back Voltage
Margin; NOTE 6, 7
QBx, nQBx
-100
tSTABLE
Time before VRB is
Allowed; NOTE 6, 7
QBx, nQBx
500
VMAX
Absolute Maximum
Output Voltage;
NOTE 8, 9
QBx, nQBx
VMIN
Absolute Minimum
Output Voltage;
NOTE 8, 10
QBx, nQBx
-300
VCROSS
Absolute Crossing
Voltage;
NOTE 8, 11, 12
QBx, nQBx
100
∆VCROSS
Total Variation of
VCROSS over all
edges;
NOTE 8, 11, 13
QBx, nQBx
Rise/Fall Edge Rate;
NOTE 6, 14
QBx, nQBx
Output Duty Cycle;
NOTE 15
Output Duty Cycle
odc
Maximum
156.25
PSNR
QAx, nQAx
Typical
F_SEL [1:0] = 00
20% to 80%
100
2.7
ns
55
ps
400
ps
20
ms
100
mV
ps
1150
mV
mV
350
mV
140
mV
0.6
5.5
V/ns
QBx, nQBx
47
53
%
QAx, nQAx
47
53
%
Measured between
-150mV to 150mV
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTES continued on next page.
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Please refer to the phase noise plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100mV differential range.
NOTE 7: Measurement taken from single ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through
the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
➝
Typical Phase Noise at 156.25MHz (3.3V)
Filter
➝
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.32ps (typical)
➝
Raw Phase Noise Data
Phase Noise Result by adding a
filter to raw data
Offset Frequency (Hz)
➝
Typical Phase Noise at 156.25MHz (3.3V)
Filter
Raw Phase Noise Data
➝
➝
Noise Power
dBc
Hz
156.25MHz
RMS Phase Jitter (Random)
1MHz to 20MHz = 0.27ps (typical)
Phase Noise Result by adding a
filter to raw data
Offset Frequency (Hz)
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Parameter Measurement Information
SCOPE
3.3V±5%
POWER SUPPLY
+ Float GND –
VDD,
VDDOA,
SCOPE
Qx
2.5V±5%
POWER SUPPLY
+ Float GND –
VDDA
VDD,
VDDOA,
Qx
VDDA
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
SCOPE
VDD,
VDDOB
50Ω
33Ω
VDDA
49.9Ω
IREF
Qx
VDDA
HCSL
50Ω
50Ω
IREF
nQx
GND
475Ω
GND
49.9Ω
475Ω
2pF
0V
0V
0V
0V
50Ω
2pF
HCSL
33Ω
VDD,
VDDOB
This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o)
measurements.
3.3V HCSL Output Load AC Test Circuit
3.3V HCSL Output Load AC Test Circuit
2.5V±5%
2.5V±5%
2.5V±5%
2.5V±5%
SCOPE
VDD,
VDD,
VDDOB
50Ω
33Ω
VDDA
IREF
VDDOB
VDDA
Qx
HCSL
49.9Ω
2pF
HCSL
50Ω
33Ω
50Ω
IREF
nQx
GND
475Ω
GND
475Ω
49.9Ω
2pF
0V
0V
50Ω
0V
This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o)
measurements.
2.5V HCSL Output Load AC Test Circuit
ICS841N254AKI REVISION A APRIL 18, 2011
0V
2.5V HCSL Output Load AC Test Circuit
9
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Parameter Measurement Information, continued
Phase Noise Plot
Noise Power
nQA[0:1]
QA[0:1]
t PW
Phase Noise Mask
f1
Offset Frequency
t
odc =
PERIOD
t PW
x 100%
t PERIOD
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
LVDS Output Duty Cycle/Pulse Width/Period
nQX0
nQx
QX1
Qx
nQX0
nQy
QX1
t sk(b)
Qy
t sk(o)
Where X = Bank A or Bank B
Output Skew
Bank Skew
TSTABLE
Clock Period (Differential)
VRB
Positive Duty
Cycle (Differential)
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Negative Duty
Cycle (Differential)
0.0V
Q - nQ
VRB
Q - nQ
TSTABLE
Differential Measurement Points for Duty Cycle/Period
Differential Measurement Points for Ringback
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Parameter Measurement Information, continued
Rise Edge Rate
Fall Edge Rate
Rise Edge Rate
Fall Edge Rate
+150mV
+150mV
0.0V
0.0V
-150mV
-150mV
Q - nQ
Q - nQ
Differential Measurement Points for Rise/Fall Edge Rate
HCSL Differential Measurement Points for Rise/Fall Time
VMAX
nQ
nQ
VCROSS_MAX
VCROSS_DELTA
VCROSS_MIN
Q
Q
VMIN
Single-ended Measurement Points for Absolute Cross
Point/Swing
Single-ended Measurement Points for Delta Cross Point
VDD
VDD
out
LVDS
➤
out
➤
out
DC Input
➤
LVDS
100
➤
VOD/∆ VOD
VOS/∆ VOS
out
➤
DC Input
➤
Differential Output Voltage Setup
Offset Voltage Setup
ICS841N254AKI REVISION A APRIL 18, 2011
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©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Applications Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
REF_CLK Input
LVDS Outputs
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the REF_CLK to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, we recommend that there
is no trace attached.
Crystal Inputs
Differential Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Interface to IDT S-RIO Switches
The ICS841N254I is designed for driving the differential reference
clock input (REF_CLK) of IDT’s S-RIO 1.3 and 2.0 switch devices.
Both the LVDS and the HCSL outputs of the ICS841N254I have the
low-jitter, differential voltage and impedance characteristics required
to provide a high-quality 156.25MHz clock signal for both S-RIO 1.3
and 2.0 switch devices. Please refer to Figure 1A and Figure 1B for
suggested interfaces. The interfaces differ by the driving output,
LVDS and HCSL, and the corresponding source termination method.
In both Figure 1A and 1B, the AC-coupling capacitors are mandatory
by the IDT S-RIO switch devices. The differential REF_CLK input is
internally re-biased and AC-terminated. Both interface circuits are
optimized for 50Ω transmission lines and generate the voltage swing
required to reliably drive the clock reference input of a IDT S-RIO
switch. Please refer to IDT’s S-RIO device datasheet for more details.
REF_CLK_P
QAn
LVDS nQAn
T= 50Ω
Figure 1A shows the recommended interface circuit for driving the
156.25MHz reference clock of an IDT S-RIO 2.0 switch by a LVDS
output (QA0, QA1) of the ICS841N254I. The LVDS-to-differential
interface as shown in Figure 1A does not require any external
termination resistors: the ICS841N254I driver contains an internal
source termination at QA0 and QA1. The differential REF_CLK input
contains an internal AC-termination (RL) and re-bias (VBIAS).
Figure 4B shows the interface circuit for driving the 156.25MHz
reference clock of an IDT S-RIO 2.0 switch by an HCSL output of the
ICS841N254I (QB0, QB1): The HCSL-to-differential interface
requires external termination resistors (22...33Ω and 50Ω) for source
termination, which should be placed close the driver (QB0, QB1).
LI
CI
QBn
HCSL nQBn
RL
VBIAS
LI
+
REF_CLK
-
ICS841N254I
CI
ICS841N254I
RL
VBIAS
49.9
REF_CLK_N
IDT S-RIO 1.3, 2.0 Switch
LI
+
REF_CLK
RL
CI
IDT S-RIO 1.3, 2.0 Switch
Figure 1B. HCSL-to-S-RIO 2.0 Reference Clock Interface
Figure 1A. LVDS-to-S-RIO 2.0 Reference Clock Interface
ICS841N254AKI REVISION A APRIL 18, 2011
CI
22...33
RL
LI
T= 50Ω
22...33
49.9
REF_CLK_N
REF_CLK_P
12
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω. This can also be accomplished by removing
R1 and changing R2 to 50Ω. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS841N254AKI REVISION A APRIL 18, 2011
13
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
HCSL Recommended Termination
Figure 3A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
0.5" Max
Rs
types. All traces should be 50Ω impedance single-ended or 100Ω
differential.
1-14"
0-0.2"
22 to 33 +/-5%
L1
L2
L4
L1
L2
L4
0.5 - 3.5"
L5
L5
PCI Expres s
PCI Express
Connector
Driver
0-0.2"
L3
L3
PCI Express
Add-in Card
49.9 +/- 5%
Rt
Figure 3A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 3B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
0.5" Max
Rs
0 to 33
L1
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0Ω to 33Ω. All traces should be 50Ω
impedance single-ended or 100Ω differential.
0-18"
0-0.2"
L2
L3
L2
L3
0 to 33
L1
PCI Expres s
Driver
49.9 +/- 5%
Rt
Figure 3B. Recommended Termination (where a point-to-point connection can be used)
ICS841N254AKI REVISION A APRIL 18, 2011
14
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode
input range of the input receivers should be verified for compatibility
with the output.
+
LVDS Driver
LVDS
Receiver
100Ω
–
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
ICS841N254AKI REVISION A APRIL 18, 2011
15
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS841N254AKI REVISION A APRIL 18, 2011
16
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Schematic Layout
Figure 6 shows an example of ICS41N254I application schematic. In
this example, the device is operated at VDD= VDDOA = VDDOB = 3.3V.
A 12pF parallel resonant 25MHz crystal is used. The load
capacitance C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. Depending on the parasitics of the printed circuit board
layout, these values might require a slight adjustment to optimize the
frequency accuracy. Crystals with other load capacitance
specifications can be used. This will requiring adjusting C1 and C2.
For this device, the crystal load capacitors are required for proper
opteration.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS841N254I provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
RU1
1K
R4
Set Logic
Input to
'0'
VDD
33
QB0
Zo = 50
+
TL2
R5
VDD
RU2
Not Install
33
nQB0
Zo = 50
-
TL3
To Logic
Input
pins
To Logic
Input
pins
RD2
1K
QB1
nQ B1
RD1
Not Install
R6
50
VDDO
C6
0.1u
R7
50
Using for PCI Express
Add-In Card
R2
475
VDD
VDD=3.3V
R3
VDDA
10
VDDOA= VDDOB=3.3V
U1
VD D
GN D
QB0
nQB0
VDD OB
QB1
nQB1
GN D
C7
10u
HCSL Termination
32
31
30
29
28
27
26
25
VDD
C3
0.01u
C4
0.1u
Optional
VDD
R9
33
R10
33
QB1
1
2
3
4
5
6
7
8
Q1
Ro ~ 7 Ohm R8
Zo = 50 Ohm
REF_CLK
nOEA
43
QB1_33 Zo = 50
nQA0
QA0
VDDO
Driv er_LVCMOS
nQB1_33 Zo = 50
-
TL6
R11
50
LVDS Termination
BYPASS
F _S EL0
F _S EL1
nO EB
R EF _SE L
C1
5pF
X1
25MHz
XTAL_IN
XTAL_OUT
nQA1
3.3V
2
C9
0.1uF
-
BLM18BB221SN1
VDDO
1
Ferrite Bead C10
R1
100
C8
0.1u
BLM18BB221SN1
1
+
VDD
C2
5pF
3.3V
QA1
Zo = 100 Ohm Dif f erential
12pF
R12
50
Using for PCI Express
Point-to-Point
Connection
9
10
11
12
13
14
15
16
C5
0.1u
+
TL5
nQB1
nO EB
R E F _SEL
X T A L_IN
XT AL_O U T
VD D
BYPASS
F _S EL0
F _S EL1
VDD
IREF
GND
nQA0
QA0
VDDOA
nQA1
QA1
GND
VDD
nc
VDDA
nc
GND
REF_CLK
nOEA
VDD
24
23
22
21
20
19
18
17
C11
C17
10uF 0.1uF
0.1uF
2
Ferrite Bead C13
C12
0.1uF
VDD
C14
10uF 0.1uF
Figure 6. ICS841N254I Application Schematic
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
ICS841N254AKI REVISION A APRIL 18, 2011
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
17
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS841N254I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS841N254I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX + IDDOA&B_MAX ) = 3.465V *(113mA + 30mA + 72mA) = 744.98mW
•
Power (HCSL_output)MAX = 44.5mW * 2 = 89.0mW
Total Power_MAX = (3.465V, with all outputs switching) = 744.98mW + 89.0mW = 833.98mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.834W * 37.7°C/W = 116.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS841N254AKI REVISION A APRIL 18, 2011
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
18
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 7.
VDD
IOUT = 17mA
➤
VOUT
RREF =
475Ω ± 1%
RL
50Ω
IC
Figure 7. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD_MAX.
Power
= (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
ICS841N254AKI REVISION A APRIL 18, 2011
19
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32-lead VFQFN
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
Transistor Count
The transistor count for ICS841N254I is: 23,445
ICS841N254AKI REVISION A APRIL 18, 2011
20
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
To p View
Anvil
Anvil
Singulation
Singula tion
or
OR
Sawn
Singulation
L
N
e (Ty p.)
2 If N & N
1
are Even
2
E2
(N -1)x e
(Re f.)
E2
2
b
A
(Ref.)
D
e
N &N
Odd
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
0. 08
C
Bottom View w/Type A ID
D2
C
Bottom View w/Type C ID
2
1
2
1
CHAMFER
4
Th er mal
Ba se
D2
2
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
ND & NE
8
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS841N254AKI REVISION A APRIL 18, 2011
21
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 10. Ordering Information
Part/Order Number
841N254AKI
841N254AKIT
841N254AKILF
841N254AKILFT
Marking
ICS41N254AI
ICS1N254AI
ICS1N254AIL
ICS1N254AIL
Package
32 Lead VFQFN
32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
ICS841N254AKI REVISION A APRIL 18, 2011
22
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
6024 Silver Creek Valley Road
San Jose, California 95138
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Technical Support
netcom@idt.com
+480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2011. All rights reserved.
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