FemtoClock® NG Crystal-to-LVDS/
HCSL Clock Synthesizer
841N254B
Datasheet
Description
Features
The 841N254B is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates
four copies of a selectable 250MHz, 156.25MHz, 125MHz or
100MHz clock signal with excellent phase jitter performance. The
four outputs are organized in two banks of two LVDS and two
HCSL ouputs. The device uses IDT’s fourth generation
FemtoClock® NG technology for an optimum of high clock
frequency and low phase noise performance, combined with a low
power consumption and high power supply noise rejection. The
synthesized clock frequency and the phase-noise performance
are optimized for driving RIO 1.3 and 2.0 SerDes reference
clocks.
▪ Fourth generation FemtoClock® (NG) technology
▪ Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
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The device supports 3.3V and 2.5V voltage supplies and is
packaged in a small 32-lead VFQFN package. The extended
temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Function Table
Inputs
F_SEL1
F_SEL0
Output Frequency with
fXTAL = 25MHz
0 (default)
0 (default)
156.25MHz
0
1
125MHz
1
0
100MHz
1
1
250MHz
clock synthesized from a 25MHz fundamental mode crystal
Four differential clock outputs (two LVDS and two HCSL
outputs)
Crystal interface designed for 25MHz,
parallel resonant crystal
RMS phase jitter at 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
RMS phase jitter at 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
Power supply noise rejection PSNR: -50dB (typical)
LVCMOS interface levels for the frequency select input
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
NOTE: F_SEL[1:0] are asynchronous controls.
Block Diagram
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841N254B Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Description and Pin Characteristic Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Phase Noise at 156.25MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Phase Noise at 156.25MHz (3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommendations for Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Interface to IDT S-RIO Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overdriving the XTAL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
HCSL Recommended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VFQFN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Schematic Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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841N254B Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Type[a]
Number
Name
Description
1, 8, 13, 32
VDD
Power
Core supply pins.
2, 4
nc
Unused
No connect.
3
VDDA
Power
Analog power supply.
5, 17,
23, 25, 31
GND
Power
Power supply ground.
6
REF_CLK
Input
Pulldown
Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.
7
nOEA
Input
Pulldown
Output enable input. See Table 6 for function. LVCMOS/LVTTL interface levels.
9
nOEB
Input
Pulldown
Output enable input. See Table 7 for function. LVCMOS/LVTTL interface levels.
10
REF_SEL
Input
Pulldown
Reference select input. See Table 4 for function.
LVCMOS/LVTTL interface levels.
11,
12
XTAL_IN,
XTAL_OUT
Input
14
BYPASS
Input
Pulldown
Bypass mode select pin. See Table 5 for function.
LVCMOS/LVTTL interface levels.
15,
16
F_SEL0,
F_SEL1
Input
Pulldown
Frequency select pin. See Table 3 for function. LVCMOS/LVTTL interface levels.
18, 19
QA1, nQA1
Output
Differential clock output. LVDS interface levels.
20
VDDOA
Power
Output supply pin for QAx outputs.
21, 22
QA0, nQA0
Output
Differential clock output. LVDS interface levels.
24
IREF
Input
26, 27
nQB1, QB1
Output
Differential clock output. HCSL interface levels.
28
VDDOB
Power
Output supply pin for QBx outputs.
29, 30
nQB0, QB0
Output
Differential clock output. HCSL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
External fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode QBx, nQBx clock outputs.
[a] Pulldown refers to internal input resistors. See Table 2 for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLDOWN
Input Pulldown Resistor
©2018 Integrated Device Technology, Inc.
Test Conditions
3
Minimum
Typical
Maximum
Units
4
pF
100
k
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841N254B Datasheet
Function Tables
Table 3. Output Divider and Output Frequency
Inputs[a]
F_SEL1
F_SEL0
Operation
fOUT with fREF = 25MHz
0 (default)
0 (default)
fOUT = fREF * 25 ÷ 4
156.25MHz
0
1
fOUT = fREF * 5
125MHz
1
0
fOUT = fREF * 4
100MHz
1
1
fOUT = fREF * 10
250MHz
[a] F_SEL[1:0] are asynchronous controls.
Table 4. PLL Reference Clock Select Function Table
Input
REF_SEL[a]
Operation
0 (default)
The crystal interface is selected as reference clock
1
The REF_CLK input is selected as reference clock
[a] REF_SEL is an asynchronous control.
Table 5. PLL BYPASS Function Table
Input
BYPASS[a]
Operation
0 (default)
PLL is enabled. The reference frequency fREF is multiplied by the PLL
feedback divider of 25 and then divided by the selected output divider N.
1
PLL is bypassed. The reference frequency fREF is divided by the selected
output divider N. AC specifications do not apply in PLL bypass mode.
[a] BYPASS is an asynchronous control.
Table 6. nOEA Output Enable Function Table
Input
nOEA[a]
0 (default)
1
Operation
QA0, nQA0 and QA1, nQA1 outputs are enabled
QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
[a] nOEA is an asynchronous control.
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841N254B Datasheet
Table 7. nOEB Output Enable Function Table
Input
nOEB[a]
0 (default)
1
Operation
QB0, nQB0 and QB1, nQB1 outputs are enabled
QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
[a] nOEB is an asynchronous control.
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics
or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 8. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDD
3.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VDD + 0.5V
Outputs, VO (HCSL)
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
37.7°C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
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841N254B Datasheet
DC Electrical Characteristics
Table 9. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
VDDOA&
Test Conditions
Analog Supply Voltage
Output Supply Voltage
B
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
2.375
2.5
2.625
V
VDD – 0.30
3.3
VDD
V
VDD – 0.30
2.5
VDD
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
IDDA
Analog Supply Current
30
mA
IDD
Power Supply Current
113
mA
IDDOA&B
Output Supply Current
72
mA
Table 10. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA =
-40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
Test Conditions
Minimum
VDD = 3.3V
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
IIH
Input High
Current
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
VDD = VIN = 2.625V or 3.465V
IIL
Input Low
Current
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
VDD = 2.625V or 3.465V,
VIN = 0V
Typical
-5
µA
Table 11. LVDS 3.3V DC Characteristics, VDD = VDDOA = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
©2018 Integrated Device Technology, Inc.
Test Conditions
Minimum
200
1.1
6
Typical
Maximum
Units
550
mV
50
mV
1.3
V
50
mV
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841N254B Datasheet
Table 12. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
80
Shunt Capacitance
7
pF
DC Electrical Characteristics
Table 13. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
Output Frequency
F_SEL [1:0] = 00
156.25
MHz
F_SEL [1:0] = 01
125
MHz
F_SEL [1:0] = 10
100
MHz
F_SEL [1:0] = 11
250
MHz
REF_CLK
25
MHz
156.25MHz, Integration Range:
1MHz – 20MHz
0.27
ps
156.25MHz, Integration Range:
12kHz – 20MHz
0.32
ps
125MHz, Integration Range:
1MHz – 20MHz
0.33
ps
125MHz,Integration Range:
12kHz – 20MHz
0.37
ps
156.25MHz, Offset: 100Hz
-91.6
dBc/Hz
156.25MHz, Offset: 1kHz
-120.8
dBc/Hz
156.25MHz, Offset: 10kHz
-132.2
dBc/Hz
156.25MHz, Offset: 100kHz
-135.0
dBc/Hz
From DC to 50MHz
-50
dB
Between QAx/nQAx & QBx/nQBx
1.8
fREF
Reference Frequency
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
N
Single-Side Band Noise Power
Minimum
PSNR
Power Supply Noise Rejection
tsk(o)
Output Skew
NOTE 2, 3
tsk(b)
Bank Skew
NOTE 3, 4
t R / tF
Output Rise/Fall
Time
tLOCK
PLL Lock Time
VRB
Ring-back Voltage
Margin; NOTE 5, 6
QBx, nQBx
-100
tSTABLE
Time before VRB is
Allowed; NOTE 5, 6
QBx, nQBx
500
QAx, nQAx
©2018 Integrated Device Technology, Inc.
20% to 80%
7
100
Typical
Maximum
Units
2.7
ns
55
ps
400
ps
20
ms
100
mV
ps
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841N254B Datasheet
Table 13. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VMAX
Absolute Maximum
Output Voltage;
NOTE 7, 8
QBx, nQBx
VMIN
Absolute Minimum
Output Voltage;
NOTE 7, 9
QBx, nQBx
-300
VCROSS
Absolute Crossing
Voltage;
NOTE 7, 10, 11
QBx, nQBx
100
VCROSS
Total Variation of
VCROSS over all
edges;
NOTE 7, 10, 12
QBx, nQBx
Rise/Fall Edge Rate;
NOTE 5, 13
QBx, nQBx
Output Duty Cycle;
NOTE 5
Output Duty Cycle
odc
Test Conditions
Minimum
Typical
Maximum
Units
1150
mV
mV
350
mV
140
mV
0.6
5.5
V/ns
QBx, nQBx
47
53
%
QAx, nQAx
47
53
%
Measured between
-150mV to 150mV
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Please refer to the phase noise plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed
to drop back into the VRB ±100mV differential range.
NOTE 7: Measurement taken from single ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS for
any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through the
measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
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841N254B Datasheet
Typical Phase Noise at 156.25MHz (3.3V)
Filter
156.25MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.32ps (typical)
Noise Power (dBc/Hz)
Raw Phase Noise Data
Phase Noise Result by adding a
filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (3.3V)
Filter
156.25MHz
RMS Phase Jitter (Random)
1MHz to 20MHz = 0.27ps (typical)
Noise Power (dBc/Hz)
Raw Phase Noise Data
Phase Noise Result by adding a
filter to raw data
Offset Frequency (Hz)
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841N254B Datasheet
Parameter Measurement Information
Figure 1. 3.3V LVDS Output Load Test Circuit
3.3V ±5%
VDD,
VDDOA,
VDDA
Figure 2. 3.3V HCSL Output Load Test Circuit
3.3V±5%
3.3V±5%
VDD,
VDDOB
VDDA
Figure 3. 2.5V HCSL Output Load Test Circuit
2.5V±5%
2.5V±5%
VDD,
VDDOB
VDDA
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841N254B Datasheet
Figure 4. 2.5V LVDS Output Load Test Circuit
SCOPE
2.5V±5%
POWER SUPPLY
+ Float GND –
VDD,
VDDOA,
Qx
VDDA
nQx
Figure 5. 3.3V HCSL Output Load Test Circuit
3.3V±5%
3.3V±5%
VDD,
VDDOB
VDDA
This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o)
measurements.
Figure 6. 2.5V HCSL Output Load Test Circuit
2.5V±5%
2.5V±5%
VDD,
VDDOB
VDDA
This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o)
measurements.
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841N254B Datasheet
Figure 7. RMS Phase Jitter
Noise Power
Phase Noise Plot
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Figure 8. Output Skew
nQx
Qx
nQy
Qy
Figure 9. Differential Measurement Points for Ringback
TSTABLE
VRB
+150mV
VRB = +100mV
0.0V
VRB = -100mV
-150mV
Q - nQ
VRB
TSTABLE
Figure 10. LVDS Output Duty Cycle/Pulse Width/Period
nQA[0:1]
QA[0:1]
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841N254B Datasheet
Figure 11. Bank Skew
nQX0
QX1
nQX0
QX1
tsk(b)
Where X = Bank A or Bank B
Figure 12. Differential Measurement Points for Duty Cycle/Period
Figure 13. HCSL Differential Measurement Points for Rise/Fall Time
Figure 14. Single-ended Measurement Points for Delta Cross Point
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841N254B Datasheet
Figure 15. Offset Voltage Setup
Figure 16. LVDS Rise/Fall Time
nQA[0:1]
80%
80%
VOD
QA[0:1]
20%
20%
tR
tF
Figure 17. Single-ended Measurement Points for Absolute Cross Point/Swing
Figure 18. Differential Output Voltage Setup
©2018 Integrated Device Technology, Inc.
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April 17, 2018
841N254B Datasheet
Applications Information
Recommendations for Unused Input Pins
Inputs
REF_CLK Input
For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a
1k resistor can be tied from the REF_CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor
can be used.
Outputs
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there
is no trace attached.
Differential Outputs
All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Interface to IDT S-RIO Switches
The 841N254B is designed for driving the differential reference clock input (REF_CLK) of IDT’s S-RIO 1.3 and 2.0 switch devices. Both
the LVDS and the HCSL outputs of the ICS841N254BI have the low-jitter, differential voltage and impedance characteristics required to
provide a high-quality 156.25MHz clock signal for both S-RIO 1.3 and 2.0 switch devices. Please see Figure 19 and Figure 20 for
suggested interfaces. The interfaces differ by the driving output, LVDS and HCSL, and the corresponding source termination method. In
both figures, the AC-coupling capacitors are mandatory by the IDT S-RIO switch devices. The differential REF_CLK input is internally
re-biased and AC-terminated. Both interface circuits are optimized for 50 transmission lines and generate the voltage swing required to
reliably drive the clock reference input of a IDT S-RIO switch. Please refer to IDT’s S-RIO device datasheet for more details.
Figure 19. LVDS-to-S-RIO 2.0 Reference Clock Interface
QAn
LVDS
REF_CLK_P
T= 50
LI
CI
RL
VBIAS
LI
RL
+
REF_CLK
-
CI
ICS841N254BI
IDT S-RIO 1.3, 2.0 Switch
©2018 Integrated Device Technology, Inc.
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April 17, 2018
841N254B Datasheet
Figure 19 shows the recommended interface circuit for driving the 156.25MHz reference clock of an IDT S-RIO 2.0 switch by a LVDS
output (QA0, QA1) of the ICS841N254BI. The LVDS-to-differential interface as shown in Figure 19 does not require any external
termination resistors: the ICS841N254BI driver contains an internal source termination at QA0 and QA1. The differential REF_CLK input
contains an internal AC-termination (RL) and re-bias (VBIAS).
Figure 20 shows the interface circuit for driving the 156.25MHz reference clock of an IDT S-RIO 2.0 switch by an HCSL output of the
841N254B (QB0, QB1): The HCSL-to-differential interface requires external termination resistors (22...33 and 50) for source
termination, which should be placed close the driver (QB0, QB1).
Figure 20. HCSL-to-S-RIO 2.0 Reference Clock Interface
QBn
REF_CLK_P
HCSL nQBn
T= 50
22...33
LI
CI
RL
VBIAS
22...33
49.9
49.9
RL
LI
+
REF_CLK
-
CI
IDT S-RIO 1.3, 2.0 Switch
ICS841N254BI
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise. Figure 21 shows an example of the interface diagram for a high speed
3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance.
For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The
values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 22 shows an example of
the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input.
It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can
be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input.
Figure 21. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
Zo = Ro + Rs
R2
100
.1uf
LVCMOS Driver
©2018 Integrated Device Technology, Inc.
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April 17, 2018
841N254B Datasheet
Figure 22. LVPECL Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
R1
50
LVPECL Driver
R2
50
R3
50
HCSL Recommended Termination
Figure 23 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output types. All traces should be 50 impedance single-ended or 100
differential
Figure 23. Recommended Source Termination (Where the driver and receiver will be on separate PCBs)
0.5" Max
L1
L1
Rs
22 to 33 +/-5%
1-14"
0-0.2"
0.5 - 3.5"
L2
L4
L5
L2
L4
L5
PCI Expres s
PCI Expres s
Driver
Connector
0-0.2"
Rt
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Figure 24 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0 to 33. All traces should be 50 impedance single-ended or 100 differential.
©2018 Integrated Device Technology, Inc.
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April 17, 2018
841N254B Datasheet
Figure 24. Recommended Termination (Where a point-to-point connection can be used)
0.5" Max
L1
L1
Rs
0 to 33
0 to 33
0-18"
0-0.2"
L2
L3
L2
L3
PCI Expres s
49.9 +/- 5%
Rt
Driver
LVDS Driver Termination
A general LVDS interface is shown in Figure 25. Standard termination for LVDS type output structure requires both a 100 parallel
resistor at the receiver and a 100 differential transmission line environment. In order to avoid any transmission line reflection issues,
the 100 resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of
output structures: current source and voltage source. The standard termination schematic as shown in Figure 25 can be used with either
type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input
range of the input receivers should be verified for compatibility with the output.
Figure 25. Typical LVDS Driver Termination
+
LVDS Driver
LVDS
Receiver
100Ω
–
100Ω Differential Transmission Line
©2018 Integrated Device Technology, Inc.
18
April 17, 2018
841N254B Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 26. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is
also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug
and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.
Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 26. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to scale)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Schematic Layout
Figure 27 shows an example of 841N254B application schematic. In this example, the device is operated at VDD = VDDOA = VDDOB =
3.3V. The 12pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the
frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this
device, the crystal load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 841N254B provides separate power supplies to isolate any high switching noise from coupling
into the internal PLL.
In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the PCB.
©2018 Integrated Device Technology, Inc.
19
April 17, 2018
841N254B Datasheet
Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all devices.
The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are properly set.
Figure 27. 841N254B Application Schematic
L ogic Control Input E xamples
Set Logic
Inp ut t o
'1'
S et Log ic
Input to
'0'
V DD
R U1
1K
QB0
VD D
RU2
N ot I ns t al l
To Logic
Input
pins
33
Zo = 50
+
nQB0
R5
33
Zo = 50
-
TL3
To Logic
Input
pins
R D1
N ot I ns t all
R4
TL2
R6
50
VDD O
C6
0.1u
RD2
1K
Using for P CI Express
Add-In C ard
R7
50
R2
QB 1
nQB 1
V DD
475
VD D
VDD=3.3V
R3
V DD A
10
VDDOA= VDDOB=3.3V
U1
V DD
GND
QB 0
nQB0
VDDOB
QB 1
nQB 1
GND
C7
10u
C4
0.1u
Optional
R9
VDD
33
QB 1
1
2
3
4
5
6
7
8
Q1
Ro ~ 7 Ohm R 8
Zo = 50 Ohm
REF _CLK
nOE A
43
VDD
nc
VDD A
nc
GN D
R EF _C LK
nOEA
VDD
IRE F
GN D
nQA0
QA0
V D D OA
nQA1
QA1
GN D
24
23
22
21
20
19
18
17
nQA0
QA0
VDD O
QB 1_33 Zo = 50
nQB1
R 10
+
TL5
-
TL6
R 11
50
LV DS Termination
nQA 1
3. 3V
2
-
BLM18BB 221SN 1
V D DO
F errit e Bead C 10
C9
0.1uF
R1
100
C8
0.1u
BLM18BB 221SN 1
1
+
Z o = 100 O hm D if f erent ial
VD D
C2
5pF
3.3V
QA1
B YP AS S
F _SE L0
F_S EL1
nOE B
RE F_S EL
XTAL_I N
XTA L_O U T
F
p
2
1
C1
5pF
X1
25MH z
R12
50
Using for PC I Express
Point-to-P oint
Connec tion
9
10
11
12
13
14
15
16
C5
0. 1u
33
nQB1_33 Zo = 50
nOE B
RE F_S EL
X TAL_IN
XT AL_OUT
VDD
B YP AS S
F _SE L0
F _S EL1
V DD
D riv er_LV CMOS
HCSL Term ina tion
32
31
30
29
28
27
26
25
V DD
C3
0.01u
C11
1
C 17
2
F errit e Bead C 13
10uF 0. 1uF
©2018 Integrated Device Technology, Inc.
0. 1uF
C 12
0. 1uF
20
VDD
C14
10uF 0. 1uF
April 17, 2018
841N254B Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 841N254B.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 841N254B is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
▪ Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX + IDDOA&B_MAX) = 3.465V *(113mA + 30mA + 72mA) = 744.98mW
▪ Power (HCSL_output)MAX = 44.5mW * 2 = 89.0mW
Total Power_MAX = (3.465V, with all outputs switching) = 744.98mW + 89.0mW = 833.98mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 37.7°C/W per Table 14.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.834W * 37.7°C/W = 116.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Table 14. Thermal Resistance JA for 32-Lead VFQFN, Forced Convection
JA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
©2018 Integrated Device Technology, Inc.
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
21
April 17, 2018
841N254B Datasheet
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 28.
Figure 28. HCSL Driver Circuit and Termination
VDD
IOUT = 17mA
VOUT
RREF =
475Ω ± 1%
RL
50Ω
IC
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50 load to ground.
The highest power dissipation occurs when VDD_MAX.
Power= (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.465V – 17mA * 50) * 17mA
Total Power Dissipation per output pair = 44.5mW
Reliability Information
Table 15. JA vs. Air Flow Table for a 32-lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37.7°C/W
32.9°C/W
29.5°C/W
Transistor Count
The transistor count for 841N254B is: 23,445
©2018 Integrated Device Technology, Inc.
22
April 17, 2018
841N254B Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/nlnlg-32-package-outline-50-x-50-mm-body-epad-315-x-315-050-mm-pitch-qfn
Ordering Information
Orderable Part Number
Marking
Package
Carrier Type
Temperature
841N254BKILF
ICS1N254BIL
Lead-Free 32-Lead VFQFN
Tray
-40C to 85C
841N254BKILFT
ICS1N254BIL
Lead-Free 32-Lead VFQFN
Tape and Reel
-40C to 85C
Revision History
Revision Date
Description of Change
April 17, 2018
Updated the package out drawings; however, no technical changes
Completed other minor changes throughout the document
May 23, 2016
Updated datasheet header/footer.
Deleted “ICS” prefix from part number throughout the datasheet.
November 4, 2013
Replacement part for ICS841N254AKI, per PCN# N1309-01.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2018 Integrated Device Technology, Inc.
23
April 17, 2018
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 1
32-VFQFPN, Package Outline Drawing
5.0 x 5.0 x 0.90 mm Body, Epad 3.15 x 3.15 mm.
NLG32P1, PSC-4171-01, Rev 02, Page 2
Package Revision History
Description
Date Created
Rev No.
April 12, 2018
Rev 02
New Format
Feb 8, 2016
Rev 01
Added "k: Value
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