841S012BKILF

Crystal-to-0.7V Differential HCSL/ LVCMOS Frequency Synthesizer GENERAL DESCRIPTION The ICS841S012I is an optimized PCIe, sRIO and IC S Gigabit Ethernet Frequency Synthesizer and a HiPerClockS™ member of HiperClock s™ family of high performance clock solutions from IDT. The ICS841S012I uses a 25MHz parallel resonant crystal to generate 33.33MHz - 200MHz clock signals, replacing multiple oscillator and fanout buffer solutions. The device supports ±0.25% center-spread, and -0.5% down- spread clocking with two spread select pins (SSC[1:0]). The VCO operates at a frequency of 2GHz. The device has three output banks: Bank A with two HCSL outputs, 100MHz – 250MHz; Bank B with seven 33.33MHz – 200MHz LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz LVCMOS/LVTTL output. All Banks A, B and C have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The low jitter character istic of the ICS841S012I makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet applications. Designed for networking and industrial applications, the ICS841S012I can also drive the highspeed clock inputs of communication processors, DSPs, switches and bridges. ICS841S012I DATA SHEET NRND FEATURES • Two 0.7V differential HCSL outputs (Bank A), configurable for PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock signals Eight LVCMOS/LVTTL outputs (Banks B/C), 18Ω typical output impedance Two REF_OUT LVCMOS/LVTTL clock outputs, 23Ω typical output impedance • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or one LVCMOS/LVTTL single-ended reference clock input • Supports the following output frequencies: HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz, 100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz • VCO: 2GHz • Spread spectrum clock: ±0.25% center-spread (typical) and -0.6% down-spread (typical) • PLL bypass and output enable • RMS period jitter: 20ps (typical), QB outputs • Full 3.3V supply mode • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package • Not Recommended for New Designs PIN ASSIGNMENT VDDOB QB6 GND QB5 VDDOB QB4 GND QB3 VDDOB QB2 GND QB1 QB0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VDD REF_OUT0 REF_OUT1 GND GND REF_IN VDD REF_SEL XTAL_IN XTAL_OUT BYPASS REF_OE nMR VDD 1 2 3 4 5 6 7 8 9 10 11 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDOC QC GND QBC_OE VDDA VDDA GND GND IREF QA0 nQA0 QA1 nQA1 VDD ICS841S012I 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE SSC1 SSC0 ICS841S012BKI REVISION A NOVEMBER 10, 2009 1 ©2009 Integrated Device Technology, Inc. GND VDD GND VDDOB ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER BLOCK DIAGRAM QA_OE Pullup F_SELA[1:0] Pulldown 2 QA0 BYPASS XTAL_IN Pulldown nQA0 ÷NA QA1 nQA1 25MHz OSC XTAL_OUT 0 1 PLL VCO 2GHz 0 Pulldown QB0 REF_IN 1 QB1 QB2 REF_SEL Pulldown M = ÷80 QB3 ÷NB QB4 F_SELB[2:0] Pulldown 3 QB5 IREF QB6 ÷NC F_SELC[2:0] nMR QBC_OE SSC[1:0] Pulldown Pullup Pullup Pullup 2 3 QC Spread Spectrum REF_OUT0 REF_OUT1 REF_OE Pulldown ICS841S012BKI REVISION A NOVEMBER 10, 2009 2 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 7, 14, 28, 29 2, 3 4, 5, 15, 27, 35, 36, 40, 46, 50, 54 6 8 9, 10 11 12 Name VDD REF_OUT0, REF_OUT1 GND REF_IN REF_SEL XTAL_IN, XTAL_OUT BYPASS REF_OE Power Output Power Input Input Input Input Input Type Description Core supply pins. Single-ended LVCMOS/LVTTL reference clock outputs. 23Ω typical output impedance. Power supply ground. Pulldown Single-ended LVCMOS/LVTTL reference clock input. Reference select pin. When HIGH selects REF_IN. When LOW, Pulldown selects crystal. LVCMOS/LVTTL interface levels. See Table 3E. Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. External tuning capacitor must be used for proper operation. When HIGH bypasses PLL. When LOW, selects PLL. Pulldown LVCMOS/LVTTL interface levels. See Table 3J. Active HIGH REF_OUT enables/disables pin. Pulldown LVCMOS/LVTTL interface levels. See Table 3H. Active LOW Master Reset. When logic LOW, the internal dividers are reset and the outputs are in high impedance (HI-Z). When logic HIGH, the Pullup internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3I. Pullup Pulldown SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D. Frequency select pins for QBx outputs. See Table 3B. LVCMOS/LVTTL interface levels. Frequency select pins for QC output. See Table 3C. LVCMOS/LVTTL interface levels. Frequency select pins for QAx/nQAx outputs. See Table 3A. LVCMOS/LVTTL interface levels. Output enable pin for Bank A outputs. LVCMOS/LVTTL interface levels. See Table 3F. Differential Bank A clock outputs. HCSL interface levels. External fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode QAx/nQAx clock outputs. Analog supply pin. Output enable pin for Bank B and Bank C outputs. LVCMOS/LVTTL Interface levels. See Table 3G. Single-ended Bank C clock output. LVCMOS/LVTTL interface levels. 18Ω typical output impedance. Output supply pin for QC LVCMOS output. 13 16, 17 18, 19, 20 21, 22, 23 24, 25 26 30, 31 32, 33 34 37, 38 39 41 42 nMR SSC1, SSC0 F_SELB2, F_SELB1, F_SELB0 F_SELC2, F_SELC1, F_SELC0 F_SELA1, F_SELA0 QA_OE nQA1, QA1 nQA0, QA0 IREF VDDA QBC_OE QC VDDOC Input Input Input Input Input Input Output Output Power Input Output Power Pulldown Pulldown Pullup Pullup 43, 48, 52, 56 VDDOB Power Output supply pins for QBx LVCMOS outputs. 44, 45, QB0, QB1, Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 18Ω 47, 49, QB2, QB3, Output typical output impedance. 51, 53, 55 QB4, QB5, QB6 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS841S012BKI REVISION A NOVEMBER 10, 2009 3 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance QB[0:6], QC REF_OUT[1:0] QB[0:6], QC VDD, VDDOB, VDDOC = 3.465V Test Conditions Minimum Typical 4 4 51 51 18 23 Maximum Units pF pF kΩ kΩ Ω Ω TABLE 3A. F_SELA FREQUENCY SELECT FUNCTION TABLE Inputs F_SELA1 L L H H F_SELA0 L H L H M Divider Value 80 80 80 80 NA Divider Value 20 16 10 8 Output Frequency (25MHz Ref.) QA[0:1]/nQA[0:1] (MHz) 100 (default) 125 200 250 TABLE 3B. F_SELB FREQUENCY SELECT FUNCTION TABLE Inputs F_SELB2 L L L L H H H H F_SELB1 L L H H L L H H F_SELB0 L H L H L H L H M Divider Value 80 80 80 80 80 80 80 80 NB Divider Value 60 40 30 20 16 15 12 10 Output Frequency (25MHz Ref.) QB[0:6] (MHz) 33.33 (default) 50 66.67 10 0 125 133.33 166.67 200 TABLE 3C. F_SELC FREQUENCY SELECT FUNCTION TABLE Inputs F_SELC2 L L L L H H H H F_SELC1 L L H H L L H H F_SELC0 L H L H L H L H M Divider Value 80 80 80 80 80 80 80 80 NC Divider Value 60 40 30 20 16 15 12 10 Output Frequency (25MHz Ref.) QC (MHz) 33.33 (default) 50 66.67 100 125 133.33 166.67 200 ICS841S012BKI REVISION A NOVEMBER 10, 2009 4 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 3D. SSC FUNCTION TABLE Input SSC1 0 0 1 1 SSC0 0 1 0 1 Mode 0 to -0.5% Down-spread ±0.25% Center-spread ±0.25% Center-spread SSC Off (default) TABLE 3E. REF_SEL FUNCTION TABLE Input REF_SEL 0 (default) 1 Input Reference XTAL REF_IN TABLE 3F. QA_OE FUNCTION TABLE Input QA_OE 0 1 (default) Function QA[0:1]/nQA[0:1] disabled (High-Impedance) QA[0:1]/nQA[0:1] enabled TABLE 3G. QBC_OE FUNCTION TABLE Input QBC_OE 0 1 (default) Function QB[0:6] and QC disabled (High-Impedance) QB[0:6] and QC enabled TABLE 3H. REF_OE FUNCTION TABLE Input REF_OE 0 (default) 1 Function REF_OUT[0:1] disabled (High-Impedance) REF_OUT[0:1] enabled TABLE 3I. nMR FUNCTION TABLE Input Function Device reset, output divider disabled 0 (High-Impedance) 1 (default) Output enabled NOTE: This device requires a reset signal after power-up to function properly. nMR TABLE 3J. BYPASS FUNCTION TABLE Input BYPASS 0 (default) 1 Function PLL Bypass (reference ÷N) ICS841S012BKI REVISION A NOVEMBER 10, 2009 5 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 31.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C Symbol VDD VDDA VDDOB, VDDOC IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current HCSL Loaded, LVCMOS No Load Test Conditions Minimum 3.135 VDD – 0.20 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 330 20 Units V V V mA mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH VIL Input High Voltage Input Low Voltage Input High Current QA_OE, QBC_OE, nMR, SSC0, SSC1, F_SELA[0:1], F_SELB[0:2]. F_SELC[0:2], REF_OE, BYPASS, REF_IN, REF_SEL QA_OE, QBC_OE, nMR, SSC0, SSC1, F_SELA[0:1], F_SELB[0:2]. F_SELC[0:2], REF_OE, BYPASS, REF_IN, REF_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V VDDOB, VDDOC = IOH = -2mA VDDOB, VDDOC = IOL = 2mA -150 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 10 150 Units V V µA µA IIH µA IIL Input Low Current -10 2.6 0.5 µA V V VOH VOL Output High Voltage Output Low Voltage TABLE 5. CRYSTAL CHARACTERISTICS Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical Fundamental 25 50 7 100 MHz Ω pF µW Maximum Units ICS841S012BKI REVISION A NOVEMBER 10, 2009 6 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 6. AC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter QB[0:6] Output Frequency Bank Skew; NOTE 1, 2 QA[0:1]/nQA[0:1] QC QB[0:6] QA[0:1]/nQA[0:1] Across Banks B and C (at Same Frequency) All Outputs at Same Frequency All Outputs at Same Frequency, REF_OE = 0 29 510 -150 100 600 350 ±150mV from crosspoint 20% - 80% 25 150 10 0 420 Test Conditions Minimum 33.33 10 0 33.33 Typical Maximum 200 250 200 80 50 160 65 100 100 10 20 33.33 1200 Units MHz MHz MHz ps ps ps ps ps ps ps ps kHz mV mV mV mV ps ns tsk(b) tsk(o) Output Skew; NOTE 1, 3 QA[0:1]/nQA[0:1] Cycle-to-Cycle Jitter ; NOTE 1 RMS Period Jitter tjit(cc) QB[0:6] QC QA[0:1]/nQA[0:1] tjit(per) FM VHIGH VLOW VCROSS ΔVCROSS tR / tF QB[0:6], QC SSC Modulation Banks A, B, C Frequency Voltage High; NOTE 4, 5 Voltage Low; NOTE 4, 6 Absolute Crossing Voltage; NOTE 4, 7, 8 Total Variation of VCROSS over all edges; NOTE 4, 7, 9 Bank A Output Rise/Fall Time Banks B, C Bank A 45 55 % odc Output Duty Cycle Banks B, C 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDOB, C/2. NOTE 4: Measurement taken from single-ended waveform. NOTE 5: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 6: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 9: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any par ticular system. See Parameter Measurement Information Section. ICS841S012BKI REVISION A NOVEMBER 10, 2009 7 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 3.3V±5% 1.65V±5% 1.65V±5% 3.3V±5% VDD, VDDOB, VDDOC SCOPE VDDA Qx VDD VDDA 0Ω 49.9Ω 50Ω Measurement Point LVCMOS GND HCSL 0Ω GND RREF = 475Ω 49.9Ω 50Ω 2pF Measurement Point 2pF -1.65V±5% 0V 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT VOH VREF VOL nQx Qx nQy Qy t sk(o) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) RMS PERIOD JITTER HCSL OUTPUT SKEW Qx:Qx V DDOX VDDOX 2 Qx 2 Qx:Qx V DDOX VDDOX 2 t sk(b) Qy 2 t sk(o) (where X = Bank B or Bank C) LVCMOS OUTPUT SKEW LVCMOS BANK SKEW ICS841S012BKI REVISION A NOVEMBER 10, 2009 8 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION, nQA[0:1] CONTINUED 80% QA[0:1] t cycle n 80% 20% ➤ t cycle n+1 ➤ QC, QB0:QB6 20% tR tF t jit(cc) = t cycle n – t cycle n+1 1000 Cycles DIFFERENTIAL CYCLE-TO-CYCLE JITTER nQ VCROSS_DELTA VCROSS_MIN Q Q VMIN SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT V DDOX Q C, QB0:QB6 t PW t PERIOD odc = t PW t PERIOD LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Rise Edge Rate +150mV 0.0V -150mV Q - nQ DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME ICS841S012BKI REVISION A NOVEMBER 10, 2009 ➤ 2 ➤ LVCMOS RISE/FALL TIME VMAX nQ VCROSS_MAX SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) 0.0V x 100% Q - nQ DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD Fall Edge Rate 9 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841S012I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDOB, and VDDOC should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01μF VDDA .01μF 10μF 10Ω FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. REF_IN INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_IN to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. We recommend that there is no trace attached. DIFFERENTIAL OUTPUT All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. ICS841S012BKI REVISION A NOVEMBER 10, 2009 10 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The ICS841S012I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. NOTE: External tuning capacitors must be used for proper operations. XTAL_IN C1 15p X1 18pF Parallel Crystal XTAL_OUT C2 22p FIGURE 2. CRYSTAL INPUT INTERFACE LVCMOS TO XTAL INTERFACE The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) VDD equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100 Ω . This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note the device performance is guaranteed by using a quartz crystal. VDD R1 Ro Rs Zo = 50 .1uf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE ICS841S012BKI REVISION A NOVEMBER 10, 2009 11 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER SPREAD SPECTRUM Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32kHz triangle waveform is used with 0.6% down-spread (+0.0% / 0.5%) from the nominal output frequency. An example of a triangle frequency modulation profile is shown in Figure 4A below. The ramp profile can be expressed as: • Fnom = Nominal Clock Frequency in Spread OFF mode • Fm = Nominal Modulation Frequency (30kHz) • δ = Modulation Factor (0.6% down spread) 1, 2Fm (1 - δ) fnom - 2 Fm x δ x Fnom x t when 1 < t < 1 2Fm Fm (1 - δ) fnom + 2 Fm x δ x Fnom x t when 0 < t < The ICS841S012BI triangle modulation frequency deviation will not exceed 0.7% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 4B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.7%. The resulting spectral reduction will be greater than 5dB, as shown in Figure 4B. It is important to note the ICS841S012DI 5dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. Fnom ➤ Δ − 10 dBm Frequency B A (1 - δ) Fnom 0.5/fm Time 1/fm ➤ δ = .6% ➤ FIGURE 4A. TRIANGLE FREQUENCY MODULATION FIGURE 4B. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN (A) SPREAD -S PECTRUM OFF (B) SPREAD -S PECTRUM ON ICS841S012BKI REVISION A NOVEMBER 10, 2009 12 ➤ ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) ICS841S012BKI REVISION A NOVEMBER 10, 2009 13 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER RECOMMENDED TERMINATION Figure 6A i s the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 6A. RECOMMENDED TERMINATION Figure 6B i s the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. FIGURE 6B. RECOMMENDED TERMINATION ICS841S012BKI REVISION A NOVEMBER 10, 2009 14 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER SCHEMATIC EXAMPLE Figure 7 shows an example of the ICS841S012I application schematic. In this example, the device is operated at VD D= VDDOB = VDDOC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1= 33pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of HCSL and one example of LVCMOS termination are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. Logic Control Input Examples QB0 VDD R1 VDD R2 VDDO VDD REF_OUT1 10 VDDA C6 0.01u R3 35 Zo = 50 Set Logic Input to '1' RU1 1K VDD Set Logic Input to '0' RU2 Not Install LVCMOS C5 10u To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins 30 Zo = 50 LVCMOS VDD 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VDDO VDDA C3 0.01u VDDOC QC GND QBC_OE VDDA VDDA GND GND IREF QA0 nQA0 QA1 nQA1 VDD 42 41 40 39 38 37 36 35 34 33 32 31 30 29 C4 10u R5 33 Zo = 50 TL3 R7 IREF QA0 nQA0 QA1 R8 50 R9 50 33 Zo = 50 TL5 + R4 10 U1 VDD Q1 Ro ~ 7 Ohm R6 43 REF_SEL Driv er_LVCMOS C1 15pF 25MHz, CL=18pF X1 XTAL_OUT C2 22pF ICS841S012i XTAL_IN BYPASS REF_OE nMR Zo = 50 Ohm REF_IN REF_OUT0 REF_OUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND SSC1 SSC0 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE GND VDD Note: External tuning capacitors must be used for proper operation. VDD REF_OUT0 REF_OUT1 GND GND REF_IN VDD REF_SEL XTAL_IN XTAL_OUT BYPASS REF_OE nMR VDD VDDOB QB6 GND QB5 VDDOB QB4 GND QB3 VDDOB QB2 GND QB1 QB0 VDDOB Using for PCI Express Add-In Card R10 475 Ohm 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SSC1 SSC0 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE Note: This device requires a reset signal at nMR after power-up to function properly. HCSL Termination Zo = 50 TL6 nQA1 Zo = 50 TL7 + - VDDO VDD (U1, 48) C9 0.1u (U1, 52) C10 0.1u (U1, 56) C11 0.1u (U1, 1) VDD (U1, 7) C13 0.1u (U1, 14) C14 0.1u (U1, 28) C15 0.1u (U1, 29) C16 0.1u VDD=3.3V VDDO=3.3V (U1, 42) VDDO C7 0.1u (U1, 43) C8 0.1u R11 50 R12 50 C12 0.1u Using for PCI Express Point-to-Point Connection FIGURE 7. ICS841S012I SCHEMATIC EXAMPLE ICS841S012BKI REVISION A NOVEMBER 10, 2009 15 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS841S012I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841S012I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation The maximum IDD current at 85° is 300mA. The HCSL output current (17mA per output pair) is included in this value. For power considerations, this output current is treated separately from the core current, so for power calculations, I = 300mA - 2 * 17mA = 266mA. DD • Power (core) = VDD_MAX * (IDD + IDDA ) = 3.465V * (266mA + 20mA) = 991.0mW Power (HCSL) = 44.5mW/Load Output Pair If all outputs are loaded, the total power is 2 * 44.5mW = 89mW LVCMOS Output Power Dissipation • Dynamic Power Dissipation at 200MHz (QB, QC) Power (200MHz) = CPD * Frequency * (VDDO)2 = 4pF * 200MHz * (3.465V)2 = 9.6mW per output Total Power (200MHz) = 9.6mW * 8 = 76.7mW • Dynamic Power Dissipation at 25MHz (REF_OUT) Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.2mW per output Total Power (25MHz) = 1.2mW * 2 = 2.4mW Total Power Dissipation • Total Power = Power (core) + Power (HCSL) + Total Power (200MHz) + Total Power (25MHz) = 991.0mW + 89mW + 76.7mW + 2.4mW = 1159mW ICS841S012BKI REVISION A NOVEMBER 10, 2009 16 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 1 meter per second air flow and a multi-layer board, the appropriate value is 31.4°C/W per Table 7. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.159W * 31.4°C/W = 121.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 56 LEAD VFQFN, FORCED CONVECTION θJA by Velocity (Meters per second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 1 27.5°C/W 2.5 24.6°C/W ICS841S012BKI REVISION A NOVEMBER 10, 2009 17 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. VDD IOUT = 17mA ➤ VOUT RREF = 475Ω ± 1% RL 50Ω IC FIGURE 8. HCSL DRIVER CIRCUIT AND TERMINATION HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs at maximum VDD . Power = (VDD_MAX – VOUT ) * IOUT, since VOUT = IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50Ω) * 17mA Total Power Dissipation per output pair = 44.5mW ICS841S012BKI REVISION A NOVEMBER 10, 2009 18 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 56 LEAD VFQFN θJA by Velocity (Meters per second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 1 27.5°C/W 2.5 24.6°C/W TRANSISTOR COUNT The transistor count for ICS841S012I is: 11,537 ICS841S012BKI REVISION A NOVEMBER 10, 2009 19 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER PACKAGE OUTLINE - K SUFFIX FOR 56 LEAD VFQFN S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L (Ref.) (N -1)x e (R ef.) N &N Even N 1 2 e (Ty p.) 2 If N & N are Even (N -1)x e OR To p View E2 E2 2 (Re f.) b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 N &N Odd Th er mal Ba se NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below. TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 5.05 0.3 4.35 8.0 5.35 0.55 0.18 0.50 BASIC 14 14 8.0 4.65 0.80 0 0.25 Reference 0.30 MINIMUM 56 1.0 0.05 MAXIMUM Reference Document: JEDEC Publication 95, MO-220 ICS841S012BKI REVISION A NOVEMBER 10, 2009 20 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature tray -40°C to 85°C 841S012BKILF ICS841S012BIL 56 lead "Lead-Free" VFQFN 841S012BKILFT ICS841S012BIL 56 lead "Lead-Free" VFQFN 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS841S012BKI REVISION A NOVEMBER 10, 2009 21 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev A A Table T4A Page 6 11 15 1 Description of Change Power Supply DC Characteristics Table - added Test Conditions to IDD row. Updated Figure 2, Cr ystal Input Interface from 33pF to 15pF/22pF. Updated Schematic Layout. Add NRND and bullet. Date 8/11/09 9/10/09 ICS841S012BKI REVISION A NOVEMBER 10, 2009 22 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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