IDTCV110NPVG8

IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV110N FEATURES: DESCRIPTION: • One high precision PLL for CPU, SSC, and N programming • One high precision PLL for SRC/PCI/SATA, SSC, and N programming • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Support spread spectrum modulation, down spread 0.5% • Support SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a higher frequency for maximum system computing power • Available in SSOP package IDTCV110N is a 56 pin clock device, compliant with Intel CK410 specifications. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. OUTPUTS: KEY SPECIFICATIONS: • 2*0.7V current –mode differential CPU CLK pair • 6*0.7V current –mode differential SRC CLK pair, one dedicated for SATA • One CPU_ITP/SRC selectable CLK pair • 9*PCI, 3 free running, 33.3MHz • 1*96MHz, 1*48MHz • 1*REF • CPU/SRC CLK cycle to cycle jitter < 85ps • SATA CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 250ps FUNCTIONAL BLOCK DIAGRAM PLL1 SSC N Programmable X1 CPU CLK Output Buffers Stop Logic CPU[1:0] CPU_ITP/SRC7 XTAL Osc Amp IREF REF X2 ITP_EN SDATA SCLK SM Bus Controller SRC CLK Output Buffer Stop Logic PLL2 SSC N Programmable SRC[6:1] PCI[5:0], PCIF[2:0] IREF VTT_PWRGD#/PD Control Logic 48MHz FSA.B.C 48MHz/96MHz Output BUffer PLL3 DOT96 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE MAY 2005 1 © 2005 Integrated Device Technology, Inc. DSC-6755/3 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VDDA 3.3V Core Supply Voltage Min VDD_PCI 1 56 PCI2 VDD 3.3V Logic Input Supply Voltage GND - 0.5 VSS_PCI 2 55 PCI1 TSTG Storage Temperature PCI3 3 54 PCI0 TAMBIENT Ambient Operating Temperature PCI4 4 53 FSC/TEST_SEL TCASE Case Temperature PCI5 5 52 REF ESD Prot Input ESD Protection VSS_PCI 6 51 VSS_REF VDD_PCI 7 50 XTAL_IN PCIF0/ITP_EN 8 49 XTAL_OUT PCIF1 9 48 VDD_REF PCIF2 10 47 SDA VDD48 11 46 SCL USB48 12 45 VSS_CPU VSS48 13 44 CPU0 DOT96 14 43 CPU0# DOT96# 15 42 VDD_CPU FSB/TEST_MODE 16 41 CPU1 VTT_PWRGD#/PD 17 40 CPU1# FSA 18 39 IREF SRC1 19 38 VSSA 20 37 VDDA VDD_SRC 21 36 CPU2_ITP/SRC7 SRC2 22 35 CPU2_ITP#/SRC7# SRC2# 23 34 VDD_SRC SRC3 24 33 SRC6 25 32 SRC6# SRC4 26 31 SRC5 SRC4# 27 30 SRC5# VDD_SRC 28 29 VSS_SRC 0 2000 Unit 4.6 V 4.6 V +150 °C +70 °C +115 °C V Human Body Model SRC1# SRC3# –65 Max NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SSOP TOP VIEW FREQUENCY SELECTION TABLE FSC, B, A CPU SRC[7:1] PCI USB DOT REF 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 Reserve 100 33.3 48 96 14.318 2 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Number Name Type Description 1 VDD_PCI PWR 3.3V 2 VSS_PCI GND GND 3 PCI3 OUT PCI clock 4 PCI4 OUT PCI clock 5 PCI5 OUT PCI clock 6 VSS_PCI GND GND 7 VDD_PCI PWR 3.3V 8 PCIF0/ITP_EN I/O PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2. 9 PCIF1 OUT PCI clock, free running 10 PCIF2 OUT PCI clock, free running 11 VDD48 PWR 3.3V 12 USB48 OUT 48MHz clock 13 VSS48 GND GND 14 DOT96 OUT 96MHz 0.7 current mode differential clock output 15 DOT96# OUT 96MHz 0.7 current mode differential clock output 16 FSB/TEST_MODE IN CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0. 17 VTT_PWRGD#/PD IN Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH) 18 FSA IN CPU frequency selection 19 SRC1 OUT Differential serial reference clock 20 SRC1# OUT Differential serial reference clock 21 VDD_SRC PWR 3.3V 22 SRC2 OUT Differential serial reference clock 23 SRC2# OUT Differential serial reference clock 24 SRC3 OUT Differential serial reference clock 25 SRC3# OUT Differential serial reference clock 26 SRC4 OUT Differential serial reference clock 27 SRC4# OUT Differential serial reference clock 28 VDD_SRC PWR 3.3V 29 VSS_SRC GND GND 30 SRC5# OUT Differential serial reference clock 31 SRC5 OUT Differential serial reference clock 32 SRC6# OUT Differential serial reference clock 33 SRC6 OUT Differential serial reference clock 34 VDD_SRC PWR 3.3V 35 CPU2_ITP#/SRC7# OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#. 36 CPU2_ITP/SRC7 OUT Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7. 37 VDDA PWR 3.3V 38 VSSA GND GND 39 IREF OUT Reference current for differential output buffer 40 CPU1# OUT Host 0.7 current mode differential clock output 41 CPU1 OUT Host 0.7 current mode differential clock output 42 VDD_CPU PWR 3.3V 3 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 43 CPU0# OUT Host 0.7 current mode differential clock output Description 44 CPU0 OUT Host 0.7 current mode differential clock output 45 VSS_CPU GND GND 46 SCL IN SMBus clock SMBus data 47 SDA I/O 48 VDD_REF PWR 3.3V 49 XTAL_OUT OUT XTAL output 50 XTAL_IN IN 51 VSS_REF GND XTAL input 52 REF OUT 53 FSC/TEST_SEL IN 54 PCI0 OUT PCI clock 55 PCI1 OUT PCI clock 56 PCI2 OUT PCI clock GND 14.318 MHz reference clock output CPU frequency selection. Selects test mode if pulled to above 2V when VTT_PWRGD# is asserted LOW. INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop INDEX BYTE WRITE INDEX BYTE READ Setting bit[11:18] = starting address, bit[20:27] = 01h. Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. 4 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CONTROL REGISTERS N PROGRAMMING PROCEDURE • • Use Index byte write. For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. 2. 3. • • • Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly. Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming. Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don’t write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes. FREQUENCY SELECTION TABLE SSC MAGNITUDE CONTROL, SMC SMC[2:0] 000 001 010 011 100 101 110 111 FS_C, B, A 101 001 011 010 000 100 110 111 -0.25 -0.5 -0.75 -1 ±0.125 ±0.25 ±0.375 ±0.5 RESOLUTION CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150 5 CPU 100 133 166 200 266 333 400 RESERVE IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 Reserve 1 SRC1, SRC1# Output enable Tristate Enable RW 1 2 SRC2, SRC2# Output enable Tristate Enable RW 1 3 SRC3, SRC3# Output enable Tristate Enable RW 1 4 SRC4, SRC4# Output enable Tristate Enable RW 1 5 SRC5, SRC5# Output enable Tristate Enable RW 1 6 SRC6, SRC6# Output enable Tristate Enable RW 1 7 CPU2, CPU2#/ Output enable Tristate Enable RW 1 SRC7, SRC7# BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 CPU[2:0], SRC[7:1], Spread Spectrum mode enable Spread off Spread on RW 0 PCI[5:0], PCIF[2:0] 1 CPU0, CPU0# Output enable Tristate Enable RW 1 2 CPU1, CPU1# Output enable Tristate Enable RW 1 3 Reserve 4 REF Output enable Tristate Enable RW 1 5 USB48 Output enable Tristate Enable RW 1 6 DOT96 Output enable Tristate Enable RW 1 7 PCIF0 Output enable Tristate Enable RW 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 0 PCIF1 Output enable Tristate Enable RW 1 1 PCIF2 Output enable Tristate Enable RW 1 2 PCI0 Output enable Tristate Enable RW 1 3 PCI1 Output enable Tristate Enable RW 1 4 PCI2 Output enable Tristate Enable RW 1 5 PCI3 Output enable Tristate Enable RW 1 6 PCI4 Output enable Tristate Enable RW 1 7 PCI5 Output enable Tristate Enable RW 1 0 BYTE 2 6 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 3 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 Reserve 1 SRC1 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 2 SRC2 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 3 SRC3 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 4 SRC4 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 5 SRC5 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 6 SRC6 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 7 SRC7 Allow controlled by software PCI_STOP, byte 6, bit 3, assertion Free running, not affected by PCI_STOP Stopped with PCI_STOP RW 0 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 Reserve RW 1 1 Reserve RW 1 2 Reserve RW 1 3 PCIF0 RW 0 RW 0 RW 0 RW 0 BYTE 4 4 PCIF1 5 PCIF2 6 DOT96 7 Reserve Allow controlled by software Not stopped Stopped with PCI_STOP, byte 6, bit 3, assertion by PCI_STOP PCI_STOP Allow controlled by software Not stopped Stopped with PCI_STOP, byte 6, bit 3, assertion by PCI_STOP PCI_STOP Allow controlled by software Not stopped Stopped with PCI_STOP, byte 6, bit 3, assertion by PCI_STOP PCI_STOP DOT96 power down drive mode Driven in power down Tristate 0 BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 0 CPU0, CPU0# CPU0 PWRDWN drive mode Driven in power down Tristate in power down RW 0 1 CPU1, CPU1# CPU1 PWRDWN drive mode Driven in power down Tristate in power down RW 0 2 CPU2, CPU2# CPU2 PWRDWN drive mode Driven in power down Tristate in power down RW 0 3 SRC[7:1], SRC[7:1]# SRC PWRDWN drive mode Driven in power down Tristate in power down RW 0 4 Reserve 0 5 Reserve 0 6 Reserve 0 7 SRC[7:1], SRC[7:1]# SRC PCI_STOP drive mode Driven in PCI_STOP 7 Tristate when stopped RW 0 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 6 Bit Output(s) Affected Description / Function 0 CPU[2:0] FSA latched value on power up R 1 CPU[2:0] FSB latched value on power up R 2 CPU[2:0] FSC latched value on power up R 3 PCI, SRC Software PCI_STOP control for PCI and SRC CLK Stop all PCI, PCIF, and SRC which can be stopped by PCI_STOP# Software STOP Disabled 4 REF REF drive strength 1x drive 2x drive 5 Reserve 6 0 1 Type RW Power On 1 1 0 Test clock mode entry control Normal operation Test mode, controlled RW 0 by Byte 6, Bit 7 7 CPU, SRC, PCI PCIF, REF, USB48, DOT96 Only valid when Byte 6, Bit 7 is HIGH Hi-Z REF/N Output(s) Affected Description / Function 0 1 0 BYTE 7 Bit Type Power On 0 Vendor ID R 1 1 Vendor ID R 0 2 Vendor ID R 1 3 Vendor ID R 0 4 Revision ID R 0 5 Revision ID R 1 6 Revision ID R 1 7 Revision ID R 0 BYTE 8 Bit Output(s) Affected 0 1 2 3 4 5 6 7 One cycle read Reserve USB48 SRC, PLL2, SSC enable Description / Function 0 1 Type Power On N Programming enable disable Disable enable enable USB 48 Strength control USB PLL power down SRC PLL power down CPU PLL power down Only valid when Byte1 bit0 is 1 1x normal normal normal disable 2x Power down Power down Power down enable RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 1 8 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 9 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 SRC SMC0 SRC SMC1 SRC SMC2 Reserve CPU SMC0 CPU SMC1 CPU SMC2 SRC/PCI SSC control see SMC table 0 1 CPU PLL SSC control see SMC table Must be 0 Must be 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 0 1 0 0 0 (Must be 0) BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 17 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 CPU_N0, LSB CPU_N1 CPU_N2 CPU_N3 CPU_N4 CPU_N5 CPU_N6 CPU_N7, MSB CPU CLK = N* Resolution see Resolution table 0 1 Type Power On RW RW RW RW RW RW RW RW BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. BYTE 25 Bit Output(s) Affected Description / Function 0 1 2 3 4 5 6 7 SRC_N0, LSB SRC_N1 SRC_N2 SRC_N3 SRC_N4 SRC_N5 SRC_N6 SRC_N7, MSB SRC f = N*SRC Resolution Resolution = 0.666667 100MHz N= 150 0 1 Type RW RW RW RW RW RW RW RW BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER. 9 Power On IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE APPLICATION NOTE Bits Strength 111 0.6x 011 0.8x 001 1x 000 1.2x Byte 18, bit[2:0] controls PCIF[2:0] strength. Byte 26, bit[2:0] controls PCI[5:0] strength. Byte 27, Byte 28 controls the magnitude of the SRC spread. (1) Byte 30, Byte 31 sets the center of the frequency of the SRC. (1) Byte 23, bit[3:0] controls the CPU PLL spread. NOTE: 1. Write byte 9 prior to Bytes 27, 28, 30, and 31. ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS LOW Voltage, HIGH Threshold For FSA.B.C test_mode 0.7 — VDD + 0.3 V VIL_FS LOW Voltage, LOW Threshold For FSA.B.C test_mode VSS - 0.3 — 0.35 V Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 mA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current All differential pairs driven — — 70 mA All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH IIL Parameter FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB Test Conditions Logic inputs — — 5 Output pin capacitance — — 6 pF X1 and X2 pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_PD(2) CPU output enable after PD de-assertion — — 300 us TFALL_PD(2) Fall time of PD — — 5 ns TRISE_PD(3) Rise time of PD — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 10 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 1150 mV VLOW Voltage LOW(2) oscilloscope math function –300 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal / -0.5% spread 2.4993 — 2.5133 333.33MHz nominal / -0.5% spread 2.9991 — 3.016 266.66MHz nominal / -0.5% spread 3.7489 — 3.77 200MHz nominal / -0.5% spread 4.9985 — 5.0266 166.66MHz nominal / -0.5% spread 5.9982 — 6.032 133.33MHz nominal / -0.5% spread 7.4978 — 7.54 100MHz nominal / -0.5% spread 9.997 — 10.0533 96MHz nominal 10.4135 — 10.4198 400MHz nominal / -0.5% spread 2.4143 — — 333.33MHz nominal / -0.5% spread 2.9141 — — 266.66MHz nominal / -0.5% spread 3.6639 — — 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 4.9135 5.9132 — — — — 133.33MHz nominal / -0.5% spread 7.4128 — — 100MHz nominal / -0.5% spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps — — 125 ps — — 125 ps 45 — 55 % d-tR Rise Time Variation(2) d-tF Fall Time Variation(2) dT3 Duty Cycle(2) Measurement from differential waveform NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 11 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol tSK3 Parameter Skew, CPU[1:0](2) Skew, CPU2(2) Skew, Test Conditions VT = 50% SRC(2) Jitter, Cycle to Cycle, CPU[1:0](2) tJCYC-CYC Jitter, Cycle to Cycle, CPU2(2) Measurement from differential waveform Jitter, Cycle to Cycle, SRC(2) Jitter, Cycle to Cycle, DOT96(2) Min. — — Typ. — — Max. 100 250 — — 250 — — 85 — — 100 — — — — 125 250 Unit ps ps NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol Parameter Test Conditions ppm Static Error(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values TPERIOD Clock Period(2) — — 0 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 2.4 — — VOH Output HIGH Voltage VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — IOL Output LOW Current IOH = -1mA V mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 500 ps VT = 1.5V — — 500 ps Cycle(1) dT1 Duty tSK1 Skew(1) tJCYC-CYC Jitter, Cycle to Cycle(1) NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 12 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions ppm Static Error(1,2) See Tperiod Min. - Max. values TPERIOD Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage IOH = -1mA VOL Output LOW Voltage IOH Output HIGH Current IOL Output LOW Current Min. Typ. Max. Unit — — 0 ppm 20.8257 — 20.834 ns 2.4 — — V IOL = 1mA — — 0.55 V VOH at Min. = 1V -29 — — mA VOH at Max. = 3.135V — — -23 VOL at Min. = 1.95V 29 — — mA VOL at Max. = 0.4V — — 27 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.5 — 1.2 ns VT = 1.5V 45 — 55 % — — 350 ps Min. Typ. Max. Unit — — 0 ppm 69.827 — 69.855 ns dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) IOH = -1mA 2.4 — — V VOL Output LOW Voltage(1) IOL = 1mA — — 0.4 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 IOL Output LOW Current VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns tF1 Fall Time(1) VOL = 0.8V, VOH = 2V 0.3 — 1.2 ns VT = 1.5V 45 — 55 % VT = 1.5V — — 1000 ps ppm TPERIOD dT1 tJCYC-CYC Duty Cycle(1) Jitter, Cycle to Cycle(1) NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 13 mA IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PCI STOP FUNCTIONALITY If PCIF (2:0) and SRC clocks are set to be free-running through SMBus programming, they will ignore the PCI_STOP register bit. PCI_STOP (Byte 6 bit 3) CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 1 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz 0 Normal Normal IREF * 6 or float Low Low 48MHz Normal Normal 14.318MHz PD, POWER DOWN PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches. PD CPU CPU# SRC SRC# PCIF/PCI USB DOT96 DOT96# REF 0 Normal Normal Normal Normal 33MHz 48MHz Normal Normal 14.318MHz 1 IREF * 2 or float Float IREF * 2 or float Float Low Low IREF * 2 or float Float Low PD ASSERTION PD CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 14 IDTCV110N PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD DE-ASSERTION The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD deassertion. tSTAB