IDTCV115-2PVG

IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR FEATURES: DESCRIPTION: • • • • • • IDTCV115-2 is a 56 pin clock device, complying the latest Intel CK410 requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. One high precision N Programming PLL for CPU One high precision N Programming PLL for SRC/PCI One high precision PLL for SATA One high precision PLL for 96MHz/48MHz Band-gap circuit for differential outputs Support multiple spread spectrum modulation, down and center • Support SMBus block read/write, index read/write • Selectable output strength for REF, PCI, and 48MHz • Available in SSOP package KEY SPECIFICATION: • • • • CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm FUNCTIONAL BLOCK DIAGRAM SATA PLL SCC SRC4 - SATA SATA/ PCI[4:0], PCIF[2:0] PCI/ PCIEX PLL SCC N Programming 14.318MHz Osc PCIE/ SRC[6:5] [3:1] MUX CPU PLL SCC N Programming Host/ CPU_ITP/ SRC7 CPU[1:0] USB48 48MHz/ DOT96 Fixed PLL No SCC 96MHz/ RESET OUTPUT TABLE CPU CPU_ITP/SRC SRC SATA PCI/PCIF REF/PCI REF DOT96 24_48MHz RESET TURBO 2 1 5 1 8 1 1 1 1 1 2 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE APRIL 2004 1 © 2004 Integrated Device Technology, Inc. DSC 6544/9 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION TEST MODE SELECT(1) If TEST_SEL sampled above 2V at VTT_PWRGD active LOW (1) (2) VDD_PCI 1 56 PCI1 VSS_PCI 2 55 PCI0 PCI2 3 54 FS_A(REF1/PCI5) PCI3 4 53 VDD_suspend PCI4/Turbo1 5 52 FS_C/REF0 VSS_PCI 6 51 VSS_REF Pin38 (test_mode) 1 0 (3) VDD_PCI 7 50 XTAL_IN PCIF0/ITP_EN 8 49 XTAL_OUT PCIF1 9 48 VDD_REF PCIF2 10 47 SCL(2) VDD_48 11 46 SDA FS_B/USB48MHz 12 45 CPUT0 CPU REF/N Hi-Z SRC REF/N Hi-Z PCI/F REF/N Hi-Z REF REF Hi-Z DOT96 REF/N Hi-Z USB REF/N Hi-Z NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, ITP_EN (2) ITP_EN 1 0 VSS_48 13 44 CPUC0 DOT_96 14 43 VDD_CPU DOT_96# 15 42 CPUT1 VTT_PWRGD/PWRDWN# 16 41 CPUC1 SRCT1 17 40 VSS_CPU SRCC1 18 39 IREF VDD_SRC 19 38 Reset# VSS 20 37 Turbo2 SRCT2 21 36 CPU2_ITP/SRCT7 SRCC2 22 35 CPU2_ITP/SRCC7 SRCT3 23 34 VDD_SRC pin 35 CPUC2_ITP SRCC7 pin 36 CPUT_ITP SRCT7 (4) SRCC3 24 33 SRCT6 VSS_GND 25 32 SRCC6 SRCT4_SATA 26 31 SRCT5 SRCC4_SATA 27 30 SRCC5 VDD_SRC 28 29 VSS_SRC NOTES: 1. After power on, pin 5 is tristate (see Byte 30 and Byte 2). 2. ~ 130KΩ internal pull-up. 3. After power on, REF1/PCI5 is tristate (see Byte 1). 4. Disabled at power on. SSOP TOP VIEW HW FREQUENCY SELECTION TABLE FSC, B, A CPU SRC4_SATA SRC[3:1], SCR[7:5] PCI USB DOT REF 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 Reserve 100 100 33.3 48 96 14.318 2 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Pin Number 1 2 3 4 5 Name VDD_PCI VSS_PCI PCI2 PCI3 PCI4/Turbo1 Type PWR GND OUT OUT OUT 6 7 8 9 10 11 12 13 14 15 16 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_48 FS_B/USB48 VSS_48 DOT_96T DOT_96C VTT_PWRGD/PWRDWN# GND PWR I/0 OUT OUT PWR I/O GND OUT OUT I/O 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SRCT1 SRCC1 VDD_SRC VSS SRCT2 SRCC2 SRCT3 SRCC3 VSS SRCT4_SATA SRCC4_SATA VDD_SRC VSS_SRC SRCC5 SRCT5 SRCC6 SRCT6 VDD_SRC CPUC2_ITP/ SRCC7 CPUT2_ITP/ SRCT7 Turbo2 Reset# IREF VSS CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 SDA OUT OUT PWR GND OUT OUT OUT OUT GND OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT IN OUT OUT GND OUT OUT PWR OUT OUT I/O Description 3.3V GND PCI clock PCI clock PCI clock output or Turbo input. Byte 30, bit 3 mode selection. Byte 30, bit 3 = 1, PCI clock. 0 = Turbo mode. In Turbo mode, 1 = load TCN and TPN into CPU and SRC PLL. GND 3.3V PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD assertion), HIGH = CPU_2. PCI clock, PCI clock, 3.3V CPU Frequency selection. 48MHz afterward. GND 96MHz 0.7V current mode differential clock output 96MHz 0.7V current mode differential clock output 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and PCIF_0/ITP_EN inputs. After VTT_PWRGD assertion, active HIGH, becomes a real-time input for asserting power down (active LOW). Internal pull HIGH. Differential Serial reference clock Differential Serial reference clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock GND SATA clock SATA clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7 Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD assertion = SRC_7 Load TCN2 into CPU PLL. Disabled at power on (see Byte 26). Reset output Reference current for differential output buffer GND Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output 3.3V Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output SMBus data 3 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONT.) Pin Number Name Type 47 48 49 50 51 52 53 54 SCL VDD_REF XTAL_OUT XTAL_IN VSS_REF FS_C/REF0 VDD_Suspend FS_A(REF1/PCI5) IN PWR OUT IN GND I/O POWER I/O 55 56 PCI0 PCI1 OUT OUT Description SMBus CLK 3.3V Xtal output Xtal input GND CPU frequency selection input at VTT_PWRGD assertion. 14.318 reference clock output afterward. Keep supply 3.3V in the power down CPU frequency selection input at VTT_PWRGD assertion. 14.318 or PCI reference clock output afterward, SMBus selectable. Tristate at power on. PCI clock PCI clock SM PROTOCOL INDEX BLOCK WRITE PROTOCOL Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master INDEX BLOCK READ PROTOCOL Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37). Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N, (0 is not valid Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 # of bits 1 8 1 8 1 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave 38 39-46 47 48-55 1 8 1 8 Master Slave Master Slave Master Slave Master Description Start D2H Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3H Ack (Acknowledge) Byte count, N (block read back of N bytes), Byte 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop INDEX BYTE WRITE INDEX BYTE READ Setting bit[11:18] = starting address, bit[20:27] = 01h. Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit. 4 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE CB1_[2:0], CB2_[2:0], CPU MODE SELECTION CB[2:0] 101 001 011 010 000 100 110 111 RESOLUTION CPU CPU CPU CPU CPU CPU CPU SRC CPU Mode, MHz 100 133 166 200 266 333 400 RESERVE SSC MAGNITUDE CONTROL SMC[2:0] 000 001 010 011 100 101 110 111 N Resolution (MHz) 0.666667 0.888889 1.333333 1.333333 2.666667 2.666667 2.666667 0.666667 % 0.67% 0.67% 0.8% 0.67% 1.00% 0.8% 0.67% 0.67% PCI When Byte5 bit6 = 0 % OFF - 0.25 - 0.5 ±0.125 ±0.25 ±0.375 ±0.5 ±0.75 PCIS[1:0] 00 01 10 11 S_CBS[1:0], H_CBS[1:0] BAND SELECTION CBS[1:0] 00 01 10 11 = 100MHz mode = 133MHz mode = 166MHz mode = 200MHz mode = 266MHz mode = 333MHz mode = 400MHz mode (PCI Express) PCI 33.33 36.36 40 S_CNS, S_PNS, H_CNS,H_PNS N SELECTION NS[1:0] 00 01 10 11 FS[C,B,A] CB1_[2:0] CB2_[2:0] Don’t care Standard of Each CPU Mode (Band) N Selection 1 N Selection 2 Don’t care S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48) Str[1:0] 00 01 10 11 2L 1H 1L 2H Multiple loads Recommend Single loads USB48 Recommend Recommend Recommend Recommend Recommend 5 N= 150 150 125 150 100 125 150 150 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 CPUT2, CPUC2/ SRCT7, SRCC7 SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 (SATA) SRCT3, SRCC3 SRCT2, SRCC2 SRCT1, SRCC1 REF0 2x drive Output enable Tristate Enable RW 1 Output enable Output enable Output enable Output enable Output enable Output enable 2x drive enable Tristate Tristate Tristate Tristate Tristate Tristate 1x Enable Enable Enable Enable Enable Enable 2x RW RW RW RW RW RW RW 1 1 1 1 1 1 1 Recommended 6 5 4 3 2 1 0 BYTE 1 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 DOT96T, DOT96C USB48 REF1/PCI5 REF0 CPUT1, CPUC1 CPUT0, CPUC0 REF1/PCI5 Output enable Not bonded out Output enable Mode Select Output enable Output enable Output enable Output enable Tristate Tristate Tristate PCI5 Tristate Tristate Tristate Tristate Enable Enable Enable REF1 Enable Enable Enable Enable RW RW RW RW RW RW RW 1 1 1 0 1 1 1 0 Bit Output(s) Affected Description/Function 0 1 Type Power On 7 6 5 4 3 2 1 0 PCI4 PCI3 PCI2 PCI1 PCI0 PCIF2 PCIF1 PCIF0 Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 0 BYTE 2 BYTE 3 Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function SRCT[7:1] CPUT2 CPUT1 CPUT0 DOT96T FSC latched value on power up FSB latched value on power up FSA latched value on power up SRCT Pwrdwn drive mode CPUT2 Pwrdwn drive mode CPUT1 Pwrdwn drive mode CPUT0 Pwrdwn drive mode DOT96 power down drive mode 0 Driven in power down Driven in power down Driven in power down Driven in power down Driven in power down 6 1 Type Power On Tristate in power down Tristate in power down Tristate in power down Tristate in power down Tristate R R R RW RW RW RW RW 0 0 0 0 0 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 4 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 PCIFStr1 PCIFStr0 PCIStrC1 PCIStrC0 REFStr1 REFStr0 48MHStr1 48MHzStr0 PCIF strength selection 0 1 Type Power On 0 0 0 1 0 0 1 1 PCI strength selection REF strength selection USB48MHz0 strength selection BYTE 5 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 PCIPLLS PCIS1 PCI PLL select See PCIS table, only valid when Byte5 bit 6 = 0 See PCIS Table SATA PLL PCI EX PLL RW RW 0 0 During the Power Down Reset SM to default SM contents have no change RW RW 0 1 RW RW RW 0 1 0 Type Power On 4 3 PCIS0 SM control registers contents SATA_SMC2 SATA_SMC1 SATA_SMC0 SATA PLL spread spectrum magnitude control select (see SMC table) Bit Output(s) Affected Description / Function 7 WDHRB 6 WDSRB 5 4 3 2 1 0 SRC_SMC2 SRC_SMC1 SRC_SMC0 CPU_SMC2 CPU_SMC1 CPU_SMC0 Hard Alarm read back, reset by WD disable Soft Alarm read back, rest by WD disable SRC(PCIEXpress) PLL spread spectrum magnitude control select (see SMC table) CPU PLL spread spectrum control magnitude select (see SMC table) Output(s) Affected Description / Function 2 1 0 BYTE 6 0 1 R R RW RW RW RW RW RW 0 1 0 1 0 0 Type Power On BYTE 7 Bit 7 6 5 4 3 2 1 0 0 Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 1 0 0 0 0 0 1 0 1 7 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 8 Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 1 1 1 1 1 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 Type Power On BYTES 9 - 16 ARE DUMMY BITES BYTE 17 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CB1_2 CB1_1 CB1_0 CPU PLL Band Selection 1 (see CPU Mode Selection table) CB2_2 CB2_1 CB2_0 CN1_8 (MSB) CPU PLL Band Selection 2 (see CPU Mode Selection table) Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CN1_7 CN1_6 CN1_5 CN1_4 CN1_3 CN1_2 CN1_1 CN1_0 (LSB) 0 1 CPU PLL N selection 1 BYTE 18 0 1 CPU PLL N selection 1 CPU Frequency = N * Resolution (see Resolution table) BYTE 19 Bit Output(s) Affected 7 6 5 4 3 2 1 0 CN2_8 (MSB) CN2_7 CN2_6 CN2_5 CN2_4 CN2_3 CN2_2 CN2_1 Description / Function 0 1 0 1 0 0 1 0 1 1 CPU N selection 2 CPU Frequency = N * Resolution (see Resolution table) 8 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 20 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 CN2_0 (LSB) CPU N selection 2 0 1 PN1_8 (MSB) PN1_7 Type Power On RW RW 0 0 0 0 0 0 0 1 Type Power On RW RW RW RW RW RW RW RW 0 0 1 0 1 1 0 0 Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 Type Power On RW 0 RW RW RW RW 0 0 0 0 RW 0 0 0 BYTE 21 Bit Output(s) Affected 7 6 5 4 3 2 1 0 PN1_6 PN1_5 PN1_4 PN1_3 PN1_2 PN1_1 PN1_0 (LSB) PN2_8 (MSB) Description / Function SRC PLL (PCI Express) N Selection 1 SRC Frequency = N * Resolution Resolution = 0.666667 Bit Output(s) Affected Description / Function 7 6 5 4 3 2 1 0 PN2_7 PN2_6 PN2_5 PN2_4 PN2_3 PN2_2 PN2_1 PN2_0 (LSB) 0 1 BYTE 22 0 1 SRC PLL (PCI Express) N Selection 1 SRC Frequency = N * Resolution Resolution = 0.666667 BYTE 23 Bit Output(s) Affected Description / Function 7 S_CBS1 6 5 4 3 S_CBS0 S_CNS1 S_CNS0 S_PNS1 2 1 0 S_PNS0 Soft Alarm CPU PLL mode select (see S_CBS Band Selection Table) Soft Alarm CPU PLL N select (see S_CNS N Selection Table) Soft Alarm SRC PLL (PCI Express) N select (see S_PNS N Selection Table) 0 9 1 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 24 Bit Output(s) Affected Description / Function 7 6 5 4 3 H_CBS1 H_CBS0 H_CNS2 H_CNS0 H_PNS1 2 1 0 H_PNS0 Hard Alarm CPU PLL mode select (see H_CBS Band Selection table) Hard Alarm CPU PLL N select (see H_CNS N Selection table) Hard Alarm SRC PLL (PCI Express) N select (see H_PNS N selection table) 0 1 Type Power On RW RW RW RW RW 0 0 0 0 0 RW 0 0 0 Type Power On RW RW RW RW RW RW RW RW 0 0 0 0 1 0 1 1 BYTE 25 Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 WD Timer 7 (MSB) WD Timer 6 WD Timer 5 WD Timer 4 WD Timer 3 WD Timer 2 WD Timer 1 WD Timer 0 (LSB) Hard Alarm timer Default is 11*290ms Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 0 Turbo2 Turbo Enable Disable Enable Soft Timer 3 (MSB) Soft Timer 2 Soft Timer 1 Soft Timer 0 (LSB) Soft alarm timer RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 1 Bit Output(s) Affected Description / Function 0 1 Type Power On 7 6 5 4 3 2 1 Watch Dog Enable Watch Dog Enable Disable Enable RW Soft Alarm Enable Soft RESET# Hard Alarm Enable Hard RESET# Hard Alarm FS Relatch Enable TCN8 (MSB) Soft Alarm Enable Soft Reset Enable Hard Alarm Enable Hard Reset Enable Relatch FS[C, B, A] at Hard Alarm Disable Disable Disable Disable Disable Enable Soft Reset Enable Enable Hard Reset Enable Relatch RW RW RW RW RW 0 0 0 0 0 0 0 RW 0 BYTE 26 BYTE 27 0 10 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE BYTE 28 Bit Output(s) Affected 7 6 5 4 3 2 1 0 TCN7 TCN6 TCN5 TCN4 TCN3 TCN2 TCN1 TCN0 (LSB) Description / Function 0 1 Turbo CPU PLL N setting CPU Frequency = N * Resolution (see Resolution table) Type Power On RW RW RW RW RW RW RW RW 1 0 0 1 0 1 1 0 Type Power On BYTE 29 Bit Output(s) Affected 7 6 5 4 3 2 1 0 TPN8 (MSB) TPN7 TPN6 TPN5 TPN4 TPN3 TPN2 TPN1 Description / Function 0 1 0 1 0 0 1 0 1 1 Turbo SRC PLL N setting SRC Frequency = N * Resolution Resolution = 0.666667 BYTE 30 Bit Output(s) Affected 7 6 5 TPN0 (LSB) TCN28 Description / Function 0 Test Mode entry control Normal operation Only valid when Byte6 bit5 is high PCI4/Turbo Mode select On chip test mode enable Hi-Z Turbo 1 Disable normal 1 4 3 2 1 PCI4/Turbo 1 Turbo 1 Test_scl 0 Test_hiz CLK outputs enable normal Test mode, controlled by byte 30 bit 4 REF/N mode PCI4 Enable SCLK=1, CLK outputs=1 SCLK=0, CLK outputs=0 CLK outputs=Tristate Bit Output(s) Affected Description / Function 0 1 7 6 5 4 3 2 1 0 TCN27 TCN26 TCN25 TCN24 TCN23 TCN22 TCN21 TCN20 Type Power On 0 0 0 RW RW RW 0 0 0 0 RW 0 BYTE 31 Type Power On 1 0 0 1 0 1 1 0 Turbo CPU PLL N setting 11 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PLL FREQUENCY PROGRAMMING PROCEDURES The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may enable either one or both of the alarms. User presets the CPU PLL Mode and N, and SRC PLL N value: 1. Set CPU PLL Mode, CB1 and CB2, byte17 2. Set CPU PLL N, CN1 and CN2, byte18 and byte19 3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte21, 22 User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively: 4. Select Soft Alarm frequency, byte23 5. Select Hard Alarm frequency, byte24 User sets the Timer and enables the WD circuit for frequency switch: 6. Set Hard Alarm Timer, byte25 7. Set Soft Alarm Timer, byte 26 8. Enable Soft and Hard Alarm and RESET# bit (If user needs RESET# signal to reset the system), byte27 9. Enable Watch Dog (WDE), byte27 • • • Soft Reset# and Hard Reset# are valid only if Soft Alarm and Hard Alarm are enabled respectively. WDE Disable resets WDSRB and WDHRB. PCI CLK is selectable from SRC PLL or SATA PLL, byte5 bit6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte5 bit[5:4]. WD SOFT AND HARD ALARM/TIME OUT OPERATION WD HARD ALARM TIMER [7:0] WD SOFT ALARM TIMER [3:0] WDE Trigger Watch Dog Circuit If Soft Alarm Enabled (byte 27): Set WDSRB (byte 6) Load CPU N and Mode selections into PCU PLL Load SRC N selection into SRC PLL If Soft Reset# Enabled (byte 27): Issue RESET# 12 If Hard Alarm Enabled (byte 27): Set WDHRB (byte 6) Load CPU N and Band selections into PCU PLL Load SRC N selections into SRC PLL If Hard Reset# Enabled (byte 27): Issue RESET# If Hard Alarm Relatch Enabled: Latch FSC, B, A IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5% Symbol Parameter Test Conditions Min. Typ. Max. Unit VIH Input HIGH Voltage 3.3V ± 5% 2 — VDD + 0.3 V VIL Input LOW Voltage 3.3V ± 5% VSS - 0.3 — 0.8 V VIH_FS FS Input HIGH Voltage For FSA.B.C and Test_Mode 0.7 — VDD + 0.3 V VIL_FS FS Input LOW Voltage For FSA.B.C and Test_Mode VSS - 0.3 — 0.35 V Input LeakageCurrent 0< VIN < VDD, no internal pull-up or pull-down –5 — +5 mA IDD3.3OP Operating Supply Current Full active, CL = full load — — 400 mA IDD3.3PD Powerdown Current mA IIL FI Input Frequency(1) LPIN Pin Inductance(2) CIN COUT Input Capacitance(2) CINX TSTAB All differential pairs driven — — 70 All differential pairs tri-stated — — 12 VDD = 3.3V — 14.31818 — MHz — — 7 nH Logic inputs — — 5 Output pin capacitance — — 6 pF X1 and X2 pins — — 5 Clock Stabilization(2,3) From VDD power-up or de-assertion of PD# to first clock — — 1.8 ms Modulation Frequency(2) Triangular modulation 30 — 33 KHz TDRIVE_SRC(2) SRC output enable after PCI_Stop# de-assertion — — 15 ns TDRIVE_PD#(2) CPU output enable after PD# de-assertion — — 300 us TFALL_PD#(2) Fall time of PD# — — 5 ns TRISE_PD#(3) Rise time of PD# — — 5 ns TDRIVE_CPU_Stop#(2) CPU output enable after CPU_Stop# de-assertion — — 10 us TFALL_CPU_Stop#(2) Fall time of PD# — — 5 ns TRISE_CPU_Stop#(3) Rise time of PD# — — 5 ns NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements. 13 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol Parameter Min. Typ. Max. Unit VO = VX 3000 — — Ω Output HIGH Voltage IOH = -1mA 2.4 — — V VOL3 Output LOW Voltage IOL = 1mA — — 0.4 V VHIGH Voltage HIGH(2) Statistical measurement on single-ended signal using 660 — 850 mV VLOW Voltage LOW(2) oscilloscope math function –150 — 150 VOVS Max Voltage(2) Measurement on single-ended signal using absolute value — — 1150 VUDS Min Voltage(2) –300 — — VCROSS(ABS) Crossing Voltage (abs)(2) 250 — 550 mV d - VCROSS Crossing Voltage (var)(2) Variation of crossing over all edges — — 140 mV Long Accuracy(2,3) See TPERIOD Min. - Max. values –300 — 300 ppm 400MHz nominal/spread 2.4993 — 2.5008 333.33MHz nominal/spread 2.9991 — 3.0009 266.66MHz nominal/spread 3.7489 — 3.7511 200MHz nominal/spread 4.9985 — 5.0015 166.66MHz nominal/spread 5.9982 — 6.0018 133.33MHz nominal/spread 7.4978 — 7.5023 100MHz nominal/spread 9.997 — 10.003 96MHz nominal 10.4135 — 10.4198 400MHz nominal/spread 2.4143 — — 333.33MHz nominal/spread 2.9141 — — 266.66MHz nominal/spread 3.6639 — — 200MHz nominal/spread 166.66MHz nominal/spread 4.9135 5.9132 — — — — 133.33MHz nominal/spread 7.4128 — — 100MHz nominal/spread 9.912 — — 10.1635 — — Current Source Output Impedance(2) VOH3 ZO ppm TPERIOD TABSMIN Average Period(3) Absolute Min Period(2,3) Test Conditions 96MHz nominal mV ns ns tR Rise Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps tF Fall Time(2) VOL = 0.175V, VOH = 0.525V 175 — 700 ps d-tR Rise Time Variation(2) — — 125 ps d-tF Fall Time Variation(2) — — 125 ps dT3 Duty Cycle(2) Measurement from differential waveform 45 — 55 % tSK3 Skew(2) VT = 50% — — 100 ps Measurement from differential waveform — — 85 ps tJCYC-CYC Jitter, Cycle to Cycle(2) NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 14 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF Symbol ppm TPERIOD Parameter Test Conditions Long Accuracy(1,2) Min. Typ. Max. Unit See Tperiod Min. - Max. values Clock Period(2) — — 300 ppm 33.33MHz output nominal 29.991 — 30.009 ns 33.33MHz output spread 29.991 — 30.1598 VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 4 V/ns Edge Rate(1) Falling edge rate 1 — 4 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 0.5 — 2 ns IOL Output LOW Current Cycle(1) mA dT1 Duty VT = 1.5V 45 — 55 % tSK1 Skew(1) VT = 1.5V — — 500 ps tJCYC-CYC Jitter(1) VT = 1.5V — — 250 ps Min. Typ. Max. Unit — — 300 ppm 20.8257 — 20.834 ns NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. ELECTRICAL CHARACTERISTICS, 48MHZ, USB Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1,2) See Tperiod Min. - Max. values Clock Period(2) 48MHz output nominal VOH Output HIGH Voltage IOH = -1mA 2.4 — — V VOL Output LOW Voltage IOL = 1mA — — 0.55 V IOH Output HIGH Current VOH at Min. = 1V -33 — — mA VOH at Max. = 3.135V — — -33 VOL at Min. = 1.95V 30 — — ppm TPERIOD IOL Output LOW Current mA VOL at Max. = 0.4V — — 38 Edge Rate(1) Rising edge rate 1 — 2 V/ns Edge Rate(1) Falling edge rate 1 — 2 V/ns tR1 Rise Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 15 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE ELECTRICAL CHARACTERISTICS - REF-14.318MHZ Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF Symbol Parameter Test Conditions Long Accuracy(1) See Tperiod Min. - Max. values Clock Period 14.318MHz output nominal VOH Output HIGH Voltage(1) VOL Output LOW Voltage(1) IOH Output HIGH Current(1) IOL Output LOW Current(1) tR1 Rise Time(1) tF1 Fall Time(1) VOL = 0.4V, VOH = 2.4V 1 — 2 ns tSK1 Skew(1) VT = 1.5V — — 500 ps dT1 Duty Cycle(1) VT = 1.5V 45 — 55 % Jitter(1) VT = 1.5V — — 1000 ps ppm TPERIOD tJCYC-CYC Min. Typ. Max. Unit — — 300 ppm 69.827 — 69.855 ns IOH = -1mA 2.4 — — V IOL = 1mA — — 0.4 V VOH at Min. = 1V, VOH at Max. = 3.135V -29 — -23 mA VOL at Min. = 1.95V, VOL at Max. = 0.4V 27 — 29 mA VOL = 0.4V, VOH = 2.4V 1 — 2 ns NOTE: 1. This parameter is guaranteed by design, but not 100% production tested. 16 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD#, POWER DOWN PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PWRDWN# CPU CPU# SRC SRC# PCIF/PCI USB 1 Normal 0 IREF * 2 or float DOT96 DOT96# REF Normal Normal Normal 33MHz Float IREF * 2 or float Float Low 48MHz Normal Normal 14.318MHz Low IREF * 2 or float Float Low PD# ASSERTION PD# should be sampled low by two consecutive CPU# rising edges before stopping clocks. All single-ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to ‘tri-state’, the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to ‘0’ the true clock will be driven high at 2 x IREF and the complementary clock will be tristated. If the control register is programmed to ‘1’ both clocks will be tristated. PWRDWN# CPU 133MHz CPU# 133MHz SRC 100MHz SRC# 100MHz USB 48MHz PCI 33MHz REF 14.31818 17 IDTCV115-2 PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PD# DE-ASSERTION The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD# deassertion. tSTABLE