IDTCV128
1-TO-12 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
1-TO-12 DIFFERENTIAL
CLOCK BUFFER
IDTCV128
DESCRIPTION:
FEATURES:
The CV128 differential buffer complies with Intel DB1200G rev. 0.5, and is
designed to work in conjunction with the main clock of CK409, CK410/CK410M
and CK410B etc., PLL is off in bypass mode and no clock detect.
• Compliant with Intel DB1200G rev. 0.5
• DIF Clock Support
− 12differential clock output pairs @ 0.7 V
− 50 ps skew performance (same gear)
• OE pin Control of All Outputs
• 3.3 V Operation
• Gear Ratio supporting generation of clocks at a different
frequency ratioed from the input.
• Split outputs supporting options of 2 outputs @1:1 and
remaining 10 pairs at an alternate gear
• Pin level OE control of individual outputs
• Multiple output frequency options up to 400Mhz as a gear ratio
of input clocks of 100-400Mhz
• Output is HCSL compatible
• SMBus Programmable configurations
• PLL Bypass Configurable
• SMBus address configurable to allow multiple buffer control in
a single control network
• Programmable Bandwidth
• Glitchfree transition between frequency states
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
OE_10_11#
DIF_0
DIF_0#
Output
Control
OE[9:0]#
DIF_1
DIF_1#
DIF_2
VTT_PWRGD#/PWRDWN
DIF_2#
DIF_3
DIF_3#
SCL
SM Bus
Controller
SDA
DIF_4
Output
Buffer
DIF_4#
DIF_5
DIF_5#
DIF_6
DIF_6#
SA_2/PLL/BYPASS#
DIF_7
CLK_IN
DIF_8
DIF_7#
DIF_8#
CLK_IN#
DIF_9
DIF_9#
HIGH_BW#
DIF_10
PLL
DIF_10#
DIF_11
DIF_11#
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JUNE 29, 2007
1
© 2005 Integrated Device Technology, Inc.
DSC-6743/A
IDTCV128
1-TO-12 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
HIGH_BW#
1
56
VDDA
CLK_IN
2
55
VSSA
VDD
3.3V Logic Input Supply Voltage GND - 0.5
CLK_IN#
3
54
IREF
TSTG
Storage Temperature
SA_0
4
53
OE_10_11#
TAMBIENT
Ambient Operating Temperature
OE_0#
5
52
DIF_11
TCASE
Case Temperature
DIF_0
6
51
DIF_11#
ESD Prot
Input ESD Protection
DIF_0#
7
50
OE_1#
8
49
DIF_1
9
48
VDD
VSS
DIF_10
DIF_1#
10
47
DIF_10#
VDD
11
46
FS_A
VSS
12
45
VTT_PWRGD#/PWRDWN
DIF_2
13
44
OE_9#
DIF_2#
14
43
DIF_9
OE_2#
15
42
DIF_3
16
41
DIF_9#
OE_8#
DIF_3#
17
40
DIF_8
OE_3#
18
39
DIF_8#
DIF_4
19
38
VDD
DIF_4#
20
37
VSS
OE_4#
21
36
DIF_7
VDD
22
35
DIF_7#
VSS
23
34
OE_7#
DIF_5
24
33
DIF_6
DIF_5#
25
32
DIF_6#
OE_5#
26
31
OE_6#
SA_1
27
30
SA_2/PLL/BYPASS#
SDA
28
29
SCL
3.3V Core Supply Voltage
Min.
VDDA
–65
0
Max.
Unit
4.6
V
4.6
V
+150
°C
+70
°C
+115
°C
2000
V
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OE FUNCTIONALITY
OE# - Pin
0
0
1
1
SSOP/ TSSOP
TOP VIEW
2
OE# - SMBus bit
1
0
1
0
DIF
Normal
Tristate
Tristate
Tristate
DIFF]#
Normal
Tristate
Tristate
Tristate
IDTCV128
1-TO-12 DIFFERENTIAL CLOCK BUFFER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
Type
Pin #
Description
CLK_IN, CLK_IN#
IN
2, 3
DIF_[9:0] & DIF_[9:0]#
OUT
6, 7, 9, 10, 13, 14, 16,
17, 19, 20, 24, 25, 32, 33,
35, 36, 39, 40, 42, 43
DIF & DIF# [11:10]
OUT
47, 48, 51, 52
0.7 V Differential clock outputs, which can be configured to be 1:1 instead of geared. Default
is geared same as 0-9 outputs.
OE_[9:0]#
IN
5, 8, 15, 18, 21, 26,
31, 34, 41, 44
3.3 V LVTTL active LOW input for enabling corresponding differential output clock. Clocks
also can be disabled via SMBus registers
OE _10_11#
IN
53
3.3 V LVTTL active low input for enabling both DIF10 and 11differential output clocks. Clocks
also can be disabled via SMBus registers individually.
HIGH_BW#
IN
1
3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW.
SCL
IN
29
SMBus slave clock input
SDA
I/O, OC
28
Open collector SMBus data
(1)
0.7v Differential input
0.7 V Differential clock outputs, geared to a ratio of the input clock
IREF
IN
54
SA_[0:1]
IN
4, 27
IN
30
3.3 V LVTTL input for PLLbypass and SMBus address. 0=PLLbypass mode; 1=PLL mode
SA_2/PLL_BYPASS#
A precision resistor is attached to this pin to set the differential output current
3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address.
FS_A
IN
46
3.3V LVTTL input to establish a HIGH (>200Mhz) or LOW frequency(
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