ISL43L420IR

DATASHEET ISL43L420 Ultra Low ON-Resistance, +1.1V to +4.5V Single Supply, Quad SPDT (Dual DPDT) Analog Switch FN6098 Rev 1.00 February 18, 2005 The Intersil ISL43L420 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.1V to +4.5V supply. Targeted applications include battery-powered equipment that benefit from low RON (0.24 and fast switching speeds (tON = 8ns, tOFF = 5ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. Features Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to “mux-in” additional functionality while reducing ASIC design risk. The ISL43L420 is offered in a small form factor package, alleviating board space limitations. • RON Matching between Channels . . . . . . . . . . . . . . . . .0.05 The ISL43L420 is a committed Quad SPDT that consists of four normally open (NO) and four normally (NC) switches. This configuration can also be used as a diff dual 2-to-1 multiplexer/demultiplexer or a dual 2-to1 multiplexer/demultiplexer. The ISL43L420 is pin compatible with the STG3699. TABLE 1. FEATURES AT A GLANCE ISL43L420 Number of Switches 4 SW Quad SPDT (Dual DPDT) 4.3V RON 0.24 4.3V tON/tOFF 8ns/5ns 3.0V RON 0.26 3.0V tON/tOFF 10ns/7ns 1.8V RON 0.45 1.8V tON/tOFF 18ns/10ns Packages 16 Ld 3x3 QFN • Drop in Replacement for the STG3699 • ON Resistance (RON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.24 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 • RON Flatness Across Signal Range . . . . . . . . . . . . . . .0.05 • Single Supply Operation. . . . . . . . . . . . . . . . . +1.1V to +4.5V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . 9kV HBM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>4kV MM COMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V MM NOX, NCX, INX, V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1000V Thermal Resistance (Typical, Note 2) JA (°C/W) 16 Ld 3x3 QFN Package . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range ISL43L420IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 4.3V Supply PARAMETER Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 3, 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS Full 0 - V+ V 25 - 0.25 0.45  Full - - 0.6  25 - 0.05 0.08  Full - - 0.09  25 - 0.05 0.15  Full - - 0.15  25 -50 - 50 nA Full -150 - 150 nA 25 -50 - 50 nA Full -150 - 150 nA 25 - 8 13 ns Full - - 18 ns 25 - 5 10 ns Full - - 15 ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) RON Matching Between Channels, RON V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at max RON, (Note 8) RON Flatness, RFLAT(ON) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 3.9V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 7) V+ = 3.9V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 7) Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 7) Full 2 3 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0(See Figure 2) 25 - -120 - pC OFF Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) 25 - 68 - dB Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) 25 - -98 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 25 - 0.003 - % FN6098 Rev 1.00 February 18, 2005 Page 3 of 13 ISL43L420 Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 3, 5), Unless Otherwise Specified (Continued) TEMP (°C) (NOTE 4) MIN TYP NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 106 - pF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 212 - pF Full 1.1 - 4.5 V 25 - - 0.06 A Full - - 1.4 A Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.6 - - V Full -0.5 - 0.5 A PARAMETER COM ON Capacitance, CCOM(ON) TEST CONDITIONS (NOTE 4) MAX UNITS POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ =1.1V to 4.5V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+, (Note 7) NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 7. Guaranteed but not tested. 8. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max RON value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 3, 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS Full 0 - V+ V 25 - 0.3 0.45  Full - - 0.6  25 - 0.05 0.08  Full - - 0.09  25 - 0.06 0.15  Full - - 0.15  25 - 1.2 - nA Full - 13 - nA 25 - 1 - nA Full - 35 - nA 25 - 11 17 ns Full - - 20 ns 25 - 8 14 ns Full - - 17 ns Full 2 3 - ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) RON Matching Between Channels, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max RON, (Note 8) RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (Note 6) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD FN6098 Rev 1.00 February 18, 2005 V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 7) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 7) V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 7) Page 4 of 13 ISL43L420 Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 3, 5), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (°C) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - -82 - pC OFF Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) 25 - 68 - dB Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) 25 - -98 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 25 - 0.003 - % NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 106 - pF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 212 - pF 25 - 23 - nA Full - 720 - nA Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.4 - - V Full -0.5 - 0.5 A COM ON Capacitance, CCOM(ON) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+, (Note 7) Electrical Specifications - 1.8V Supply PARAMETER Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Notes 3, 5), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 4) MIN TYP (NOTE 4) MAX UNITS Full 0 - V+ V 25 - 0.45 0.8  Full - - 0.85  25 - 18 23 ns Full - - 25 ns 25 - 10 15 ns Full - - 18 ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 7) V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 7) Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 7) Full 2 5 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - -44 - pC OFF Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) 25 - 68 - dB Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) 25 - -98 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 106 - pF COM ON Capacitance, CCOM(ON) 25 - 212 - pF Input Voltage Low, VINL Full - - 0.4 V Input Voltage High, VINH Full 1.0 - - V Full -0.5 - 0.5 A f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL FN6098 Rev 1.00 February 18, 2005 V+ = 2.0V, VIN = 0V or V+, (Note 7) Page 5 of 13 ISL43L420 Electrical Specifications - 1.1V Supply PARAMETER Test Conditions: V+ = +1.1V, GND = 0V, VINH = 1.0V, VINL = 0.3V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 4) MIN Full (NOTE 4) MAX UNITS TYP ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG 0 - V+ V V+ = 1.1V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) 25 - 2.5 -  Full - 3.1 -  V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 7) 25 - 30 - ns Full - 35 - ns V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 1, Note 7) 25 - 15 - ns Full - 20 - ns Full - 4 - ns Input Voltage Low, VINL Full - 0.3 - V Input Voltage High, VINH Full - 0.6 - V Full - 0.5 - A 25 - - 0.02 A Full - - 0.6 A ON Resistance, RON DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD V+ = 1.1V, VNO or VNC = 1.0V, RL = 50, CL = 35pF, (See Figure 3, Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 1.1V, VIN = 0V or V+, (Note 7) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 1.1V, VIN = 0V or V+ Test Circuits and Waveforms V+ V+ LOGIC INPUT tr < 5ns tf < 5ns 50% 0V tOFF SWITCH INPUT VNO SWITCH INPUT VOUT NO or NC COM IN VOUT 90% SWITCH OUTPUT C 90% LOGIC INPUT RL 50 GND CL 35pF 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R  ON  FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES FN6098 Rev 1.00 February 18, 2005 Page 6 of 13 ISL43L420 Test Circuits and Waveforms (Continued) V+ SWITCH OUTPUT VOUT RG VOUT V+ ON ON LOGIC INPUT OFF C VG VOUT COM NO or NC GND IN 0V CL LOGIC INPUT Q = VOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ V+ NO VNX LOGIC INPUT C VOUT COM NC 0V RL 50 IN SWITCH OUTPUT VOUT 90% 0V tD CL 35pF GND LOGIC INPUT CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME V+ V+ C C RON = V1/100mA SIGNAL GENERATOR NO or NC NO or NC VNX IN 0V or V+ IN V1 0V or V+ COM COM ANALYZER 1mA GND GND RL FIGURE 4. OFF ISOLATION TEST CIRCUIT FN6098 Rev 1.00 February 18, 2005 FIGURE 5. RON TEST CIRCUIT Page 7 of 13 ISL43L420 Test Circuits and Waveforms (Continued) V+ C V+ C SIGNAL GENERATOR NO or NC COM 50 NO or NC IN1 IN 0V or V+ COM ANALYZER 0V or V+ IMPEDANCE ANALYZER RL NC or NO COM N.C. GND GND FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT Detailed Description The ISL43L420 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.1V to 4.5V supply with low onresistance (0.24) and high speed operation (tON = 8ns, tOFF = 5ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.1V), low power consumption (2.7W max), low leakage currents (150nA max), and the tiny QFN package. The ultra low on-resistance and RON flatness provide very low insertion loss and distortion to applications that require signal reproduction. approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (See Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (See Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this FN6098 Rev 1.00 February 18, 2005 GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL43L420 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L420 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.1V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. Page 8 of 13 ISL43L420 This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (See Figure 16). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50 systems, the signal response is reasonably flat even past 30MHz with a -3dB bandwidth of 104MHz (See Figure 19). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 20 Typical Performance Curves details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 68dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. TA = 25°C, Unless Otherwise Specified 0.31 3 ICOM = 100mA 0.3 ICOM = 100mA 0.29 2.5 V+ = 2.7V 0.28 0.27 2 V+ = 3V RON () RON () 0.26 0.25 0.24 V+ = 3.6V V+ = 1.1V 1.5 0.23 1 0.22 V+ = 1.5V 0.21 V+ = 4.3V 0.2 0.5 0.19 V+ = 1.8V 0 0.18 0 1 2 3 4 VCOM (V) FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE FN6098 Rev 1.00 February 18, 2005 5 0 0.5 V+ = 1.65V 1 VCOM (V) 1.5 FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE Page 9 of 13 2 ISL43L420 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 0.28 0.35 V+ = 4.3V ICOM = 100mA 0.26 0.3 0.24 85°C 85°C 0.22 RON () RON () V+ = 2.7V ICOM = 100mA 0.2 0.25 25°C 25°C 0.18 0.2 -40°C 0.16 -40°C 0.14 0 1 2 3 4 0.15 5 0 0.5 1 1.5 VCOM (V) VCOM (V) FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 2 2.5 FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE 3.5 0.5 V+ = 1.8V ICOM = 100mA 0.45 3 V+ = 1.1V ICOM = 100mA -40°C 3 85°C 25°C 2.5 RON () RON () 0.4 0.35 0.3 2 1.5 85°C 1 25°C -40°C 0.25 0.2 0.5 0 0 0.5 1 1.5 2 0 0.2 0.4 0.6 VCOM (V) 0.8 1 1.2 VCOM (V) FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE 1.5 50 1.4 1.3 1.2 VINH AND VINL (V) 0 Q (pC) V+ = 1.8V V+ = 3V -50 -100 1.1 VINH 1 0.9 0.8 VINL 0.7 0.6 0.5 0.4 -150 0 0.5 1 1.5 2 2.5 VCOM (V) FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE FN6098 Rev 1.00 February 18, 2005 3 0.3 1 1.5 2 2.5 3 3.5 4 4.5 V+ (V) FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE Page 10 of 13 ISL43L420 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 20 50 40 30 85°C -40°C 10 0 25°C 1 1.5 5 2 2.5 3 V+ (V) 3.5 4 0 4.5 GAIN 0 20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 100 10 100 FREQUENCY (MHz) CROSSTALK (dB) -20 PHASE (DEGREES) NORMALIZED GAIN (dB) -10 PHASE 1.5 1 2.5 3 V+ (V) 3.5 4 4.5 -20 20 -30 30 -40 40 -50 50 60 -60 ISOLATION 70 -70 80 -80 CROSSTALK -90 90 100 -100 -110 1K 600 10 V+ = 3V FIGURE 19. FREQUENCY RESPONSE 10K 100K 1M 10M FREQUENCY (Hz) 110 100M 500M FIGURE 20. CROSSTALK AND OFF ISOLATION 100 50 V+ = 4.5V V+ = 4.5V VCOM = 0.3V 50 0 0 iOFF (nA) iON (nA) 2 FIGURE 18. TURN-OFF TIME vs SUPPLY VOLTAGE V+ = 3V 1 25°C -40°C FIGURE 17. TURN-ON TIME vs SUPPLY VOLTAGE 0 85°C 10 OFF ISOLATION (dB) 20 tOFF (ns) tON (ns) 15 25°C -50 25°C -50 85°C -100 85°C -100 0 1 2 3 VCOM/NX (V) 4 FIGURE 21. ON LEAKAGE vs SWITCH VOLTAGE FN6098 Rev 1.00 February 18, 2005 5 -150 0 1 2 3 4 VNX (V) FIGURE 22. OFF LEAKAGE vs SWITCH VOLTAGE Page 11 of 13 5 ISL43L420 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: TBD 228 PROCESS: Si Gate CMOS © Copyright Intersil Americas LLC 2004-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6098 Rev 1.00 February 18, 2005 Page 12 of 13 ISL43L420 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C A D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E 9 TOP VIEW A2 A A3 SIDE VIEW 4X P 9 - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.18 - D1 2.75 BSC 9 1.35 1.65 7, 8, 10 - 2.75 BSC 1.35 1.50 9 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 16 2 Nd 4 3 - 0.60 NX k  - - 12 4 3 9 9 Rev. 1 6/04 NOTES: 1 (DATUM A) 2 3 6 INDEX AREA NX L N e 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (Ne-1)Xe REF. E2 E2/2 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. SECTION "C-C" C L 9. Features and dimensions A2, A3, D1, E1, P &  are present when Anvil singulation method is used and not present for saw singulation. C L L e FN6098 Rev 1.00 February 18, 2005 1.50 3.00 BSC - 10 5, 8 3.00 BSC P D2 2 N FOR ODD TERMINAL/SIDE 0.30 D Ne 7 L1 0.23 9 8 4X P C C 1.00 - 0.10 M C A B D2 (DATUM B) A1 5 NX b 8 0.90 - e 0.08 C SEATING PLANE 0.80 E1 / / 0.10 C C NOTES A E2 0 4X B MAX A1 E 0.15 C B 0.15 C A NOMINAL D2 2X 2X MIN b E/2 E1 SYMBOL L1 10 L 10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension. e TERMINAL TIP FOR EVEN TERMINAL/SIDE Page 13 of 13