3.3V, 1:6, LVCMOS PLL Clock Generator
MPC9330
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
DATA SHEET
The MPC9330 is a 3.3 V compatible, 1:6 PLL based clock generator targeted for high
performance low-skew clock distribution in mid-range to high-performance telecomm,
networking and computing applications. With output frequencies up to 120 MHz and output
skews less than 150 ps, the device meets the needs of the most demanding clock applications.
The MPC9330 is specified for the temperature range of 0°C to +70°C.
MPC9330
Features
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1:6 PLL Based Low-Voltage Clock Generator
3.3 V Power Supply
Generates Clock Signals Up to 120 MHz
Maximum Output Skew of 150 ps
On-Chip Crystal Oscillator Clock Reference
Alternative LVCMOS PLL Reference Clock Input
Internal and External PLL Feedback
PLL Multiplies the Reference Clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x,
x/2, x/3, or x/4
Supports Zero-Delay Operation in External Feedback Mode
Synchronous Output Clock Stop in Logic Low Eliminates Output Runt Pulses
Power_Down Feature Reduces Output Clock Frequency
Drives Up to 12 Clock Lines
32-Lead LQFP Packaging
32-Lead Pb-Free Package
Ambient Temperature Range 0C to +70C
Internal Power-Up Reset
Pin and Function Compatible to the MPC930
For functional replacement use 8T49N285A
3.3 V 1:6 LVCMOS
PLL CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9330
requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL
feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency.
Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers
(divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the MPC9330 is running at either 4x, 8x, 12x, 16x, or 24x of the reference clock
frequency. In internal feedback configuration (divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the
QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA,
FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The PLL_EN control
selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the
output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected,
deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs
and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output clock stop control allows the outputs
to start and stop synchronously in the logic low state, without the potential generation of runt pulses.
The MPC9330 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals
while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated
transmission lines, each of the MPC9330 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is
packaged in a 7x7 mm2 32-lead LQFP package.
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
VCC
25k
XTAL_IN
XTAL_OUT
XTAL
VCO
2
0
4
1
0
1
PLL
QA0
2
0
4
1
VCC
QA1
Bank B
QB0
1
25k
CLK
Stop
6
25k
FB_IN
FB_SEL
Ref
1
CCLK
REF_SEL
Bank A
0
0
FB
0
1
CLK
Stop
QB1
16
25k
Bank C
VCC
QC0
25k
PWR_DN
0
VCC
1
25k
CLK
Stop
QC1
PLL_EN
FSELA
FSELB
FSELC
3 x 25k
VCC
Power_On Reset
3 x 25k
3
CLK_STOP0
CLK_STOP1
OE/MR
GND
QB0
QB1
VCC
FB_SEL
REF_SEL
PLL_EN
NC
Figure 1. MPC9330 Logic Diagram
24
23
22
21
20
19
18
17
GND
25
16
GND
QA1
26
15
QC1
QA0
27
14
QC0
VCC
28
13
VCC
FSELA
29
12
FB_IN
FSELB
30
11
CLK_STOP1
FSELC
31
10
CLK_STOP0
NC
32
MPC9330
2
3
4
5
6
7
8
NC
VCC_PLL
PWR_DN
CCLK
OE/MR
XTAL_IN
XTAL_OUT
GND
9
1
NC
It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see Applications Information section for details.
Figure 2. MPC9330 32-Lead Package Pinout (Top View)
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
XTAL_IN, XTAL_OUT
Input
Analog
Crystal oscillator interface
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
FB_SEL
Input
LVCMOS
Feedback select
REF_SEL
Input
LVCMOS
Reference clock select
PWR_DN
Input
LVCMOS
Output frequency and power down select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
CLK_STOP0-1
Input
LVCMOS
Clock output enable/disable
OE/MR
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0-1, QB0-1, QC0-1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC
filter for the analog power supply pin VCC_PLL. Please see Applications Information section for
details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation.
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
The crystal oscillator output is the PLL reference clock
CCLK is the PLL reference clock
FB_SEL
0
Internal PLL feedback of 16. fVCO = 16 * fref
External feedback. Zero-delay operation
enabled for CCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9330 is fully static
and no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
Normal operation mode with PLL enabled.
PWR_DN
1
VCO 2 (High output frequency range)
VCO 4 (Low output frequency range)
FSELA
0
Output divider 2
Output divider 4
FSELB
0
Output divider 2
Output divider 4
FSELC
0
Output divider 4
Output divider 6
CLK_STOP[0:1]
11
See Table 3
OE/MR
1
Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the
PLL feedback loop is open. The VCO is tied to its lowest
frequency. The MPC9330 requires reset after any loss of PLL
lock. Loss of PLL lock may occur when the external feedback
path is interrupted. The length of the reset pulse should be
greater than one reference clock cycle (CCLK). Reset does not
affect PLL lock in internal feedback configuration.
Outputs enabled (active)
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 8 through Figure 10 for supported frequency ranges and output to input frequency ratios.
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table(1)
CLK_STOP0
CLK_STOP1
QA[0:1]
QB[0:1]
QC[0:1]
0
0
Active
Stopped in logic L state
Stopped in logic L state
0
1
Active
Stopped in logic L state
Active
1
0
Stopped in logic L state
Stopped in logic L state
Active
1
1
Active
Active
Active
1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1].
Table 4. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC 2
Condition
VTT
Output Termination Voltage
V
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch-Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 5. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.9
V
VIN
DC Input Voltage
–0.3
VCC+0.3
V
DC Output Voltage
–0.3
VCC+0.3
V
DC Input Current
20
mA
DC Output Current
50
mA
125
°C
VOUT
IIN
IOUT
TS
Storage Temperature
–65
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 6. DC Characteristics (VCC = 3.3 V 5%, TA = 0°C to 70°C)
Symbol
Characteristics
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
ICC_PLL
ICCQ
Min
Typ
2.0
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
V
IOH = -24 mA(1)
V
V
IOL= 24 mA
IOL= 12 mA
2.4
0.55
0.30
14 – 17
Input Current(2)
Condition
100
A
VIN = VCC or GND
Maximum PLL Supply Current
5.0
10
mA
VCC_PLL Pin
Maximum Quiescent Supply Current
5.0
10
mA
All VCC Pins
1. The MPC9330 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
2. Inputs have pull-down or pull-up resistors affecting the input current.
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 7. AC Characteristics (VCC = 3.3 V 5%, TA = 0°C to 70°C)(1)
Symbol
fref
Characteristics
Input Reference Frequency(2)
PLL mode, external feedback
PLL mode, internal feedback
Min
4 feedback(3)
8 feedback
12 feedback
16 feedback
24 feedback
16 feedback)
Typ
Max
Unit
50
25
16.67
12.5
8.33
12.5
120
60
40
30
20
30
TBD
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Input Reference Frequency in PLL bypass mode(4)
fVCO
VCO Lock Frequency Range(5)
200
480
MHz
fXTAL
Crystal Interface Frequency Range(6)
10
25
MHz
fMAX
Output Frequency
50
25
16.67
12.5
8.33
120
60
40
30
20
MHz
MHz
MHz
MHz
MHz
25
2
75
%
ns
1.0
ns
+1.2
+400
+70
°
ps
ps
50
150
ps
ps
55
%
1.0
ns
frefDC
tPW, MIN
4 output
8 output
12 output
16 output
24 output
Reference Input Duty Cycle
Minimum Input Reference Pulse Width
tr, tf
CCLK Input Rise/Fall Time
t()
Propagation Delay (SPO)(7) for the
tsk(o)
Output-to-Output Skew(8)
- entire fref range
- fref = 8.33 MHz
- fref = 50.0 MHz
-1.2
-400
-70
(within output bank)
(any output)
DC
Output Duty Cycle
45
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
50
300
ps
tJIT(PER)
Period Jitter
35
250
ps
10
70
ps
tJIT()
BW
tLOCK
I/O Phase Jitter
PLL closed loop bandwidth(9)
PLL mode, external feedback
RMS (1)
4 feedback
8 feedback
12 feedback
16 feedback
24 feedback
Maximum PLL Lock Time
50
0.8-5.0
0.5-2.0
0.3-1.0
0.25-0.6
0.2-0.5
Condition
PLL locked
PLL locked
0.8 to 2.0 V
0.55 to 2.4 V
MHz
MHz
MHz
MHz
MHz
10
ms
1. AC characteristics apply for parallel output termination of 50 to VTT.
2. PLL mode requires PLL_EN = 0 to enable the PLL.
3. 4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one 2 output to FB_IN. See Table 3 to Table 5 for
other feedback configurations.
4. In bypass mode, the MPC9330 divides the input reference clock.
5. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
6. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
7. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked). tsk(o) [ps] = tsk(o) [°] B(fref 360°)
8. Skew data applicable for equally loaded outputs only.
9. –3 dB point of PLL transfer characteristics.
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Output Power Down (PWR_DN) Timing Diagram
VCO2
VCO4
PWR_DWN
QAx (2)
QBx (4)
QCx (6)
Output Clock Stop (CLK_STOP) Timing Diagram
QAx (2)
QBx (4)
QCx (6)
CLK_STOP0
CLK_STOP1
QAx (2)
QBx (4)
QCx (6)
Programming the MPC9330
The MPC9330 supports output clock frequencies from 8.33 to
120 MHz. Different feedback and output divider configurations can
be used to achieve the desired input to output frequency
relationship. The feedback frequency and divider should be used to
situate the VCO in the frequency lock range between 200 and 480
MPC9330 REVISION 8 3/11/16
MHz for stable and optimal operation. The FSELA, FSELB, FSELC
and PWR_DN pins select the desired output clock frequencies.
Possible frequency ratios of the reference clock input to the outputs
are 1:4, 1:3, 1:2, 1:1, 2:3, 4:3 and 3:2. Table 8 through Table 10
illustrate the various output configurations and frequency ratios
supported by the MPC9330.
6
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 8. MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
fref(1) [MHz]
PWR_DN
FSELA
FSELB
FSELC
12.5–30.0
0
0
0
0
fref 4
(50-120 MHz) fref 4
(50-120 MHz) fref 2
0
0
0
1
fref 4
(50-120 MHz) fref 4
(50-120 MHz) fref 4 3
0
0
1
0
fref 4
(50-120 MHz) fref 2
(25-60 MHz) fref 2
0
0
1
1
fref 4
(50-120 MHz) fref 2
(25-60 MHz) fref 4 3
0
1
0
0
fref 2
(25-60 MHz) fref 4
(50-120 MHz) fref 2
0
1
0
1
fref 2
(25-60 MHz) fref 4
(50-120 MHz) fref 4 3
0
1
1
0
fref 2
(25-60 MHz) fref 2
(25-60 MHz) fref 2
0
1
1
1
fref 2
(25-60 MHz) fref 2
(25-60 MHz) fref 4 3
(16.6-40 MHz)
1
0
0
0
fref 2
(25-60 MHz) fref 2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
0
1
fref 2
(25-60 MHz) fref 2
1
0
1
0
fref 2
(25-60 MHz) fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
0
1
1
fref 2
(25-60 MHz) fref
(12.5-30 MHz) fref 2 3
(8.33-20 MHz)
1
1
0
0
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref
(12.5-30 MHz)
1
1
0
1
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref 2 3
(8.33-20 MHz)
1
1
1
0
fref
(12.5-30 MHz) fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
1
1
1
fref
(12.5-30 MHz) fref
(12.5-30 MHz) fref 2 3
(8.33-20 MHz)
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
(25-60 MHz) fref 2 3
(25-60 MHz)
(16.6-40 MHz)
(25-60 MHz)
(16.6-40 MHz)
(25-60 MHz)
(16.6-40 MHz)
(25-60 MHz)
(8.33-20 MHz)
1. fref is the input clock reference frequency (CCLK or XTAL).
Table 9. MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
PLL
Feedback
fref(1)
[MHz]
VCO 4(2)
50–120
VCO 8(3)
25–60
VCO 12(4) 16.67–40
1.
2.
3.
4.
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
0
0
fref
(50-120 MHz) fref
(50-120 MHz) fref 2
(25-60 MHz)
0
0
1
fref
(50-120 MHz) fref
(50-120 MHz) fref 3
(16.6-40 MHz)
0
1
0
fref
(50-120 MHz) fref 2
(25-60 MHz) fref 2
(25-60 MHz)
0
1
1
fref
(50-120 MHz) fref 2
(25-60 MHz) fref 3
(16.6-40 MHz)
1
0
0
fref
(25-60 MHz) fref 2
(50-120 MHz) fref
1
0
1
fref
(25-60 MHz) fref 2
(50-120 MHz) fref 2 3
(25-60 MHz)
1
1
0
fref
(25-60 MHz) fref
(25-60 MHz) fref
1
1
1
fref
(25-60 MHz) fref
(25-60 MHz) fref 2 3
0
0
1
fref 3
(50-120 MHz) fref 3
0
1
1
fref 3
(50-120 MHz) fref 3 2
1
0
1
fref 3 2
(25-60 MHz) fref 3
1
1
1
fref 3 2
(25-60 MHz) fref 3 2
(16.6-40 MHz)
(25-60 MHz)
(16.6-40 MHz)
(50-120 MHz) fref
(16.6-40 MHz)
(25-60 MHz) fref
(16.6-40 MHz)
(50-120 MHz) fref
(16.6-40 MHz)
(25-60 MHz) fref
(16.6-40 MHz)
fref is the input clock reference frequency (CCLK or XTAL).
QAx connected to FB_IN and FSELA=0, PWR_DN=0.
QAx connected to FB_IN and FSELA=1, PWR_DN=0.
QCx connected to FB_IN and FSELC=1, PWR_DN=0.
Table 10. MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
PLL
Feedback
fref(1)
[MHz]
FSELA
FSELB
FSELC
VCO 16(2)
12.5–30
1
0
0
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref 2 3
(8.33-20 MHz)
1
1
0
fref
(12.5-30 MHz) fref
(12.5-30 MHz) fref
1
1
1
fref
(12.5-30 MHz) fref
(12.5-30 MHz) fref 2 3
0
0
1
fref 3
(25-60 MHz) fref 3
(25-60 MHz) fref
(8.33-20 MHz)
(25-60 MHz) fref 3 2 (12.5-30 MHz) fref
(8.33-20 MHz)
VCO 24(3)
8.33–20
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
(12.5-30 MHz)
(8.33-20 MHz)
0
1
1
fref 3
1
0
1
fref 3 2 (12.5-30 MHz) fref 3
(25-60 MHz) fref
(8.33-20 MHz)
1
1
1
fref 3 2 (12.5-30 MHz) fref 3 2 (12.5-30 MHz) fref
(8.33-20 MHz)
1. fref is the input clock reference frequency (CCLK or XTAL).
2. QAx connected to FB_IN and FSELA=1, PWR_DN=1.
3. QCx connected to FB_IN and FSELC=1, PWR_DN=1.
MPC9330 REVISION 8 3/11/16
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©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC9330 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if this
noise is seen on the power supply pins. Random noise on the
VCC_PLL power supply impacts the device characteristics, for
instance, I/O jitter. The MPC9330 provides separate power supplies
for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of
the device. The purpose of this design technique is to isolate the
high switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system environment
where it is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but effective
form of isolation is a power supply filter on the VCC_PLL pin for the
MPC9330. Figure 3 illustrates a typical power supply filter scheme.
The MPC9330 frequency and phase stability is most susceptible to
noise with spectral content in the 100 kHz to 20 MHz range.
Therefore the filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is the DC
voltage drop across the series filter resistor RF. From the data sheet,
the ICC_PLL current (the current sourced through the VCC_PLL pin) is
typically 5 mA (10 mA maximum), assuming that a minimum of
2.985 V must be maintained on the VCC_PLL pin. The resistor RF
shown in Figure 3 should have a resistance of 10–15 to meet the
voltage drop criteria.
RF = 10 – 15
VCC
Driving Transmission Lines
The MPC9330 clock driver was designed to drive high-speed
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were designed
to exhibit the lowest impedance possible. With an output impedance
of less than 20 the drivers can drive either parallel or series
terminated transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note AN1091.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme, either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50 resistance to VCC2.
This technique draws a fairly high level of DC current and thus
only a single terminated line can be driven by each output of the
MPC9330 clock driver. For the series terminated case, however,
there is no DC current draw, thus the outputs can drive multiple
series terminated lines. Figure 4 illustrates an output driving a single
series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9330 clock driver
is effectively doubled due to its capability to drive multiple lines.
MPC9330
Output
Buffer
CF = 22 F
IN
RF
14
RS = 36
ZO = 50
RS = 36
ZO = 50
RS = 36
ZO = 50
OutA
VCC_PLL
CF
10 nF
MPC9330
Output
Buffer
MPC9330
VCC
33...100 nF
IN
OutB0
14
OutB1
Figure 3. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are defined
by the required filter characteristics: the RC filter should provide an
attenuation greater than 40 dB for noise whose spectral content is
above 100 kHz. In the example RC filter shown in Figure 3, the filter
cut-off frequency is around 3-5 kHz, and the noise attenuation at 100
kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of an
individual capacitor, its overall impedance begins to look inductive
and, thus, increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance path to
ground exists for frequencies well above the bandwidth of the PLL.
Although the MPC9330 has several design features to minimize the
susceptibility to power supply noise (isolated power and grounds
and fully differential PLL), there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
MPC9330 REVISION 8 3/11/16
Figure 4. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation results of an
output driving a single line versus two lines. In both cases, the drive
capability of the MPC9330 output buffer is more than sufficient to
drive 50 transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9330. The output waveform in
Figure 5 shows a step in the waveform; this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 36 series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
8
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Since this step is well above the threshold region, it will not cause
any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better match
the impedances when driving multiple lines, the situation in Figure 6
should be used. In this case the series terminating resistors are
reduced such that when the parallel combination is added to the
output buffer impedance, the line impedance is perfectly matched.
= VS ( Z0 (RS+R0 + Z0))
= 50 || 50
= 36 || 36
= 14
= 3.0 (25 (18+14+25)
= 1.31 V
At the load end, the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
Final skew data pending specification.
VL
Z0
RS
R0
VL
MPC9330
Output
Buffer
OutA
tD = 3.8956
OutB
tD = 3.9386
RS = 22
ZO = 50
14 + 22 || 22 = 50 || 50
25 = 25
2.0
Voltage (V)
ZO = 50
14
3.0
2.5
RS = 22
In
1.5
Figure 6. Optimized Dual Line Termination
1.0
0.5
0
2
4
6
8
Time (ns)
10
12
14
Figure 5. Single versus Dual Waveforms
MPC9930 DUT
Pulse
Generator
Z = 50
ZO = 50
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 7. CCLK MPC9330 AC Test Reference for Vcc = 3.3 V
MPC9330 REVISION 8 3/11/16
9
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
VCC
VCC 2
GND
VCC
VCC
VCC 2
CCLK
GND
VCC 2
GND
tSK(O)
VCC
VCC 2
FB_IN
GND
t()
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
Figure 8. Output-to-Output Skew tSK(O)
Figure 9. Propagation Delay (t(), static phase offset)
Test Reference
VCC
VCC 2
CCLK
GND
tP
FB_EN
T0
DC = tP/T0 x 100%
TJIT() = |T0–T1mean|
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
Figure 10. Output Duty Cycle (DC)
Figure 11. I/O Jitter
TN
TN+1
TJIT(CC) = |TN–TN+1|
TJIT(PER) = |TN–1/f0|
T0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
Figure 12. Cycle-to-Cycle Jitter
Figure 13. Period Jitter
VCC=3.3 V
2.4
0.55
tF
tR
Figure 14. Output Transition Time Test Reference
MPC9330 REVISION 8 3/11/16
10
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
PACKAGE DIMENSIONS
4X
0.20 H
6
A-B D
D1
3
e/2
D1/2
PIN 1 INDEX
32
A, B, D
25
1
E1/2 A
F
B
6 E1
E
4
F
DETAIL G
8
17
9
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
4
D
4X
A-B D
H
SEATING
PLANE
DETAIL G
D
D/2
0.20 C
E/2
28X
e
32X
C
0.1 C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
b
8X
(θ1˚)
0.20
R R2
A2
8
C A-B D
SECTION F-F
R R1
A
M
5
0.25
GAUGE PLANE
A1
(S)
L
(L1)
θ˚
DETAIL AD
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
q
q1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0˚
7˚
12 REF
0.08
0.20
0.08
--0.20 REF
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC9330 REVISION 8 3/11/16
11
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
Description of Change
Date
12/19/12
8
1
NRND – Not Recommend for New Designs
8
1
Removed NRND
5/5/15
1
Product Discontinuation Notice - Last time buy expires September 7, 2016.
PDN N-16-02
3/11/16
8
MPC9330 REVISION 8 3/11/16
12
©2016 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
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