MPC9865VMR2

Freescale Semiconductor Technical Data Advance Information Clock Generator for PowerQUICC III Clock Generator for PowerQUICC III The MPC9865 is a PLL based clock generator specifically designed for Freescale Microprocessor and Microcontroller applications including the PowerPC and PowerQUICC. This device generates a microprocessor input clock. The microprocessor clock is selectable in output frequency to any of the commonly used microprocessor input and bus frequencies. The device offers eight low skew clock outputs in two banks, each configurable to support different clock frequencies. The extended temperature range of the MPC9865 supports telecommunication and networking requirements. MPC9865 DATA SHEET Rev 2, May/2006 MPC9865 MPC9865 MICROPROCESSOR CLOCK GENERATOR Features • • • • • • • • • • • 8 LVCMOS outputs for processor and other circuitry Crystal oscillator or external reference input 25 or 33 MHz Input reference frequency Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33, or 16 MHz Buffered reference clock output (2 copies) Low cycle-to-cycle and period jitter 100-lead PBGA package 100-lead Pb-free package available 3.3 V supply with 3.3 V or 2.5 V LVCMOS output supplies Supports computing, networking, telecommunications applications Ambient temperature range –40°C to +85°C SCALE 2 1 VF SUFFIX VM SUFFIX (PB-FREE) 100 MAPBGA PACKAGE CASE 1462-01 Functional Description The MPC9865 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60, or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83, 66, 50, 33, or 16 MHz. The single-ended LVCMOS outputs provide 8 low skew outputs for use in driving a microprocessor or microcontroller clock input as well as other system components. The input reference, either crystal or external input is also buffered to a separate dual outputs that my be used as the clock source for a Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of XTAL_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33 MHz configuration pin is used to select between a 33 and 25 MHz input frequency. The MPC9865 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. IDT™ Clock Generator for PowerQUICC III © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1 MPC9865 MPC9865 Clock Generator for PowerQUICC III CLK PCLK PCLK NETCOM 0 1 ÷N Ref QA1 PLL OSC QA0 0 1 CLK_SEL XTAL_IN 1 0 2000 MHz QA2 XTAL_OUT QA3 XTAL_SEL ÷N QB0 PLL_BYPASS QB1 REF_33 MHz QB2 QB3 CLK_A[0:5] CLK_B[0:5] REF_OUT0 MR REF_OUT1 REF_OUT1_E Figure 1. MPC9865 Logic Diagram MPC9865 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 2 MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM Table 1. Pin Configurations Pin I/O Type Function Supply Active/State CLK Input LVCMOS PLL Reference Clock Input (pull-down) VDD PCLK, PCLK Input LVPECL VDD — VDDOA — VDD — LVCMOS Crystal Oscillator Input Pin VDD — LVCMOS Crystal Oscillator Output Pin VDD — PLL reference clock input (PCLK — pull-down, PCLK — pull-up and pull-down) QA0, QA1, QA2, QA3 QB0, QB1, QB2, QB3 Output LVCMOS Clock Outputs REF_OUT0 REF_OUT1 Output LVCMOS Reference Output (25 MHz or 33 MHz) XTAL_IN Input XTAL_OUT Output CLK_SEL Input LVCMOS Select between CLK and PCLK input (pull-down) VDD High XTAL_SEL Input LVCMOS Select between External Input and Crystal Oscillator Input (pull-down) VDD High REF_33 MHz Input LVCMOS Selects 33 MHz input (pull-down) VDD High REF_OUT1_E Input LVCMOS Enables REF_OUT1 output (pull-down) VDD High MR Input LVCMOS Master Reset (pull-up) VDD Low PLL_BYPASS Input LVCMOS Select PLL or static test mode (pull-down) VDD High CLK_A[0:5](1) Input LVCMOS Configures Bank A clock output frequency (pull-up) VDD — CLK_B[0:5](2) Input LVCMOS Configures Bank B clock output frequency (pull-up) VDD — VDD — — 3.3 V Supply — — VDDA — — Analog Supply — — VDDOA — — Output Supply — Bank A — — VDDOB — — Output Supply — Bank B — — GND — — Ground — — 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb). 2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb). Table 2. Function Table Control Default 0 1 CLK_SEL 0 CLK PCLK XTAL_SEL 0 CLKx XTAL PLL_BYPASS 0 Normal Bypass REF_OUT1_E 0 Disables REF_OUT1 Enables REF_OUT1 REF_33 MHz 0 Selects 25 MHz Reference Selects 33 MHz Reference MR 1 Reset Normal CLK_A and CLK_B control output frequencies. See Table 3 for specific device configuration. IDT™ Clock Generator for PowerQUICC III Clock Drivers Devices has been acquired by Integrated Device Technology, Inc FreescaleAdvanced Timing Solutions Organization Freescale Semiconductor 3 MPC9865MPC9865 3 MPC9865 Clock Generator for PowerQUICC III NETCOM Table 3. Output Configurations (Banks A & B) CLK_x[0:5](1) CLK_x[0] (msb) CLK_x[1] CLK_x[2] CLK_x[3] CLK_x[4] CLK_x[5] (lsb) N Frequency (MHz) 111111 1 1 1 1 1 1 126 15.87 111100 1 1 1 1 0 0 120 16.67 101000 1 0 1 0 0 0 80 25.00 011110 0 1 1 1 1 0 60 33.33 010100 0 1 0 1 0 0 40 50.00 010000 0 1 0 0 0 0 32 62.5 001111 0 0 1 1 1 1 30 66.67 001100 0 0 1 1 0 0 24 83.33 001010 0 0 1 0 1 0 20 100.00 001001 0 0 1 0 0 1 18 111.11 001000 0 0 1 0 0 0 16 125.00 000111 0 0 0 1 1 1 15 133.33 000110 0 0 0 1 1 0 12 166.67 000101 0 0 0 1 0 1 10 200.00 000100 0 0 0 1 0 0 (2) 8 250 1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb). 2. Minimum value for N. MPC9865 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 4 MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM OPERATION INFORMATION Output Frequency Configuration The MPC9865 was designed to provide the commonly used frequencies in PowerQUICC, PowerPC and other microprocessor systems. Table 3 lists the configuration values that will generate those common frequencies. The MPC9865 can generate numerous other frequencies that may be useful in specific applications. The output frequency (fout) of either Bank A or Bank B may be calculated by the following equation. fout = 2000 / N where fout is in MHz and N = 2 * CLK_x[0:5] This calculation is valid for all values of N from 8 to 126. Note that N = 15 is a modified case of the configuration inputs CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to 00111 or 7. Crystal Input Operation TBD Power-Up and MR Operation Figure 2 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. See Table 9 for actual parameter values. The MPC9865 may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD MR treset_rel treset_pulse Figure 2. MR Operation Power Supply Bypassing The MPC9865 is a mixed analog/digital product. The architecture of the MPC9865 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VDD pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VDD VDD 22 μF 0.1 μF Power Consumption Calculation For unloaded outputs the power consumption of the MPC9855 can be calculated as follows. P = VDD * IDDBASE + nA * (VDDOA ** 2 * CPD * fA) + nB * (VDDOB ** 2 * CPD * fB) where VDD = core supply voltage IDDBASE = base supply current nA = number of A bank outputs (= 4) nB = number of B bank outputs (= 4) VDDOA = voltage supply on bank A outputs VDDOB = voltage supply on bank B outputs CPD = power dissipation capacitance fA = frequency of bank A outputs fB = frequency of bank B outputs MPC9865 15 Ω VDDA 0.1 μF Figure 3. VCC Power Supply Bypass IDT™ Clock Generator for PowerQUICC III Clock Drivers Devices has been acquired by Integrated Device Technology, Inc FreescaleAdvanced Timing Solutions Organization Freescale Semiconductor 5 MPC9865MPC9865 5 MPC9865 Clock Generator for PowerQUICC III NETCOM Table 4. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VDD Supply Voltage (core) –0.3 3.8 V VDDA Supply Voltage (Analog Supply Voltage) –0.3 VDD V VDDOx Supply Voltage (LVCMOS output for Bank A and B) –0.3 VDD V DC Input Voltage –0.3 VDD+0.3 V –0.3 VDDx+0.3 V ±20 mA ±50 mA 125 °C VIN VOUT IIN IOUT TS (2) DC Output Voltage DC Input Current DC Output Current Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific output pin. Table 5. General Specifications Symbol Characteristics Min Typ Max Unit Condition VDD ÷ 2 V Input Capacitance 4 pF Inputs CPD Power Dissipation Capacitance 10 pF Per Output θJA Thermal Resistance (Junction-to-Ambient) 54.5 °C/W Air flow = 0 TA Ambient Temperature VTT Output Termination Voltage CIN –40 85 °C Table 6. DC Characteristics (TA = –40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition TBD TBD mA VDD + VDDA pins TBD mA VDDIN pins Supply Current for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5% IDDBASE IDDA Base Supply Current (Core) Maximum Quiescent Supply Current (Analog Supply) MPC9865 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 6 6 MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM Table 7. LVPECL DC Characteristics (TA = –40°C to 85°C)(1) Symbol Characteristics Min Typ Max Unit Condition Differential LVPECL Clock Inputs (CLK1, CLK1) for VDD = 3.3 V ± 0.5% VPP VCMR Differential Voltage(2) (peak-to-peak) (LVPECL) 250 Differential Input Crosspoint Voltage(3) (LVPECL) 1.0 mV VDD – 0.6 V 1. AC characteristics are design targets and pending characterization. 2. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Table 8. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS for VDD = 3.3 V ± 5% VIH Input High Voltage VIL Input Low Voltage IIN Input Current(1) 2.0 VDD + 0.3 V LVCMOS 0.8 V LVCMOS ± 200 μA VIN = VDDL or GND V IOH = –24 mA 0.5 V IOL = 24 mA LVCMOS for VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5 and VDDOB = 3.3 V ± 5% VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance 2.4 Ω 14 – 17 LVCMOS for VDD= 3.3 V ± 5%, VDDOA = 2.5 V ± 5% and VDDOB= 2.5 V ± 5% VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance 1.9 0.4 18 – 22 V IOH = –15 mA V IOL = 15 mA Ω 1. Inputs have pull-down resistors affecting the input current. IDT™ Clock Generator for PowerQUICC III Clock Drivers Devices has been acquired by Integrated Device Technology, Inc FreescaleAdvanced Timing Solutions Organization Freescale Semiconductor 7 MPC9865MPC9865 7 MPC9865 Clock Generator for PowerQUICC III NETCOM Table 9. AC Characteristics (VDD = 3.3 V ± 5%, VDDOAB = 3.3 V ± 5%, TA= –40°C to +85°C)(1) (2) Symbol Characteristics Min Typ Max Unit 250 MHz MHz MHz MHz Condition Input and Output Timing Specification fref 25 33 25 Input Reference Frequency (25 MHz input) Input Reference Frequency (33 MHz input) XTAL Input Input Reference Frequency in PLL Bypass Mode(3) fVCO VCO Frequency Range fMCX Output Frequency frefPW Reference Input Pulse Width frefCcc Input Frequency Accuracy 2000 Bank A output Bank B output 15.87 15.87 MHz 200 200 MHz MHz 2 tr, tf Output Rise/Fall Time 150 DC Output Duty Cycle 45 PLL bypass PLL locked ns 50 100 ppm 500 ps 20% to 80% 55 % Bank A and B 10 ms PLL Specifications tLOCK treset_ref treset_pulse Maximum PLL Lock Time MR Hold Time on Power Up 10 ns MR Hold Time 10 ns Skew and Jitter Specifications tsk(O) Output-to-Output Skew (within a bank) 50 ps tsk(O) Output-to-Output Skew (across banks A and B) 100 ps VDDOA = 3.3 V VDDOB = 3.3 V tJIT(CC) Cycle-to-Cycle Jitter 150 ps Bank A and B tJIT(PER) Period Jitter 150 ps Bank A and B Output Rise/Fall Time TBD ns 20% to 80% tr, tf 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50Ω to VTT. 3. In bypass mode, the MPC9865 divides the input reference clock. Pulse Generator Z = 50Ω ZO = 50Ω RT = 50Ω ZO = 50Ω DUT MPC9865 RT = 50Ω VTT VTT Figure 4. MPC9865 AC Test Reference (LVCMOS Outputs) MPC9865 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 8 8 MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM Table 10. MPC9865 Pin Diagram (Top View) 1 2 3 4 5 6 7 8 9 10 A VDDOA VDDOA CLKA[1] CLKA[3] CLKA[5] VDD QA1 QA2 VDDOA VDDOA B VDDOA VDDOA CLKA[0] CLKA[2] CLKA[4] QA0 VDDOA QA3 VDDOA VDDOA C RSVD RSVD VDD VDD VDD VDD VDD VDD VDD REF_OUT[0] D VDDA VDDA VDD GND GND GND GND VDD RSVD REF_OUT[1] E XTAL_SEL CLK VDD GND GND GND GND VDD VDD GND F PCLK PCLK VDD GND GND GND GND VDD RSVD RSVD G CLK_SEL REF_33MHz VDD GND GND GND GND VDD PLL_BYPASS MR H XTAL_IN XTAL_OUT VDD VDD VDD VDD VDD VDD RSVD REF_OUT1E J VDDOB VDDOB CLKB[0] CLKB[2] CLKB[4] QB0 VDDOB QB3 VDDOB VDDOB K VDDOB VDDOB CLKB[1] CLKB[3] CLKB[5] VDD QB1 QB2 VDDOB VDDOB Table 11. MPC9865 Pin List Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA Signal 100 Pin MAPBGA VDDOA A1 RSVD C1 XTAL_SEL E1 CLK_SEL G1 VDDOB J1 VDDOA A2 RSVD C2 CLK E2 REF_33MHz G2 VDDOB J2 CLKA[1] A3 VDD C3 VDD E3 VDD G3 CLKB[0] J3 CLKA[3] A4 VDD C4 GND E4 GND G4 CLKB[2] J4 CLKA[5] A5 VDD C5 GND E5 GND G5 CLKB[4] J5 VDD A6 VDD C6 GND E6 GND G6 QB0 J6 QA1 A7 VDD C7 GND E7 GND G7 VDDOB J7 QA2 A8 VDD C8 VDD E8 VDD G8 QB3 J8 VDDOA A9 VDD C9 VDD E9 PLL_BYPASS G9 VDDOB J9 VDDOA A10 REF_OUT0 C10 GND E10 MR G10 VDDOB J10 VDDOA B1 VDDA D1 PCLK F1 XTAL_IN H1 VDDOB K1 VDDOA B2 VDDA D2 PCLK F2 XTAL_OUT H2 VDDOB K2 CLKA[0] B3 VDD D3 VDD F3 VDD H3 CLKB[1] K3 CLKA[2] B4 GND D4 GND F4 VDD H4 CLKB[3] K4 CLKA[4] B5 GND D5 GND F5 VDD H5 CLKB[5] K5 QA0 B6 GND D6 GND F6 VDD H6 VDD K6 VDDOA B7 GND D7 GND F7 VDD H7 QB1 K7 QA3 B8 VDD D8 VDD F8 VDD H8 QB2 K8 VDDOA B9 RSVD D9 RSVD F9 RSVD H9 VDDOB K9 VDDOA B10 REF_OUT1 D10 RSVD F10 REF_OUT1_E H10 VDDOB K10 IDT™ Clock Generator for PowerQUICC III Clock Drivers Devices has been acquired by Integrated Device Technology, Inc FreescaleAdvanced Timing Solutions Organization Freescale Semiconductor 9 MPC9865MPC9865 9 MPC9865 Clock Generator for PowerQUICC III NETCOM PACKAGE DIMENSIONS PAGE 1 OF 2 VA SUFFIX VM SUFFIX (PB-FREE) 100 MAPBGA PACKAGE CASE 1462-01 ISSUE A MPC9865 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 10 MPC9865 Advanced Clock Drivers Devices Freescale Semiconductor MPC9865 Clock Generator for PowerQUICC III NETCOM PACKAGE DIMENSIONS PAGE 2 OF 2 VA SUFFIX VM SUFFIX (PB-FREE) 100 MAPBGA PACKAGE CASE 1462-01 ISSUE A IDT™ Clock Generator for PowerQUICC III Clock Drivers Devices has been acquired by Integrated Device Technology, Inc FreescaleAdvanced Timing Solutions Organization Freescale Semiconductor 11 MPC9865MPC9865 11 MPC9865 MPC92459 PART NUMBERS 900 Clock MHz Generator Low Voltage forNAME PowerQUICC LVDS Clock III Synthesizer INSERT PRODUCT AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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