R1LV0416CBG-7LI

R1LV0416CBG-I Series Wide Temperature Range Version 4M SRAM (256-kword × 16-bit) REJ03C0259-0001 Preliminary Rev.0.01 Jan.11.2005 Description The R1LV0416CBG-I is a 4-Mbit static RAM organized 256-kword × 16-bit. The R1LV0416C-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The R1LV0416CBG-I Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 48-pin CSP (0.75 mm ball pitch). Features • Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V • Fast access time: 55/70 ns (max) • Power dissipation:  Active: 5.0 mW/MHz (typ)(VCC = 2.5 V) : 6.0 mW/MHz (typ) (VCC = 3.0 V)  Standby: 1.25 µW (typ) (VCC = 2.5 V) : 1.5 µW (typ) (VCC = 3.0 V) • Completely static memory.  No clock or timing strobe required • Access and cycle times are equal. • Common data input and output.  Three state output • Battery backup operation.  2 chip selection for battery backup • Temperature range: −40 to +85°C Ordering Information Type No. R1LV0416CBG-5SI R1LV0416CBG-7LI Access time 55 ns 70 ns Package 48-ball CSP with 0.75 mm ball pitch (48FHH) Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specifications. Rev.0.01, Jan.11.2005, page 1 of 14 R1LV0416CBG-I Series Pin Arrangement 48-ball CSP 1 A LB# 2 OE# 3 A0 4 A1 5 A2 6 CS2 B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE# I/O7 H NC A8 A9 A10 A11 NC (Top view) Pin Description Pin name A0 to A17 I/O0 to I/O15 CS1# (CS1) CS2 WE# (WE) OE# (OE) LB# (LB) UB# (UB) VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Power supply Ground No connection Rev.0.01, Jan.11.2005, page 2 of 14 R1LV0416CBG-I Series Block Diagram LSB A12 A11 A10 A9 A8 A13 A14 A15 A16 MSB A17 A7 Row decoder • • • • • V CC V SS Memory matrix 2,048 x 2,048 I/O0 Input data control I/O15 • • Column I/O Column decoder • • LSB A4 A3 A2 A1 A5 A6 A0 MSB • • CS2 CS1# LB# UB# WE# OE# Control logic Rev.0.01, Jan.11.2005, page 3 of 14 R1LV0416CBG-I Series Operation Table CS1# CS2 WE# OE# H × × × × L × × × × × × L H H L L H H L L H H L L H L × L H L × L H L × L H H H Note: H: VIH, L: VIL, ×: VIH or VIL UB# × × H L H L L H L × LB# × × H L L H L L H × I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature range Storage temperature range under bias Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. Symbol VCC VT PT Topr Tstg Tbias Value −0.5 to +4.6 −0.5*1 to VCC + 0.3*2 0.7 −40 to +85 −65 to +150 −40 to +85 Unit V V W °C °C °C DC Operating Conditions (Ta = −40 to +85°C) Symbol Supply voltage VCC VSS Input high voltage VCC = 2.2 V to 2.7 V VIH VCC = 2.7 V to 3.6 V VIH Input low voltage VCC = 2.2 V to 2.7 V VIL VCC = 2.7 V to 3.6 V VIL Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Parameter Min 2.2 0 2.0 2.2 −0.2 −0.3 Typ 2.5/3.0 0     Max 3.6 0 VCC + 0.3 VCC + 0.3 0.4 0.6 Unit V V V V V V Note 1 1 Rev.0.01, Jan.11.2005, page 4 of 14 R1LV0416CBG-I Series DC Characteristics Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| Min   Typ   Max Unit Test conditions 1 µA Vin = VSS to VCC 1 µA CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC 20 mA CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA 25 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1# ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V 0.3 mA CS2 = VIL 10 µA Vin ≥ 0 V 8 µA (1) 0 V ≤ CS2 ≤ 0.2 V or Operating current Average operating current ICC ICC1   5*1 8*1 ICC2  2*1 Standby current Standby current −5SI to +85°C to +70°C to +40°C to +25°C ISB ISB1 ISB1 ISB1 ISB1    0.1*1    0.7*2 3 µA (2) CS1# ≥ VCC − 0.2 V, 1  0.5* 2.5 µA CS2 ≥ VCC − 0.2 V or −7LI to +85°C ISB1   20 µA (3) LB# = UB# ≥ VCC − 0.2 V, to +70°C ISB1   16 µA CS2 ≥ VCC − 0.2 V, to +40°C ISB1  0.7*2 10 µA CS1# ≤ 0.2 V to +25°C ISB1  0.5*1 10 µA Output high voltage VCC =2.2 V to 2.7 V VOH 2.0 — — V IOH = −0.5 mA VCC =2.7 V to 3.6 V VOH 2.4 — — V IOH = −1 mA VCC =2.2 V to 3.6 V VOH2 VCC − 0.2 — — V IOH = −100 µA Output low voltage VCC =2.2 V to 2.7 V VOL — — 0.4 V IOL = 0.5 mA VCC =2.7 V to 3.6 V VOL — — 0.4 V IOL = 2 mA VCC =2.2 V to 3.6 V VOL2 — — 0.2 V IOL = 100 µA Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Input capacitance Cin  Input/output capacitance CI/O  Note: 1. This parameter is sampled and not 100% tested. Typ   Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 Rev.0.01, Jan.11.2005, page 5 of 14 R1LV0416CBG-I Series AC Characteristics (Ta = −40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V) : VIL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V) • Input rise and fall time: 5 ns • Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) : 1.4 V (VCC = 2.7 V to 3.6 V) • Output load: See figures (Including scope and jig) VTM 1.4 V R1 Dout R1 = 3070 Ω 30pF R2 R2 = 3150 Ω VTM = 2.3 V Dout 50pF RL=500 Ω Output load (A) (VCC = 2.2 V to 2.7 V) Output load (B) (VCC = 2.7 V to 3.6 V) Read Cycle R1LV0416CBG-I -5SI -7LI Max Min  70 55  55  55  35   10 55   10  10  5  5 20 0 20 0 20 0 20 0 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z LB#, UB# disable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#, UB# disable to high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tBA tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ Min 55     10  10 10 5 5 0 0 0 0 Max  70 70 70 40  70     25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Rev.0.01, Jan.11.2005, page 6 of 14 R1LV0416CBG-I Series Write Cycle R1LV0416CBG-I -5SI -7LI Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 55  70  ns Address valid to end of write tAW 50  60  ns Chip selection to end of write tCW 50  60  ns 5 Write pulse width tWP 40  50  ns 4 LB#, UB# valid to end of write tBW 50  55  ns Address setup time tAS 0  0  ns 6 Write recovery time tWR 0  0  ns 7 Data to write time overlap tDW 25  30  ns Data hold from write time tDH 0  0  ns Output active from end of write tOW 5  5  ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3 Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.0.01, Jan.11.2005, page 7 of 14 R1LV0416CBG-I Series Timing Waveform Read Timing Waveform (WE# = VIH) t RC Address tAA tACS1 CS1# tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address CS2 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB#, UB# tBLZ*2, 3 tOE OE# tOLZ*2, 3 Dout High impedance Valid data tOH tOHZ*1, 2, 3 Rev.0.01, Jan.11.2005, page 8 of 14 R1LV0416CBG-I Series Write Timing Waveform (1) (WE# Clock) tWC Address Valid address tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tAW tWP*4 WE# tAS*6 tDW Din tWHZ*1, 2 Valid data tDH tOW*2 High impedance Dout Rev.0.01, Jan.11.2005, page 9 of 14 R1LV0416CBG-I Series Write Timing Waveform (2) (CS# Clock, OE# = VIH) tWC Address Valid address tAW tAS*6 CS1# tCW*5 CS2 tBW LB#, UB# tCW*5 tWR*7 tWP*4 WE# tDW Din Valid data tDH High impedance Dout Rev.0.01, Jan.11.2005, page 10 of 14 R1LV0416CBG-I Series Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH) tWC Address Valid address tAW tCW*5 CS1# tCW*5 CS2 tAS*6 LB#, UB# tBW tWR*7 tWP*4 WE# tDW Din Valid data tDH High impedance Dout Rev.0.01, Jan.11.2005, page 11 of 14 R1LV0416CBG-I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ  Max  Unit Test conditions*3 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V µA µA µA µA µA µA µA µA ns ns VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V Data retention current −5SI to +85°C to +70°C to +40°C to +25°C ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR tCDR tR          0.7*2 0.5*   0.7*2 1 1 10 8 3 2.5 20 16 10 10   −7LI to +85°C to +70°C to +40°C to +25°C Chip deselect to data retention time Operation recovery time  0.5* 0  tRC*4  See retention waveform Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed. 3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. 4. tRC = read cycle time. Rev.0.01, Jan.11.2005, page 12 of 14 R1LV0416CBG-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) (VCC = 2.2 V to 2.7 V) t CDR V CC 2.2 V Data retention mode tR V DR 2.0 V CS1# 0V CS1# ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (2) (CS1# Controlled) (VCC = 2.7 V to 3.6 V) t CDR V CC 2.7 V Data retention mode tR 2.2 V V DR CS1# 0V CS1# ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (3) (CS2 Controlled) (VCC = 2.2 V to 2.7 V) t CDR V CC 2.2 V CS2 V DR 0.4 V 0V 0 V < CS2 < 0.2 V Data retention mode tR Low VCC Data Retention Timing Waveform (4) (CS2 Controlled) (VCC = 2.7 V to 3.6 V) t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR Rev.0.01, Jan.11.2005, page 13 of 14 R1LV0416CBG-I Series Low VCC Data Retention Timing Waveform (5) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V) t CDR V CC 2.2 V Data retention mode tR V DR 2.0 V LB#, UB# 0V LB#, UB# ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (6) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V) t CDR V CC 2.7 V Data retention mode tR 2.2 V V DR LB#, UB# 0V LB#, UB# ≥ VCC – 0.2 V Rev.0.01, Jan.11.2005, page 14 of 14 Revision History Rev. 0.01 Date Jan.11.2005 Page Initial issue  R1LV0416CBG-I Series Contents of Modification Description Sales Strategic Planning Div. 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