R1LV0416DBG-5SI

R1LV0416D Series 4M SRAM (256-kword × 16-bit) REJ03C0311-0100 Rev.1.00 May.24.2007 Description The R1LV0416D is a 4-Mbit static RAM organized 256-kword × 16-bit, fabricated by Renesas's high-performance 0.15µm CMOS and TFT technologies. R1LV0416D Series has realized higher density, higher performance and low power consumption. The R1LV0416D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. The R1LV0416D Series is packaged in a 44-pin thin small outline mount device, or a 48-ball fine pitch ball grid array. Features • Single 3.0 V supply: 2.7 V to 3.6 V • Fast access time: 55/70 ns (max) • Power dissipation:  Standby: 3 µW (typ) (VCC = 3.0 V) • Equal access and cycle times • Common data input and output.  Three state output • Battery backup operation.  2 chip selection for battery backup • Temperature Range: -40 to +85°C Rev.1.00, May.24.2007, page 1 of 15 R1LV0416D Series Ordering Information Type No. R1LV0416DSB-5SI R1LV0416DSB-7LI R1LV0416DBG-5SI R1LV0416DBG-7LI Access time 55 ns 70 ns 55 ns 70 ns 400-mil 44-pin plastic TSOP II PTSB0044GA-A (44P3W-H) 48-ball CSP with 0.75 mm ball pitch PTBG0048HB-A (48FHH) Package Rev.1.00, May.24.2007, page 2 of 15 R1LV0416D Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 48-ball CSP 1 A LB# 2 OE# 3 A0 4 A1 5 A2 6 CS2 B I/O8 UB# A3 A4 CS1# I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE# I/O7 H NC A8 A9 A10 A11 NC (Top view) Pin Description Pin name A0 to A17 I/O0 to I/O15 CS1# (CS1) CS2 OE# (OE) WE# (WE) LB# (LB) UB# (UB) VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Output enable Write enable Lower byte select Upper byte select Power supply Ground No connection Rev.1.00, May.24.2007, page 3 of 15 R1LV0416D Series Block Diagram LSB V CC V SS • • • • • A13 A7 A8 A9 A10 A11 A12 A6 A14 A15 A16 Row decoder Memory matrix 2,048 x 2,048 MSB I/O0 Input data control I/O15 • • Column I/O Column decoder • • LSB A0 A1 A2 A3 A4 A5 A17 MSB • • CS2 CS1# LB# UB# WE# OE# Control logic Rev.1.00, May.24.2007, page 4 of 15 R1LV0416D Series Operation Table CS1# H × × L L L L L L L CS2 × L × H H H H H H H WE# × × × H H H L L L H OE# × × × L L L × × × H UB# × × H L H L L H L × LB# × × H L L H L L H × I/O0 to I/O7 High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Operating temperature1 Storage temperature range Storage temperature range under bias Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. Symbol VCC VT PT Topr Tstg Tbias Value −0.5 to +4.6 −0.5*1 to VCC + 0.3*2 0.7 −40 to +85 −65 to +150 −40 to +85 Unit V V W °C °C °C DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 2.7 0 2.2 −0.3 −40 Typ 3.0 0    Max 3.6 0 VCC + 0.3 0.6 +85 Unit V V V V °C 1 Note 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, May.24.2007, page 5 of 15 R1LV0416D Series DC Characteristics Parameter Input leakage current Output leakage current Symbol |ILI| |ILO| Min   Typ   Max 1 1 Unit µA µA Test conditions Vin = VSS to VCC CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current Average operating current ICC ICC1     20 25 mA CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1# ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V mA CS2 = VIL µA µA µA µA µA µA µA µA V V V V Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V Average values IOH = −1 mA IOH = −100 µA IOL = 2 mA IOL = 100 µA ICC2   5 Standby current Standby current −5SI to +85°C to +70°C to +40°C to +25°C −7LI to +85°C to +70°C to +40°C to +25°C Output high voltage ISB ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 ISB1 VOH VOH2 VOL VOL2          2.4 VCC − 0.2 — — 0.1*1    1* 1 0.3 10 8 3 2.5 20 16 10 10 — — 0.4 0.2    1* 1 — — — — Output low voltage Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min   Typ   Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. Rev.1.00, May.24.2007, page 6 of 15 R1LV0416D Series AC Characteristics (Ta = -40 to +85°C, VCC = 2.7 V to 3.6 V) Test Conditions Input pulse levels: VIL = 0.4 V, VIH = 2.4 V • Input rise and fall time: 5 ns • Input/output timing reference levels: 1.4 V • Output load: See figures (Including scope and jig) 1.4 V RL=500 Ω Dout 50 pF Output load Rev.1.00, May.24.2007, page 7 of 15 R1LV0416D Series Read Cycle R1LV0416D -5SI Parameter Read cycle time Address access time Chip select access time Symbol tRC tAA tACS1 tACS2 Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z tOE tOH tBA tCLZ1 tCLZ2 LB#, UB# disable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z tBLZ tOLZ tCHZ1 tCHZ2 LB#, UB# disable to high-Z Output disable to output in high-Z tBHZ tOHZ Min 55     10  10 10 5 5 0 0 0 0 Max  55 55 55 35  55     20 20 20 20 Min 70     10  10 10 5 5 0 0 0 0 -7LI Max  70 70 70 40  70     25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes Rev.1.00, May.24.2007, page 8 of 15 R1LV0416D Series Write Cycle R1LV0416D -5SI Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 55 50 50 40 50 0 0 25 0 5 0 0 Max           20 20 Min 70 60 60 50 55 0 0 30 0 5 0 0 -7LI Max           25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 3 1, 2 6 7 5 4 Notes Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.00, May.24.2007, page 9 of 15 R1LV0416D Series Timing Waveform Read Timing Waveform (WE# = VIH) t RC Address tAA tACS1 CS1# tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address CS2 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB#, UB# tBLZ*2, 3 tOE OE# tOLZ*2, 3 Dout High impedance Valid data tOH tOHZ*1, 2, 3 Rev.1.00, May.24.2007, page 10 of 15 R1LV0416D Series Write Timing Waveform (1) (WE# Clock) tWC Address Valid address tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tAW tWP*4 WE# tAS*6 tDW Din tWHZ*1, 2 Valid data tDH tOW*2 High impedance Dout Rev.1.00, May.24.2007, page 11 of 15 R1LV0416D Series Write Timing Waveform (2) (CS# Clock, OE# = VIH) tWC Address Valid address tAW tAS CS1# tCW*5 CS2 tBW LB#, UB# *6 tCW*5 tWR*7 tWP*4 WE# tDW Din Valid data tDH High impedance Dout Rev.1.00, May.24.2007, page 12 of 15 R1LV0416D Series Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH) tWC Address Valid address tAW tCW*5 CS1# tCW*5 CS2 tAS*6 LB#, UB# tBW tWR*7 tWP*4 WE# tDW Din Valid data tDH High impedance Dout Rev.1.00, May.24.2007, page 13 of 15 R1LV0416D Series Low VCC Data Retention Characteristics (Ta = -40 to +85°C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ  Max  Unit V Test conditions Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V Average values Data retention current −5SI to +85°C to +70°C to +40°C to +25°C ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR ICCDR tCDR tR         0 5    1* 1 10 8 3 2.5 20 16 10 10   µA µA µA µA µA µA µA µA ns ms −7LI to +85°C to +70°C to +40°C to +25°C    1* 1 Chip deselect to data retention time Operation recovery time Note:   See retention waveform 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Rev.1.00, May.24.2007, page 14 of 15 R1LV0416D Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) t CDR V CC 2.7 V Data retention mode tR 2.2 V V DR CS1# 0V CS1# ≥ VCC – 0.2 V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled) t CDR V CC 2.7 V Data retention mode tR 2.2 V V DR LB#, UB# 0V LB#, UB# ≥ VCC – 0.2 V Rev.1.00, May.24.2007, page 15 of 15 Revision History Rev. 0.01 1.00 Date Dec. 25, 2006 May. 24, 2007 R1LV0416D Series Data Sheet Contents of Modification Description Page  Initial issue 2 Ordering Information R1LV0416DSB-5S% to R1LV0416DSB-5SI R1LV0416DSB-7L% to R1LV0416DSB-7LI R1LV0416DBG-5S% to R1LV0416DBG-5SI R1LV0416DBG-7L% to R1LV0416DBG-7LI 3 Pin Arrangement A6 to A13, A13 to A6 4 Change of Block Diagram 5 Absolute Maximum Ratings: Deletion of R ver. specification 5 DC Operating Conditions: Deletion of R ver. specification 6 DC Characteristics ISB1 (-5SI) (to +25°C) max: 3 µA to 2.5 µA AC Characteristics: Change of Test Conditions 7 Low VCC Data Retention Characteristics 14 ICCDR (-5SI) (to +25°C) max: 3 µA to 2.5 µA Deletion of note 2 Sales Strategic Planning Div. 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