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On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
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R1RP0416D Series
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0108-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RP0416D Series is a 4-Mbit high speed static RAM organized 256-k word × 16-bit. It has realized
high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in
400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.
Features
• Single 5.0 V supply: 5.0 V ± 10%
• Access time: 12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 160 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current : 5 mA (max)
: 1.0 mA (max) (L-version)
• Data retention current: 0.5 mA (max) (L-version)
• Data retention voltage: 2 V (min) (L-version)
• Center VCC and VSS type pin out
Ordering Information
Type No.
Access time
Package
R1RP0416DGE-2PR
12 ns
400-mil 44-pin plastic SOJ (44P0K)
R1RP0416DGE-2LR
12 ns
R1RP0416DSB-2PR
12 ns
R1RP0416DSB-2LR
12 ns
Rev.1.00, Mar.12.2004, page 1 of 13
400-mil 44-pin plastic TSOPII (44P3W-H)
R1RP0416D Series
Pin Arrangement
44-pin SOJ
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-pin TSOP
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
(Top View)
Pin Description
Pin name
Function
A0 to A17
Address input
I/O1 to I/O16
Data input/output
CS#
Chip select
OE#
Output enable
WE#
Write enable
UB#
Upper byte select
LB#
Lower byte select
VCC
Power supply
VSS
Ground
NC
No connection
Rev.1.00, Mar.12.2004, page 2 of 13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
R1RP0416D Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
Row
decoder
Internal
voltage VCC
generator
VSS
1024-row × 32-column ×
8-block × 16-bit
(4,194,304 bits)
CS
I/O1
..
.
I/O8
Column I/O
Input
data
control
I/O9
..
.
I/O16
Column decoder
CS
(LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB)
WE#
CS#
LB#
UB#
OE#
CS
Rev.1.00, Mar.12.2004, page 3 of 13
R1RP0416D Series
Operation Table
CS# OE# WE# LB# UB# Mode
VCC current
I/O1−
−I/O8
I/O9−
−I/O16
Ref. cycle
H
×
×
×
×
Standby
ISB, ISB1
High-Z
High-Z
L
H
H
×
×
Output disable
ICC
High-Z
High-Z
L
L
H
L
L
Read
ICC
Output
Output
Read cycle
L
L
H
L
H
Lower byte read ICC
Output
High-Z
Read cycle
L
L
H
H
L
Upper byte read ICC
High-Z
Output
Read cycle
L
L
H
H
H
ICC
High-Z
High-Z
L
×
L
L
L
Write
ICC
Input
Input
Write cycle
L
×
L
L
H
Lower byte write ICC
Input
High-Z
Write cycle
L
×
L
H
L
Upper byte write ICC
High-Z
Input
Write cycle
L
×
L
H
H
High-Z
High-Z
ICC
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
−0.5 to +7.0
Voltage on any pin relative to VSS
VT
−0.5* to VCC + 0.5*
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
−55 to +125
°C
Storage temperature under bias
Tbias
−10 to +85
°C
1
Unit
V
2
V
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Min
Typ
Max
Unit
3
4.5
5.0
5.5
V
4
0
0
0
VIH
2.2
VCC + 0.5*
VIL
−0.5*
0.8
VCC*
VSS*
Input voltage
Notes: 1.
2.
3.
4.
1
VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
Rev.1.00, Mar.12.2004, page 4 of 13
V
2
V
V
R1RP0416D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Test conditions
Input leakage current
|ILI|
2
µA
VIN = VSS to VCC
Output leakage current
|ILO|
2
µA
VIN = VSS to VCC
Operation power supply current
ICC
160
mA
Min cycle
CS# = VIL, lOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB
40
mA
Min cycle, CS# = VIH,
Other inputs = VIH/VIL
ISB1
5
mA
f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
*
Output voltage
Note:
1
1.0*
1
VOL
0.4
V
IOL = 8 mA
VOH
2.4
V
IOH = −4 mA
1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Input capacitance*
1
Input/output capacitance*
Note:
1
Symbol
Min
Max
Unit
Test conditions
CIN
6
pF
VIN = 0 V
CI/O
8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
Rev.1.00, Mar.12.2004, page 5 of 13
R1RP0416D Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
1.5 V
DOUT Zo = 50 Ω
5V
RL = 50 Ω
480 Ω
DOUT
255 Ω
30 pF
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tBLZ, tCHZ, tOHZ,
tBHZ, tWHZ, and tOW)
Read Cycle
R1RP0416D
-2
Parameter
Symbol
Min
Max
Unit
Read cycle time
tRC
12
ns
Address access time
tAA
12
ns
Chip select access time
tACS
12
ns
Output enable to output valid
tOE
6
ns
Byte select to output valid
tBA
6
ns
Output hold from address change
tOH
3
ns
Chip select to output in low-Z
tCLZ
3
ns
Notes
1
Output enable to output in low-Z
tOLZ
0
ns
1
Byte select to output in low-Z
tBLZ
0
ns
1
Chip deselect to output in high-Z
tCHZ
6
ns
1
Output disable to output in high-Z
tOHZ
6
ns
1
Byte deselect to output in high-Z
tBHZ
6
ns
1
Rev.1.00, Mar.12.2004, page 6 of 13
R1RP0416D Series
Write Cycle
R1RP0416D
-2
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
tWC
12
ns
Address valid to end of write
tAW
8
ns
Chip select to end of write
tCW
8
ns
8
Write pulse width
tWP
8
ns
7
Byte select to end of write
tBW
8
ns
Address setup time
tAS
0
ns
5
Write recovery time
tWR
0
ns
6
Data to write time overlap
tDW
6
ns
Data hold from write time
tDH
0
ns
Write disable to output in low-Z
tOW
3
ns
1
Output disable to output in high-Z
tOHZ
6
ns
1
Write enable to output in high-Z
tWHZ
6
ns
1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or
after the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 13
R1RP0416D Series
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
t RC
Address
Valid address
tAA
tACS
CS#
tOE
tCHZ *1
tBA
tOHZ *1
tBLZ *1
tBHZ *1
OE#
LB#, UB#
tOLZ *1
tOH
tCLZ *1
DOUT
High impedance *4
Rev.1.00, Mar.12.2004, page 8 of 13
Valid data
*4
R1RP0416D Series
Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL)
tRC
Address
Valid address
tOH
tAA
tACS
tCHZ*1
CS#
tOE
tOHZ*1
OE#
tOLZ*1
tCLZ*1
DOUT
High impedance *4
Rev.1.00, Mar.12.2004, page 9 of 13
Valid data
*4
R1RP0416D Series
Write Timing Waveform (1) (WE# Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE#*3
tCW
CS#*3
OE#
tBW
LB#, UB#
tOLZ
tWHZ
tOW
tOHZ
High impedance
DOUT
*2
DIN
Rev.1.00, Mar.12.2004, page 10 of 13
tDW
tDH
Valid data
R1RP0416D Series
Write Timing Waveform (2) (CS# Controlled)
tWC
Valid address
Address
tWR
tAW
tAS
tWP
WE# *3
tCW
CS# *3
OE#
tBW
LB#, UB#
tOLZ
tWHZ
tOW
tOHZ
High impedance *
DOUT
*2
DIN
Rev.1.00, Mar.12.2004, page 11 of 13
tDW
tDH
Valid data
4
R1RP0416D Series
Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH)
tWC
Address
Valid address
tAW
tWR
tWP
WE#*3
tCW
CS#*3
tAS
tBW
UB# (LB#)
tBW
LB# (UB#)
tDW
DIN-UB
(DIN-LB)
tDH
Valid data
tDW
DIN-LB
(DIN-UB)
DOUT
Rev.1.00, Mar.12.2004, page 12 of 13
tDH
Valid data
High impedance
R1RP0416D Series
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Max
Unit
Test conditions
VCC for data retention
VDR
2.0
V
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current
ICCDR
500
µA
VCC = 3 V
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data retention time
tCDR
0
ns
See retention waveform
Operation recovery time
tR
5
ms
Low VCC Data Retention Timing Waveform
t CDR
Data retention mode
V CC
4.5 V
2.2 V
V DR
CS#
0V
Rev.1.00, Mar.12.2004, page 13 of 13
VCC ≥ CS# ≥ VCC − 0.2 V
tR
Revision History
Rev.
Date
R1RP0416D Series Data Sheet
Contents of Modification
Page
Description
0.01
Sep. 30, 2003
Initial issue
1.00
Mar.12.2004
Deletion of Preliminary
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
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circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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