BD8381EFV-M

Power Management ICs for Automotive Body Control LED Drivers for Automotive Light BD8381EFV-M No.11039EAT14 ●Description BD8381EFV-M is a white LED driver with the capability of withstanding high input voltage (50V MAX). A current-mode buck-boost DC/DC controller is also integrated to achieve stable operation against voltage input and also to remove the constraint of the number of LEDs in series connection. The brightness can be controlled by either PWM or DC. The PWM brightness signal generation circuit is built into, and the control without microcomputer is also possible. ●Features 1) Input voltage range 5.0 – 30 V 2) Integrated buck-boost current-mode DC/DC controller 3) Built-in CR timer for PWM brightness 4) PWM linear brightness 5) Built-in protection functions (UVLO, OVP, TSD, OCP, SCP) 6) LED error status detection function (OPEN/ SHORT) 7) HTSSOP-B28 package ●Applications Headlight and running (DRL) of night of daylight, etc. ●Absolute maximum ratings (Ta=25℃) Parameter Power supply voltage BOOT Voltage SW,CS,OUTH Voltage BOOT-SW Voltage VREG,OVP,OUTL,FAIL1,FAIL2,THM,SS, COMP,RT,SYNC,EN,DISC,VTH,FB,LEDR, LEDC,DRLIN, PWMOUT,CT Voltage Power Consumption Operating temperature range Storage temperature range Junction temperature Symbol VCC VBOOT VSW, VCS, VOUTH VBOOT-SW VVREG,VOVP,VOUTL,VFAIL1,VFAIL2,VTHM,VSS, VCOMP,VRT,VSYNCVEN,VDISC,VVTH,VFB,VLEDR, VLEDC, ,VDRLIN,VPWMOUT VCT Pd Topr Tstg Tjmax Ratings 50 55 50 7 -0.3～7 < VCC 1.45※1 -40～+125 -55～+150 150 Unit V V V V V W ℃ ℃ ℃ ※1 IC mounted on glass epoxy board measuring 70mm×70mm×1.6mm, power dissipated at a rate of 11.6mW/℃ at temperatures above 25℃. ※2 A radiation is not designed. ●Operating conditions (Ta=25℃) Parameter Power supply voltage Oscillating frequency range External synchronization frequency range External synchronization pulse duty range ※3 ※4 Symbol VCC FOSC FSYNC FSDUTY Ratings 5.0～30 200～600 fosc～600 40～60 Unit V kHz kHz % ※3 Connect SYNC to GND or OPEN when not using external frequency synchronization. ※4 Do not switch between internal and external synchronization when an external synchronization signal is input to the device. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/20 2011.04 - Rev.A BD8381EFV-M ●Electrical characteristics (Unless otherwise specified, VCC=12V Ta=25℃) Limits Parameter Symbol Min Typ Circuit current Standby current [VREG Block (VREG)] Reference voltage [OUTH Block] OUTH high-side ON resistance OUTH low-side ON resistance Over-current protection operating voltage [OUTL Block] OUTL high-side ON resistance OUTL low –side ON resistance [SW Block] SW low -side ON resistance [PWMOUT Block] PWMOUT high-side ON resistance PWMOUT low-side ON resistance [Error Amplifier Block] Reference voltage COMP sink current COMP source current [Oscillator Block] Oscillating frequency [OVP Block] Over-voltage detection reference voltage OVP hysteresis width [UVLO Block ] UVLO voltage UVLO hysteresis width [PWM Generation circuit Block] VTH Threshold voltage VTH Threshold voltage PWM minimum ON width LED OPEN detection function LED SHORT detection function LED GND short protection timer [Logic Inputs] Input HIGH voltage Input LOW voltage Input current 1 Input current 2 [FAIL Output (open drain) ] FAIL LOW voltage ◎ Technical Note Max. 7.0 8 5.5 7.0 5.0 VCC -0.52 8.0 5.0 9.0 8.0 5.0 Unit mA µA V Ω Ω V Conditions EN=Hi, SYNC=Hi, RT=OPEN, CIN=10µF EN=Low IREG=-5mA，CREG=10µF ION=-10mA ION=10mA ICC IST VREG RONHH RONHL VOLIMIT 4.5 1.5 1.0 VCC -0.68 2.0 1.0 2.0 2.0 1.0 4.5 0 5.0 3.5 2.5 VCC -0.60 4.0 2.5 4.5 4.0 2.5 RONLH RONLL RONSW RONPWMH RONPWML Ω Ω Ω Ω Ω ION=-10mA ION=10mA IONSW=10mA IONPWMH=-10mA IONPWML=10mA FB-COMPShort, Ta=-40℃～125℃ VFB>0.2V, Vcomp=1V VFB GND short protection detection timer.) Rcr1 Rcr2 Ccr 20 10 100000 1.44 (RCR1+2RCR2)CCR RCR2 (RCR1+2RCR2) ×100 kΩ kΩ pF VTH OUTL FPWM= ILED TON_PWM= Fig. 12 ●About time from EN turning on to PWM turning on and the start from PWM low Duty ※The GND short protection detecting function (hereafter, ①SCP timer detection starts SCP) starts with EN=Low→Hi, and after the time of the timer set with the external capacitor connected with CT, it EN becomes latch off. (Above figure ① and ②) ②Time of SCP timer The charge with SS begins synchronizing with turning on EN. The PWM latch off function is built into when there is ③Time until turning on PWM not PWM turning on, and when the PWM latch off is PWM detected, (② of SS and the SCP counter) is reset. (The time of the timer at latch OFF is calculated by oscillatory frequency ×32770 counts of DC/DC. ) Therefore, the ④Time of PWM latch timer ⑤Time until switching starts after inputting PWM following relations exist at time until PWM is turned on, time of PWM latch timer and SCP detection time after EN COUP is turned on at external brightness. (However, after ③ is turned on, ③ IL_MAX Feedback the value of L 3. Select the value of L such that 0.05[V/µs] < Vout *RCS < 0.3[V/ µs] L 4. Select coil, schottky diodes, MOSFET and RCS which meet with the ratings 5. Select the output capacitor which meets with the ripple voltage requirements 6. Select the input capacitor 7. Work on with the compensation circuit 8. Work on with the Over-Voltage Protection (OVP) setting 9. Work on with the soft-start setting 10. Verify experimentally www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/20 2011.04 - Rev.A BD8381EFV-M Technical Note 1. Computation of the Input Peak Current and IL_MAX ①Calculation of the maximum output voltage (Vout_max) To calculate the Vout_max, it is necessary to take into account of the VF variation and the number of LED connection in series. ΔVF: VF Variation N: Number of LED connection in series Vout_max = (VF + ΔVF) × N + 0.2+ RPWMON×Iout RPWMON: PWMOUT FET Ron ②Calculation of the output current Iout D: FB standard voltage variation 0.2V Iout= M: Output current resistance variation RISET ③Calculation of the input peak current IL_MAX IL_MAX = IL_AVG + 1/2ΔIL IL_AVG = (VIN + Vout) × Iout / (n × VIN) ΔIL= VIN L × 1 Fosc × Vout VIN+Vout n: efficiency Fosc: switching frequency ・The worst case scenario for VIN is when it is at the minimum, and thus the minimum value should be applied in the equation. ・ The L value of 10µH  47µH is recommended. The current-mode type of DC/DC conversion is adopted for BD8381EFV-M, which is optimized with the use of the recommended L value in the design stage. This recommendation is based upon the efficiency as well as the stability. The L values outside this recommended range may cause irregular switching waveform and hence deteriorate stable operation. ・n (efficiency) is approximately 80% VIN IL Rcs CS M1 L D2 Vout M2 D1 Co Fig.21 External Application Circuit 2. The setting of over-current protection Choose Rcs with the use of the equation Vocp_min (=0.54V) / Rcs > IL_MAX When investigating the margin, it is worth noting that the L value may vary by approximately ±30%. 3. The selection of the L In order to achieve stable operation of the current-mode DC/DC converter, we recommend selecting the L value in the range indicated below: 0.05 [V/µs] < The smaller Vout×Rcs < 0.3 [V/µs] L Vout×Rcs allows stability improvement but slows down the response time. L Current rating Coil L Diode D1 Diode D2 MOSFET M1 MOSFET M2 Rcs ※ ※ 4. Selection of coil L, diode D1 and D2, MOSFET M1 and M2, and Rcs Voltage rating ― > VIN_MAX > Vout > VIN_MAX > Vout ― > Iocp2 × Rcs Heat loss > IL_MAX > Iocp > Iocp > Iocp > Iocp ― Allow some margin, such as the tolerance of the external components, when selecting. In order to achieve fast switching, choose the MOSFETs with the smaller gate-capacitance. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 12/20 2011.04 - Rev.A BD8381EFV-M 5. Selection of the output capacitor Select the output capacitor Cout based on the requirement of the ripple voltage Vpp. Vpp = Iout × Cout Vout × Vout+VIN 1 Fosc + IL_MIN × RESR Technical Note Choose Cout that allows the Vpp to settle within the requirement. Allow some margin also, such as the tolerance of the external components. 6.Selection of the input capacitor A capacitor at the input is also required as the peak current flows between the input and the output in DC/DC conversion. We recommend an input capacitor greater than 10µF with the ESR smaller than 100m. The input capacitor outside of our recommendation may cause large ripple voltage at the input and hence lead to malfunction. 7. Phase Compensation Guidelines In general, the negative feedback loop is stable when the following condition is met:  Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more) However, as the DC/DC converter constantly samples the switching frequency, the gain-bandwidth (GBW) product of the entire series should be set to 1/10 the switching frequency of the system. Therefore, the overall stability characteristics of the application are as follows:  Overall gain of 1 (0dB) with a phase lag of less than 150º (i.e., a phase margin of 30º or more)  GBW (frequency at gain 0dB) of 1/10 the switching frequency Thus, to improve response within the GBW product limits, the switching frequency must be increased. The key for achieving stability is to place fz near to the GBW. GBW is decided by phase delay fp1 by COUT and output impedance RL. Of each becomes like the next expression. Vout 1 Phase-lead fz = [Hz] 2πCpcRpc 1 Phase-lag fp1 = [Hz] 2πRLCout LED FB A COMP Rpc Cpc Good stability would be obtained when the fz is set between 1kHz～10kHz. Please substitute the value at the maximum load for RL. In buck-boost applications, Right-Hand-Plane (RHP) Zero exists. This Zero has no gain but a pole characteristic in terms of phase. As this Zero would cause instability when it is in the control loop, so it is necessary to bring this zero before the GBW. fRHP= Vout+VIN/(Vout+VIN) 2πILOADL [Hz] ILOAD: MAXIMUM LOAD CURRENT It is important to keep in mind that these are very loose guidelines, and adjustments may have to be made to ensure stability in the actual circuitry. It is also important to note that stability characteristics can change greatly depending on factors such as substrate layout and load conditions. Therefore, when designing for mass-production, stability should be thoroughly investigated and confirmed in the actual physical design. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 13/20 2011.04 - Rev.A BD8381EFV-M Technical Note 8. Setting of the soft-start The soft-start allows minimization of the coil current as well as the overshoot of the output voltage at the start-up. For the capacitance we recommend in the range of 0.001  0.1µF. For the capacitance less than 0.001µF may cause overshoot of the output voltage. For the capacitance greater than 0.1µF may cause massive reverse current through the parasitic elements of the IC and damage the whole device. In case it is necessary to use the capacitance greater than 0.1µF, ensure to have a reverse current protection diode at the Vcc or a bypass diode placed between the SS-pin and the Vcc. Soft-start time TSS TSS = CSSX0.7V / 5uA [s] CSS: The capacitance at the SS-pin 9. Verification of the operation by taking measurements The overall characteristic may change by load current, input voltage, output voltage, inductance, load capacitance, switching frequency, and the PCB layout. We strongly recommend verifying your design by taking the actual measurements. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/20 2011.04 - Rev.A BD8381EFV-M ●Power consumption calculation Pc(N) = ICC*VCC + 1 2 Technical Note *Ciss*VREG*Fsw*VREG×2×2+ 1 2 ×Ciss×VREG×FPWM×VREG×2 ICC ： Current of the maximum circuit VCC ：Power-supply voltage Ciss ： External FET capacity Vsw ： SW gate voltage Fsw ： SW frequency FPWM ： PWM frequency ＜Calculation example＞ When assuming Pc(4) = 10mA × 30V + 500pF × 5V × 300kHz × 5V×2×2+ it becomes Pc = about 300mW. 4 (1) θja=66.5℃/W (Density of board copper foil3%) (3) 3.12W 3 (2) 2.77W 1 2 ×1500pF×5×200×5×2, Pd[Ｗ] (2) θja=45℃/W (Density of board copper foil34%) (3) θja=40℃/W (Density of board copper foil60%) Power Consumption 2 (1) 1.88W 1 0 25 50 75 95 100 125 150 Ambient temperature Ta[℃] Fig.22 Note1: The value of Power consumption : on glass epoxy board measuring 70mm×70mm×1.6mm (1 layer board/Copper foil thickness 18µm) Note2: The value changes depending on the density of the board copper foil. However, this value is an actual measurement value and no guarantee value. Pd=2200mW (968mW) ： Density of the board copper foil 3% Pd=3200mW (1408mW)： Density of the board copper foil 34% Pd=3500mW (1540mW)： Density of the board copper foil 60% The value in () is a Power consumption of the Ta=125℃. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 15/20 2011.04 - Rev.A BD8381EFV-M ●Application circuit 1 Vin VREG FAIL1 OVP UVLO VCC VREG TSD OVP OCP CS COUT Technical Note EN PWM Timer Latch Control Logic BOOT OUTH DRV CTL SW DGND VREG OUTL ERR AMP GND + SYNC OSC RT SLOPE PWM COMP OCP OVP SS VREG + LEDR SHORT Det LEDC SS PWMOUT THM INP1 INP2 DRLIN OPEN/ SHORT/ SCP Detect DISC VTH CR TIMER Open Det Timer Latch SCP Det FAIL2 FB VREG PGND CT Fig. 23 Buck application composition (It is INP1, INP2, and two input selector function. ) ●Application circuit 2 Vin VREG FAIL1 OVP UVLO VCC VREG TSD OVP OCP CS COUT EN PWM Timer Latch Control Logic BOOT OUTH DRV CTL SW DGND VREG OUTL ERR AMP GND + SYNC OSC RT SLOPE PWM COMP OCP OVP SS VREG + LEDR SHORT Det LEDC SS PWMOUT THM FB VREG DRLIN OPEN/ SHORT/ SCP Detect DISC VTH CR TIMER Open Det Timer Latch SCP Det FAIL2 PGND CT Fig. 24 Boost application composition (When invalidating short detection. ) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 16/20 2011.04 - Rev.A BD8381EFV-M ●Input/output Equivalent Circuits Technical Note 1. COMP VREG VREG 2. SS VREG VCC 4. EN EN COMP SS 5. RT VREG VREG VREG 6. SYNC 8. THM VCC RT SYNC 9. FB 10. DISC VREG VCC DISC 11. VTH VREG FB VTH 12. DRLIN VCC 13,14. FAIL1,FAIL2 15. OVP VCC DRLIN FAIL1 FAIL2 OVP ※The values are all Typ. value. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 17/20 2011.04 - Rev.A BD8381EFV-M ●Input/output Equivalent Circuits(Continuation) Technical Note 16,17. LEDC, LEDR 19,22. PWMOUT, OUTL 20. CT VREG VREG LEDC LEDR VREG CT 24. SW 25. OUTH BOOT VCC BOOT 26. CS SW OUTH CS SW SW SW 27. BOOT 28. VREG VREG VCC VREG BOOT VREG ※The values are all Typ. value. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 18/20 2011.04 - Rev.A BD8381EFV-M Technical Note ●Notes for use 1. Absolute maximum ratings We are careful enough for quality control about this IC. So, there is no problem under normal operation, excluding that it exceeds the absolute maximum ratings. However, this IC might be destroyed when the absolute maximum ratings, such as impressed voltages or the operating temperature range(Topr), is exceeded, and whether the destruction is short circuit mode or open circuit mode cannot be specified. Please take into consideration the physical countermeasures for safety, such as fusing, if a particular mode that exceeds the absolute maximum rating is assumed. 2. Reverse polarity connection Connecting the power line to the IC in reverse polarity (from that recommended) will damage the part. Please utilize the direction protection device as a diode in the supply line. 3. Power supply line Due to return of regenerative current by reverse electromotive force, using electrolytic and ceramic suppress filter capacitors (0.1µF) close to the IC power input terminals (Vcc and GND) are recommended. Please note the electrolytic capacitor value decreases at lower temperatures and examine to dispense physical measures for safety. And, for ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, width of power wiring, GND wiring, and routing of wiring. Please make the power supply lines (where large current flow) wide enough to reduce the resistance of the power supply patterns, because the resistance of power supply pattern might influence the usual operation. 4. GND line The ground line is where the lowest potential and transient voltages are connected to the IC. 5. Thermal design Do not exceed the power dissipation (Pd) of the package specification rating under actual operation, and please design enough temperature margins. 6. Short circuit mode between terminals and wrong mounting Do not mount the IC in the wrong direction and be careful about the reverse-connection of the power connector. Moreover, this IC might be destroyed when the dust short the terminals between them or power supply, GND. 7. Radiation Strong electromagnetic radiation can cause operation failures. 8. ASO(Area of Safety Operation.) Do not exceed the maximum ASO and the absolute maximum ratings of the output driver. 9. TSD(Thermal shut-down) The TSD is activated when the junction temperature (Tj) reaches 175℃(with 25℃ hysteresis), and the output terminal is switched to Hi-z. The TSD circuit aims to intercept IC from high temperature. The guarantee and protection of IC are not purpose. Therefore, please do not use this IC after TSD circuit operates, nor use it for assumption that operates the TSD circuit. 10. Inspection by the set circuit board The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge electricity in each and all process. Moreover, in the inspection process, please turn off the power before mounting the IC, and turn on after mounting the IC. In addition, please take into consideration the countermeasures for electrostatic damage, such as giving the earth in assembly process, transportation or preservation. 11. IC terminal input + This IC is a monolithic IC, and has P isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in this P-layer and N-layer of each element. For instance, the resistor or the transistor is connected to the terminal as shown in the figure below. When the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GND(P substrate). Please do not apply the voltage to the input terminal when the power-supply voltage is not impressed. Moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage is impressing. Resistor Terminal-A Terminal-A Terminal-B C B E B Parasitic element C E P+ P P+ Surrounding elements Parasitic element GND Parasitic element GND Parasitic element GND GND Transistor(NPN) Terminal-B P+ P P+ P-Substrate P-Substrate structure of IC 12. Earth wiring pattern Use separate ground lines for control signals and high current power driver outputs. Because these high current outputs that flows to the wire impedance changes the GND voltage for control signal. Therefore, each ground terminal of IC must be connected at the one point on the set circuit board. As for GND of external parts, it is similar to the above-mentioned www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 19/20 2011.04 - Rev.A BD8381EFV-M ●Ordering part number Technical Note B Part No. D 8 Part No. 3 8 1 E F V -M E 2 Package EFV: HTSSOP-B28 for Packaging and forming specification Automotive E2: Embossed tape and reel HTSSOP-B28 9.7±0.1 (MAX 10.05 include BURR) (5.5) 28 15 Tape +6° 4° −4° 0.5±0.15 1.0±0.2 Embossed carrier tape (with dry pack) 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold Quantity Direction of feed 6.4±0.2 4.4±0.1 (2.9) ( reel on the left hand and you pull out the tape on the right hand ) 1 14 0.625 1.0MAX 1PIN MARK S +0.05 0.17 -0.03 0.85±0.05 0.08±0.05 0.08 S 0.65 +0.05 0.24 -0.04 0.08 M 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 20/20 2011.04 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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