BD9897FS-E2

1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE ＢＤ９８９７ＦＳ FUNCTION ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 36V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin Synchronous operating the other BD9897FS IC’s BURST mode controlled by PWM and DC input Output liner Control by external DC voltage ○Absolute Maximum Ratings（Ta = 25℃） Parameter Supply Voltage BST pin SW pin BST-SW voltage difference Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation * Symbol Limits Unit VCC 36 V BST 40 V SW 36 V BST-SW 7 V Topr -40～+85 ℃ Tstg -55～+150 ℃ Tjmax +150 ℃ Pd 950* mW Pd derate at 7.6mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇Operating condition Parameter Supply voltage BST voltage BST-SW voltage difference CT oscillation frequency BCT oscillation frequency Symbol Limits Unit VCC 7.5～30.0 V BST 4.0～36.0 V BST-SW 4.0～6.5 V fCT 60～180 kHz fBCT 0.05～1.00 kHz Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of REV. B this document, official version takes priority. 2/4 ○ Electric Characteristics（Ta=25℃，VCC=24V） Parameter （（WHOLE DEVICE）） Operating current Symbol Limits TYP. MIN. MAX. Unit Conditions Icc1 － 7.2 13 mA Icc2 － 13.0 30.0 μA VstH VstL 2.0 -0.3 － － VCC 0.8 V V VuvloH ⊿VCC_Vuvlo Vuvlo2 ⊿Vuvlo 5.7 0.26 2.179 0.074 6.0 0.35 2.25 0.098 6.3 0.43 2.321 0.122 V V V V VREG IREG 5.68 20.0 5.80 － 5.92 － V mA Iact Ineg VOSCH 1.35/(RT*7) Iact×29 1.8 1.5/(RT*6) Iact×35 2.0 1.65/(RT*5) Iact×41 2.2 A A V fCT=120kHz OSC Min voltage Soft start current SRT ON resistance （（BOSC BLOCK）） VOSCL 0.35 0.45 0.60 V fCT=120kHz ISS RSRT 0.6 － 1.1 100 1.6 200 μA Ω BOSC Max voltage VBCTH 1.94 2.00 2.06 V BOSC Min voltage BOSC constant current VBCTL 0.40 0.50 0.60 V fBCT=0.3kHz IBCT 1.35/BRT 1.5/RT 1.65/RT A VBCT=0.2V BOSC frequency （（FEED BACK BLOCK）） fBCT 291 300 309 Hz (BRT=33kΩ BCT=0.048μF) IS threshold voltage 1 VIS① 1.225 1.250 1.275 V IS threshold voltage 2 VIS② － VREFIN VIS① V VVS 1.220 1.250 1.280 V IIS1 IIS2 IVS VISCOMP① VISCOMP② VREFIN － 32 － 0.90 － 0.6 － 50 － 0.94 VREFIN×0.73 － 0.9 68 0.9 0.98 － 1.6 μA μA μA V V V VDUTY-OUTH VDUTY-OUTL RDUTY-OUTSink RDUTY-OUTSouce 2.8 － － － 3.1 150 250 3.4 0.5 300 500 V V Ω Ω RsinkLN RsourceLN RsinkHN RsourceLN MAX DUTY TOFF FOUT 0.75 2.5 1.25 2.5 46.0 100 58.5 1.5 5 2.5 5 48.0 200 60.0 3.0 10 5.0 10 49.5 400 61.5 Ω Ω Ω Ω % ns kHz VCP ICP 1.94 0.40 2.0 0.55 2.06 0.70 V μA VCOMPH VCOMP2_H VCOMP_L_1 VCOMP_L_2 2.460 2.460 1.225 0.606 2.485 2.485 1.25 0.625 2.510 2.510 1.275 0.644 V V V V VCT_SYNCH 2.8 3.1 3.4 V VCT_SYNCL － － 0.5 V RCT_SYNC_SYNC RCT_SYNC_SOURCE VCT_SYNC_IN_H VCT_SINK_IN_L － － 2.0 -0.3 150 370 － － 300 740 3.3 0.6 Ω Ω V V Stand-by current （（STAND BY CONTROL）） Stand-by voltage H Stand-by voltage L （（UVLO BLOCK））） Operating voltage (VCC) Hesteresis width (VCC) Operating voltage (UVLO) Hesteresis width (UVLO) （（REG BLOCK）） REG output voltage REG source current （（OSC BLOCK）） Active edge setting current Negative edge setting current OSC Max voltage VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage ① IS COMP detect voltage ② VREF input voltage range （（DUTY BLOCK）） High voltage Low voltage DUTY-OUT sink resistance DUTY-OUT source resistance （（OUTPUT BLOCK）） LN output sink resistance LN output source resistance HN output sink resistance HN output source resistance MAX DUTY OFF period Drive output frequency （（TIMER LATCH BLOCK）） Timer Latch setting voltage Timer Latch setting current （（COMP CLOCK）） COMP1 over voltage detect voltage COMP2 over voltage detect voltage COMP2 under voltage detect voltage ① COMP2 under voltage detect voltage ② ((Synchronous Block)) High voltage Low voltage CT_SYNC sink resistance CT_SYNC source resistance High voltage input range Low voltage input range （This product is not designed to be radiation-resistant.） REV. B CT_SYNC_IN = OPEN System ＯＮ System ＯＦＦ VCC>7.0V fBCT=0.3kHz VREF applying voltage DUTY=2.2V DUTY=0V IS=0.5V VREFIN≧1.25V VREFIN＜1.25V No effect at VREF＞1.25V VBST-VSW=5.0V VBST-VSW=5.0V FOUT=60kHz (RT=4.7kΩ CT=235pF) VSS＞2.2V VSS＞2.2V VSS＞2.2V VSS＜2.2V 3/4 〇Package Dimensions 〇Pin Description Device Mark BD9897FS Lot No. SSOP-A32 (Unit：mm) 〇Block Diagram REV. B PIN No. PIN NAME 1 PGND Ground for FET drivers 2 LN2 NMOS FET driver 3 HN2 NMOS FET driver 4 SW2 Lower rail voltage for HN2 output 5 BST2 Boot-Strap input for HN2 output 6 CT_SYNC_IN CT synchronous signal input pin 7 CT_SYNC_OUT CT synchronous signal output pin 8 SRT 9 RT 10 CT 11 GND 12 BCT FUNCTION External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External capacitor from CT to GND for adjusting the triangle oscillator GROUND External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from BRT to GND for adjusting the BURST triangle oscillator 13 BRT 14 DUTY 15 DUTY_OUT 16 STB Stand-by switch 17 CP External capacitor from CP to GND for Timer Latch 18 FAIL COMP2 under voltage protect clock output 19 VREF Reference voltage input pin for Error amplifier 20 VS Error amplifier input 21 IS Error amplifier input 22 FB Error amplifier output 23 SS External capacitor from SS to GND for Soft Start Control 24 COMP2 Under, over voltage detect pin 25 COMP1 Over voltage detect pin 26 VCC Supply voltage input 27 UVLO External Under Voltage Lock Out 28 REG Internal regulator output 29 BST1 Boot-Strap input for HN1 output 30 SW1 Lower rail voltage for HN1 output 31 HN1 NMOS FET driver 32 LN1 NMOS FET driver Control PWM mode and BURST mode BURST signal output pin 4/4 〇NOTE FOR USE １. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. ２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. ３. Mounting failures, such as misdirection or miscounts, may harm the device. ４. A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin. ６. BD9897FS incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. ７. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. ９. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. １０. By STB voltage, BD9897FS are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～2.0V). １１. The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. １２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. Transistor (NPN) Resistance (PinA) (PinB) B E C Ｃ GND P P＋ N P＋ N Ｎ N Ｎ P substrate GND Parasitic diode N P substrate GND Parasitic diode (PinB) (PinA) B CＣ Ｂ EＥ Parasitic diode GND GND Other adjacent components Parasitic diode Fig-1 Simplified structure of a Bipolar IC REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). 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