BU9897GUL-W

1/4 ◇ STRUCTURE ◇ PRODUCT ◇ PART NUMBER Silicon Monolithic Integrated Circuit I2C BUS 128Kbit (16,384×8bit) EEPROM BU9897GUL-W PACKAGE VCSP50L2 PART NUMBER BU9897GUL-W ◇FEATURES Two wire serial interface Wide operating voltage range (1.7V～5.5V) Endurance : 1,000,000 erase/write cycles ◇ ABSOLUTE MAXIMUM RATING (Ta=25℃) Parameter Symbol Rating Supply Voltage Vcc -0.3～6.5 Power Dissipation Pd 220 Storage Temperature Tstg -65～125 Operating Temperature Topr -40～85 Terminal Voltage － -0.3～Vcc+1.0 *1 2.2mW/℃(*1) for operation above 25℃ *2 The Max value of Terminal Voltage is not over 6.5V ◇ RECOMMENDED OPERATING CONDITION Parameter Supply Voltage Input Voltage Symbol Vcc VIN Rating 1.7～5.5 0～Vcc Unit V V Unit V mW ℃ ℃ V *1 *2 REV. B 2/4 ◇MEMORY CELL CHARACTERISTICS (Ta=25℃, Vcc=1.7～5.5V) Specification Parameter Min. Typ. Write/Erase Cycle *1 1,000,000 Data Retention *1 40 ○Initial Data FFh in all address. ◇DC OPERATING CHARACTERISTICS Parameter "H" Input Voltage1 "L" Input Voltage1 "L" Output Voltage1 "L" Output Voltage2 Input Leakage Current Output Leakage Current Symbol Min. VIH1 VIH2 VOL1 VOL2 ILI ILO ICC1 Operating Current ICC2 Standby Current ISB － － － － 0.5 2.0 ｍA μA 0.7Vcc -0.3 － － -1 -1 － Specification Min. － － － － － － － Min. Vcc+1.0 0.3Vcc 0.4 0.2 1 1 2.5 V V V V μA μA mA IOL=3.0mA，2.5V≦Vcc≦ 5.5V（SDA） IOL=0.7mA，1.7V≦Vcc＜ 2.5V（SDA） VIN=0V～Vcc VOUT=0V～Vcc（SDA） Vcc=5.5V,fSCL=400ｋHz， tWR=5ms Byte Write,Page Write Vcc=5.5V,fSCL=400ｋHz Random Read,Current Read,Sequential Read Vcc=5.5V,SDA,SCL=Vcc A0,A1,A2=GND,WP=GND Unit Specification Max. - Unit Cycles Years *1 Not 100% TESTED ◇ AC OPERATING CHARACTERISTICS (Unless otherwise specified Ta=-40～85℃, Vcc=1.7～5.5V) Specification Parameter Clock Frequency Data Clock High Period Data Clock Low Period SDA and SCL Rise Time *1 SDA and SCL Fall Time *1 Start Condition Hold Time Start Condition Setup Time Input Data Hold Time Input Data Setup Time Output Data Delay Time Output Data Hold Time Stop Condition Setup Time Bus Free Time Write Cycle Time Noise Spike Width (SDA and SCL) WP Hold Time WP Setup Time WP High Period Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP Min. － 0.6 1.2 － － 0.6 0.6 0 100 0.1 0.1 0.6 1.2 － － 0 0.1 1.0 Typ. － － － － － － － － － － － － － － － － － － Max. 400 － － 0.3 0.3 － － － － 0.9 － － － 5 0.1 － － － Unit kHz μs Μs Μs Μs Μs μs ns ns μs μs μs μs ns μs ns μs μs *1 Not 100% TESTED ◇BLOCK DIAGRAM A0 B3 14bit ◇PIN No. NAME PIN No. A1 A2 A3 A4 B1 B3 B4 C1 C2 C3 C4 PIN NAME SCL WP Vcc GND SDA A0 GND GND A2 A1 GND 128Kbit EEPROM ARRAY 8bit SLAVE, WORD ADDRESS REGISTER DATA REGISTER A3 Vcc A1 C3 ADDRESS DECODER 14bit A2 WP START STOP A2 C2 CONTROL LOGIC ACK A1 SCL GND C1 HIGH VOLTAGE GEN. VCC LEVEL DETECT B1 SDA Fig.-1 BLOCK DIAGRAM REV. B 3/4 ◇NOTES FOR POWER SUPPLY Vcc rises through the low voltage region in which internal circuit of IC and the controller are unstable, so that device may not work properly due to an incomplete reset of internal circuit. To prevent this, the device has the feature of P.O.R. and LVCC. In the case of power up, keep the following conditions to ensure functions of P.O.R. and LVCC. 1. 2. It is necessary to be "SDA='H'" and "SCL='L' or 'H'". Follow the recommended conditions of tR, tOFF, Vbot for the function of P.O.R. during power up. tR Vcc ◇RECOMMENDED CONDITIONS OF tR, tOFF, Vbot tOFF 0 Vbot Fig.-2 Vcc RISING WAVEFORM 3. Prevent SDA and SCL from being "High-Z". In case that condition 1. and/or 2. cannot be met, take following actions. A） Unable to keep condition 1. ( SDA is "LOW" during power up.) →Control SDA ,SCL to be "HIGH" as Fig.-3(a), 3(b). B）Unable to keep condition 2. →After power becomes stable, execute C）Unable to keep both conditions 1 and 2. →Follow the instruction A first, then the instruction B. Vcc SCL tLOW SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT tSU:DAT Fig.-3（a） SCL='H' and SDA='L' Fig.-3（b） SCL='L' and SDA='L' ◇CAUTIONS ON USE (1) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (2) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND terminal. (3) Thermal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (4) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (5) Use in a strong electromagnetic field may cause malfunction, therefore, evaluated design sufficiently. REV. B 4/4 9897 Lot No. GND SDA SCL A2 A1 A0 GND GND GND WP Vcc The A4, B4, C4 pins are set to GND inside chip. Please set these OPEN. Please don’t connect these GND. Fig.-1 PHYSICAL DIMENSION (UNIT:mm) REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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