BU2506FV

D/A Converter Series for Electronic Adjustments High-precision 10bit 8ch・10ch Type D/A Converters BU2506FV, BU2505FV No.09052EAT03 ●Description BU2506FV and BU2505FV ICs are high performance 10bit R-2R type DACs with 8ch and 10ch outputs, respectively. Cascade connection is possible, ensuring suitability with multi-channel applications. Each channel incorporates a full swing output-type buffer amplifier with high speed output response characteristics, resulting in a greatly shortened wait time. The ICs also utilize the TTL level input method, and with the RESET pin the output voltage can be kept in the lower reference voltage range. ●Features 1) High performance, multi-channel R-2R-type 10bit D/A converter built-in (BU2506FV: 8 channels, BU2505FV: 10 channels) 2) Full swing output type buffer amplifier incorporated at each output channel 3) The RESET terminal can keep the output voltage at all channels within the lower reference voltage range 4) Digital input compatible with TTL levels 5) 14bit 3-line serial data + RESET signal input (address 4bit + data 10bit) 6) Cascade connection available 7) LSB first / MSB first of 10bit data can be changed by the REVERSE terminal 8) Compact package: 0.65mm pitch, 20 pins (SSOP-B20) ●Applications DVDs, CD-Rs, CD-RWs, Digital cameras ●Lineup Parameter Power source voltage range Number of channels Differential non linearity error Integral non linearity error Data transfer frequency Package ●Absolute Maximum Ratings(Ta=25℃) Parameter Power source voltage D/A converter upper standard voltage Input voltage Output voltage Storage temperature range Power dissipation BU2505FV 4.5 to 5.5V 10ch ±1.0LSB ±3.5LSB 10MHz SSOP-B20 BU2506FV 4.5 to 5.5V 8ch ±1.0LSB ±3.5LSB 10MHz SSOP-B20 Symbol VCC VDD VIN VOUT Tstg Pd Limits -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -55 to 125 400* Unit V V V V ℃ mW * Derated at 4mW/℃ at Ta>25℃, mounted on a 70x70x1.6mm FR4 glass epoxy board (copper foil area less than 3%) Note: These products are not robust against radiation ●Recommended Operating Conditions(Ta=25℃) Parameter Symbol Power supply voltage range Operating temperature range VCC Topr Limits 4.5 to 5.5 -30 to 85 Unit V ℃ www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 1/8 2009.06 - Rev.A BU2506FV,BU2505FV Technical Note ●Electrical Characteristics(Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃) Limits Parameter Symbol Unit Conditions MIN. TYP. MAX. Power source current ICC 0.85 2.8 mA At CLK=10MHz, IAO=0μA Input leak current IILK -5 5 μA VIN=0 to VCC Input voltage L VIL 0.8 V Input voltage H VIH 2.0 V Output voltage L VOL 0 0.4 V IOL=2.5mA Output voltage H VOH 4.6 5 V IOH=-2.5mA 4.5 7.5 mA Consumption current IrefH Data condition : at maximum current 3.7 6.2 mA(*1) D/A converter upper standard voltage Outputs are not necessarily within VrefH 3.0 5 V setting range the standard voltage setting range, but ARE within the buffer amplifier D/A converter lower standard voltage VrefL 0 1.5 V output voltage range (VO). setting range 0.1 4.9 IO=±100μA Buffer amplifier output voltage range VO V 0.2 4.75 IO=±1.0mA Upper saturation voltage =0.35V Buffer amplifier output drive range IO -2 2 mA Lower saturation voltage =0.23V Differential non-linearity error DNL -1.0 1.0 VrefH =4.796V LSB Integral non-linearity error INL -3.5 3.5 VrefL=0.7V Precision VCC=5.5V (4mV/LSB) Zero point error SZERO -25 25 mV At no load (IO=+0mA ) Full scale error SFULL -25 25 Buffer amplifier output impedance RO 5 15 Ω Input voltage 0V Pull-up I/O internal resistance value Rup 12.5 25 37.5 kΩ (Resistance value changes according to voltage supplied) *1 Value in the case where CH1 ~ CH8 are set to maximum current ●Timing Characteristics(Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃) Limits Conditions Parameter Symbol Unit MIN. TYP. MAX. Judgment level is 80% / 20% of VCC. Reset L pulse width tRTL 50 Clock L pulse width tCKL 50 Clock H pulse width tCKH 50 Clock rise time tcr 50 Clock fall time tcf 50 Data setup time tDCH 20 nS Data hold time tCHD 40 Load setup time tCHL 50 Load hold time tLDC 50 Load H pulse width tLDH 50 Data output delay time tDO 90 CL=100pF CL≦1000pF, VO:0.5V⇔4.5V . DA output settling time tLDD 7 20 μS Until output becomes the final value 1/2LSB RESET tRTL CLK tCKL DI tLDH LD DA OUTPUT tDo DO OUTPUT tDCH tCHD tCHL tLDD tLDC tcr tCKH tcf www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 2/8 2009.06 - Rev.A BU2506FV,BU2505FV Technical Note ●Cascade Connection A cascade connection data output terminal (DO) is available for reducing the design load when the number of channels is increased. The DO terminal can be connected directly to the data input terminal (DI) of the next stage. Its effectiveness increases as the number of channels increases.The data transition timing is as shown below. DO LD CLK DI BU2505FV (* 2) CPU LD CLK DI DO LD CLK DI BU2505FV (* 1) CLK DI Data of #1 LD DO Data of #2 In a cascade connection, in order to have sufficient data change and clock edge time margins, make the clock line the shortest. ●Block Diagrams BU2505FV VDD (VrefH) BU2506FV VDD (VrefH) VSS (VrefL) AO3 AO4 AO5 Reverse Reset AO6 AO7 AO8 VCC VCC 11 10 11 TEST1 AO9 AO8 D/A D/A D/A 12 12 9 9 8 TEST2 AO10 AO7 D/A D/A 8 D/A 13 13 8 7 10 AO6 DO DO D/A 7 D/A 14 14 7 Address decoder 6 ・・・ D13 D13 D10 11 12 Reset 14bit Shift register 14bit Shift register D10 11 12 LD LD 15 15 6 Address decoder ・・・ 6 D9 Reverse 8 CLK CLK 7 16 16 6 5 6 7 8 D9 5 4 3 2 1 D0 AO5 D/A D0 1 2 3 4 5 D/A 17 17 DI DI 4 5 AO1 AO4 AO1 D/A D/A D/A 5 D/A 18 18 3 4 1 10bit Latch 10bit Latch 1 10bit Latch 10bit R-2R DA converter 10bit Latch 4 10bit R-2R DA converter 10bit R-2R DA converter 10bit R-2R DA converter AO2 AO3 AO2 ・・・ 19 19 2 ・・・ Ch2 Ch3 Ch2 Ch3 Buffer operation amplifier VSS (VrefL) GND GND 20 20 1 Buffer operation amplifier www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 3/8 2009.06 - Rev.A 1 2 3 L L L L 4 L L 5 6 7 L L 8 L L L 9 L L L 10 BU2506FV,BU2505FV ●Terminal Descriptions No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name VSS AO3 AO4 AO5 Reverse Reset AO6 AO7 AO8 VDD VCC AO9(TEST1) AO10(TEST2) DO LD CLK DI AO1 AO2 GND Analog / Digital Analog Analog Analog Analog Digital Digital Analog Analog Analog Analog Analog Analog Digital Digital Digital Digital Analog Analog I/O O O O I I O O O O O O I I I O O Description DA converter lower standard voltage (VrefL) input terminal 10bit D/A output(CH3) 10bit D/A output(CH4) 10bit D/A output(CH5) Technical Note Equivalent Circuit 6 4 4 4 2 2 4 4 4 5 4 4 3 1 1 1 4 4 - The reverse LSB and MSB of data designation 10bit in 14bit. All ch analog output L fixed 10bit D/A output(CH6) 10bit D/A output(CH7) 10bit D/A output(CH8) DA converter upper standard voltage (VrefH) input terminal Power source terminal 10bit D/A output(CH9) (BU2506FV : test terminal) 10bit D/A output(CH10) (BU2506FV : test terminal) This outputs bit data of LSB of 14bit shift register. LD terminal. When High level is input, the value of 14bit shift register is loaded to decoder and D/A output register. Shift clock input terminal. At rise of shift clock, the signal from DI terminal is input to 14bit shift register. Serial data input terminal. Serial data whose data length is 14bit (address 4bit + data 10bit) is input. 10bit D/A output(CH1) 10bit D/A output(CH2) GND terminal *In the case of BU2506FV, be sure to leave the TEST1 and TEST2 terminals open www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 4/8 2009.06 - Rev.A BU2506FV,BU2505FV ●Command Transmission 1) Reverse = open (or VCC short-circuit) setting (Data: LSB first) (1) Data format Last MSB Ｄ13 Ｄ12 Ｄ11 Ｄ10 Ｄ9 Ｄ8 Ｄ7 Ｄ6 Ｄ5 Ｄ4 Ｄ3 Ｄ2 Ｄ1 First LSB Ｄ0 For address selection ｱﾄﾞﾚｽ選択用 Technical Note Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用 For D/A converter output setting (2) Data timing diagram DI CLK LD DA OUTPUT LSB D0 D1 D2 D3 D11 D12 MSB D13 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 : 1 1 D5 0 0 1 1 : 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 0 1 0 1 : 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 : : : : : 1 1 1 1 1 1 1 1 1 1 2) Reverse = L setting(Data: MSB first ) (1) Data format Last MSB Ｄ4 Ｄ5 Ｄ6 Ｄ7 Ｄ8 Ｄ9 Ｄ10 Ｄ11 Ｄ12 Ｄ13 D8 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL First LSB Ｄ3 Ｄ2 Ｄ1 Ｄ0 For D/A converter output setting Ｄ／Ａｺﾝﾊﾞｰﾀ出力設定用 For ｱﾄﾞﾚｽ選択用 address selection (2) Data timing diagram DI CLK LD DA OUTPUT LSB D0 D1 D2 D3 D11 D12 MSB D13 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 0 0 0 0 : 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address selection Inconsequential AO1 selection AO2 selection AO3 selection AO4 selection AO5 selection AO6 selection AO7 selection AO8 selection AO9 selection*1 AO10 selection*1 Inconsequential Inconsequential Inconsequential Inconsequential Inconsequential D13 0 1 0 1 : 0 1 D12 0 0 1 1 : 1 1 D11 0 0 0 0 : 1 1 D10 0 0 0 0 : 1 1 D9 0 0 0 0 : 1 1 D8 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A output (VrefH=VDD, VrefL=VSS) VrefL (VrefH-VrefL)/1024×1+VrefL (VrefH-VrefL)/1024×2+VrefL (VrefH-VrefL)/1024×3+VrefL : (VrefH-VrefL)/1024×1022+VrefL (VrefH-VrefL)/1024×1023+VrefL *1 In the BU2506FV, this channel is for testing, therefore, do not designate. www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 5/8 2009.06 - Rev.A BU2506FV,BU2505FV ●Electrical Characteristics Curves 6 Technical Note 6 6 5 5 5 4 4 4 VOUT [V] 3 VOUT [V] VOUT [V] 3 3 2 2 2 1 1 1 0 0 200 400 600 800 1000 1200 0 0 200 400 600 800 1000 1200 0 0 200 400 600 800 1000 1200 Input Code [decimal] Input Code [decimal] Input Code [decimal] Fig.1 Output voltage linearity(-30℃) Fig.2 Output voltage linearity(25℃) Fig.3 Output voltage linearity(85℃) 1.5 40 1.5 1 35 1 0.5 DNL [LSB] 30 0.5 0 DNL [LSB] Rup [kΩ] 25 0 -0.5 20 -0.5 -1 15 -1 - 1.5 0 200 400 600 800 1000 1200 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 -1.5 0 200 400 600 800 1000 1200 Input Code [decimal] Vin [V] Input Code [decimal] Fig.4 Differential linearity error (－30℃) 1.5 Fig.5 Differential linearity error(25℃) 1.5 Fig.6 Differential linearity error(85℃) 1.5 1 1 1 0.5 0.5 0.5 INL [LSB] INL [LSB] 0 0 INL [LSB] 0 200 400 600 800 1000 1200 0 -0.5 -0.5 -0.5 -1 -1 -1 -1.5 0 200 400 600 800 1000 1200 -1.5 -1.5 0 200 400 600 800 1000 1200 Input Code [decimal] Input Code [decimal] Input Code [decimal] Fig.7 Integral linearity error(-30℃) 6 5 code=1FFh Fig.8 Integral linearity error(25℃) 2.52 Fig.9 Integral linearity error(85℃) 40 35 2.51 VOUT [V] ICC [mA] Rup [kΩ] 4 3 2 1 0 -40 code=000h Ta=-30℃ Ta=25℃ Ta=85℃ 30 2.5 25 Ta=25℃ Ta=85℃ 20 2.49 15 Ta=-30℃ code=3FFh 2 .48 -2.5 -1.5 -0.5 0.5 1.5 2.5 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 10 Temp. [ ℃ ] 60 IOUT [mA] Vin [V] Fig.10 Circuit current temperature characteristic Fig.11 Output load fluctuation characteristic (input code : 1FFh) Fig.12 Pull-up built in resistance characteristic www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 6/8 2009.06 - Rev.A BU2506FV,BU2505FV ●Equivalent Circuits Technical Note *1 1 to inside 2 to inside 3 from inside 4 ･ 5 ･ 6 5 4 6 *1 25kΩ at Vcc = 5.0V (changes according to voltage supplied) ●Standard Example Application Circuit V refH VCC AO1 CH1 V refL AO2 CH2 AO3 R everse R eset CH3 C ontroller LD C LK DI A O 10 GND C H 10 ●Operation Notes Ensure that a constant voltage is supplied to each of the 1 ground and 3 power supply terminals. Insert a bypass capacitor between each power supply terminal and ground in order to prevent deterioration of the D/A conversion accuracy due to ripple and noise signals. A capacitor should be inserted between the output and ground in order to eliminate jitter and noise. A capacitance up to 100pF is recommended (including the capacitance of the wire). This IC can select to decode the 10bit DI data pattern using either LSB first or MSB first, depending on the conditions of the REVERSE terminal. Therefore, be sure to stabilize the REVERSE terminal by leaving it open or short-circuiting VDD (LSB first), or short-circuiting GND (MSB first). Inserting a capacitor between the RESET terminal and GND and utilizing a time constant enables power ON reset functionality. Furthermore, when inputting the reset signal from the controller, it is possible to fix the output of all channels to Low at the low area of pulse. www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 7/8 2009.06 - Rev.A BU2506FV,BU2505FV ●Ordering part number Technical Note B U 2 Part No. 2506 2505 5 0 6 F V - E 2 Part No. Package FV: SSOP-B20 Packaging and forming specification E2: Embossed tape and reel SSOP-B20 6.5 ± 0.2 20 11 Tape Quantity 0.3Min. Embossed carrier tape 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold 6.4 ± 0.3 4.4 ± 0.2 Direction of feed ( reel on the left hand and you pull out the tape on the right hand ) 1 10 0.15 ± 0.1 1.15 ± 0.1 0.1± 0.1 0.1 0.65 0.22 ± 0.1 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2009 RzOHM Co., Ltd. All rights reserved. 8/8 2009.06 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. 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