74HC374PW,118

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 The 74HC/HCT374 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive, edge-triggered register • Common 3-state output enable input The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. • Independent register and 3-state buffer operation • Output capability: bus driver When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. • ICC category: MSI GENERAL DESCRIPTION The “374” is functionally identical to the “534”, but has non-inverting outputs. The 74HC/HCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to Qn fmax CI CPD power dissipation capacitance per flip-flop CL = 15 pF; VCC = 5 V 15 13 ns maximum clock frequency 77 48 MHz input capacitance 3.5 3.5 pF 17 17 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 HCT 2 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-state output enable input (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3-state flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge-triggered) 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 FUNCTION TABLE OPERATING MODES INPUTS OUTPUTS OE CP Dn INTERNAL FLIP-FLOPS load and read register L L ↑ ↑ l h L H L H load register and disable outputs H H ↑ ↑ l h L H Z Z Q0 to Q7 Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state ↑ = LOW-to-HIGH CP transition Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Qn 50 18 14 165 33 28 205 41 35 250 50 43 ns 2.0 4.5 6.0 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Qn 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 19 7 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tsu set-up time Dn to CP 60 12 10 14 5 4 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.8 th hold time Dn to CP 5 5 5 −6 −2 −2 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 6.0 30 35 23 70 83 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT OE CP Dn 1.25 0.90 0.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Qn 16 32 40 48 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 16 30 38 45 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to Qn 18 28 35 42 ns 4.5 Fig.7 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 19 11 24 29 ns 4.5 Fig.6 tsu set-up time Dn to CP 12 7 15 18 ns 4.5 Fig.8 th hold time Dn to CP 5 −3 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 26 44 21 17 MHz 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state 74HC/HCT374 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for Dn input. December 1990 7 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 8 74HC/HCT374