LC88F52H0A

Ordering number : ENA1951 LC88F58B0A Overview CMOS LSI FROM 128K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller The SANYO LC88F58B0A is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard programmable), 6K-byte RAM, six 16-bit timers, a base timer serving as a time-of-day clock, two synchronous SIO interfaces with automatic transmission capability, a single master I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a 11-channel 12-bit resolution AD converter, a motor drive signal generator circuit, two multifrequency 12-bit PWM modules, a watchdog timer, a system clock frequency divider, a 40-source (24 modules) 16-vector interrupt feature, and on-chip debugger feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16 registers Flash ROM • Capable of onboard programming with a wide range of voltage levels (3.0 to 5.5V). • Block-erasable in 128 or 1K byte units. • Data written in 2-byte units. • 131072 × 8 bits RAM • 6144 × 8 bits * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.03 41311HKIM 20080924-S00002 No.A1951-1/31 LC88F58B0A Minimum Instruction Cycle Time (tCYC) • 83.3 ns (12MHz) VDD = 4.5 to 5.5V • 100 ns (10MHz) VDD = 3.0 to 5.5V • 500 ns (2MHz) VDD = 2.2 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units : 52 (P0n, P1n, P2n, P30 to P33, P4n, P6n, P70 to P72, PA0 to PA3, PC2) • Oscillation/normal withstand voltage I/O ports : 2 (PC0, PC1) • Oscillation dedicated ports : 2 (CF1, CF2) • Reset pins : 1 (RESB) • TEST pins : 1 (TEST) • Power pins : 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. No.A1951-2/31 LC88F58B0A Serial Interfaces • SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SIO1: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SMIIC0: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • UART0 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 4/8 cycle 6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) 7) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. • UART2 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock : System clock/OSC0/OSC1 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. AD Converter 1) 12/8 bits resolution selectable 2) Analog input: 11 channels 3) Comparator mode 4) Automatic reference voltage generation PWM • PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B) 1) 2-channel pairs controlled independently of one another 2) Clock source selectable from system clock or OSC1 3) 8-bit prescaler: TPWMR0=(prescaler value + 1) × clock period 4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit 5) Fundamental wave PWM mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 High pulse width : 0 to (Fundamental wave period - TPWMR0) 6) Fundamental wave + additional pulse mode Fundamental wave period : 16 TPWMR0 to 256 TPWMR0 Overall period : Fundamental wave period × 16 High pulse width : 0 to (Fundamental wave period - TPWMR0) No.A1951-3/31 LC88F58B0A Watchdog Timer 1) Driven by the base timer + internal watchdog timer dedicated counter 2) Interrupt or reset mode selectable Motor Drive Signal Generator Circuit Interrupts (peripheral function) • 40 sources (24 modules), 16 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Vector Address 08000H 08004H 08008H 0800CH 08010H 08014H 08018H 0801CH 08020H 08024H 08028H 0802CH 08030H 08034H 08038H 0803CH INT1 (1) INT2 (1)/timer 1 (2)/UART2 (4) INT3 (1)/timer 2 (4)/SMIIC0 (1) INT4 (1)/timer 3 (2) INT5 (1)/timer 4 (1)/SIO1 (2) USM0 (3) PWM0 (1) ADC (1)/timer 5 (1) INT6 (1) INT7 (1)/SIO0 (2) Port 0 (3) Watchdog timer (1) Base timer (2) Timer 0 (2) INT0 (1) Interrupt Module • 3 priority levels selectable. • Of interrupts of the same level, the one with the smallest vector address takes precedence. • A number enclosed in parentheses denotes the number of sources. Subroutine Stack: 6K-byte RAM area • Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes • Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/Division Instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) Oscillator Circuits • RC oscillator circuit (internal): For system clock • OSC1 (CF oscillator circuit): For system clock, built-in Rf circuit • OSC0 (crystal oscillator circut): For low-speed system clock • SLRC oscillator circuit (internal): For system clock (exception processing time) System Clock Divider Function • Can run on low current. • 1/1 to 1/128 of the system clock frequency can be set. No.A1951-4/31 LC88F58B0A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not stopped automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC and OSC0 oscillators automatically stop. 2) There are three ways of releasing the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt established at SIO0 or SIO1 (5) Having an interrupt established at UART2 • HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. 1) OSC1 and RC oscillations automatically stop. 2) OSC0 maintains the state that is established when the HOLDX mode is entered. 3) There are four ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at the base timer circuit (5) Having an interrupt established at SIO0 or SIO1 (6) Having an interrupt established at UART2 On-chip Debugger Function • Supports software debugging with the IC mounted on the target board. • Supports source line debugging and tracing functions, and breakpoint setting. • Single-wire communication Package Form • SQFP64 (10×10): Lead-free and halogen-free type Development Tools • On-chip debugger: EOCUIF1 + LC88F58B0A Programming Board Package SQFP64 (10 × 10) Programming Board W88F58SQ Flash Programming Manufacturer Flash Support Group (Single) Flash Support Group (Gang) SANYO Model Name AF9708/09/09B/09C AF9723/23B AF9833 SKK/SKK Type-B Supported Version Revison : After Rev.03.04 Revison : After Rev.02.29 Revison : After Rev.01.90 Revison : After Rev.01.13 LC88F58B0A Device LC88F58B0A LC88F58B0A No.A1951-5/31 LC88F58B0A Package Dimensions unit : mm (typ) 3190A 12.0 48 49 33 32 0.5 10.0 64 1 0.5 (1.25) (1.5) 17 16 0.18 0.15 1.7max 0.1 SANYO : SQFP64(10X10) Pin Assignment PA3/USM0O3 PA2/USM0O2 PA1/USM0O1 PA0/USM0O0 P44/SI1/SB1 P46/PWM0A P47/PWM0B 32 31 30 29 28 27 26 P45/SCK1 PC2/FILT P33/INT3 P40/INT6 P41/INT7 P43/SO1 10.0 12.0 VDD3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P32/INT2 P31/INT1 P30/INT0 TEST RESB PC0/XT1 PC1/XT2 VSS1 CF1 CF2 VDD1 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P65/AN5 2 P66/AN6 3 P67/AN7 4 P20/INT4 5 P21/INT5 6 P22/SM0CK 7 P23/SM0DA 8 P24/SM0DO 9 10 11 12 13 14 15 16 VDD2 VSS2 P27 P00/P0INT P01/P0INT P02/P0INT P25/T4O P26/T5O P72/AN10 P71/AN9 P70/AN8 P17/U2TX P16/U2RX P15/T3OH P14/T3OL/U0RX P13/U0TX P12/SCK0 P11/SI0/SB0 P10/SO0 P07/T0PWMH/U0BRG P06/T0PWML P05/P05INT P04/P04INT P03/P0INT VSS3 P42 LC88F58B0A 25 24 23 22 21 20 19 18 17 Top view SANYO: SQFP64 (10×10) (Lead-free and halogen-free type) No.A1951-6/31 LC88F58B0A System Block Diagram RC Base timer X’tal Low speed RC Watchdog timer Clock generator CF FLASH ROM Timer 0 RAM Timer 1 Xstromy16 CPU On-chip debugger Timer 2 Port 0 Timer 3 Port 1 Timer 4 Port 2 Timer 5 Port 3 SIO0 Port 4 SIO1 Port 6 SMIIC0 Port 7 UART0 Port A UART2 Port C PWM0 INT0 to INT7 Motor control signal generator AD No.A1951-7/31 LC88F58B0A Pin Description Pin Name VSS1, VSS2, VSS3 VDD1, VDD2, VDD3 Port 0 P00 to P07 I/O - Power sources Description I/O + Power sources • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • HOLD release input (P00 to P03, P04, P05) • Port 0 interrupt input (P00 to P03, P04, P05) • Pin functions P06: Timer 0L output P07: Timer 0L output/UART0 clock input Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/pulse input/output P12: SIO0 clock input/output P13: UART0 transmit P14: Timer 3L output/UART0 receive P15: Timer 3H output P16: UART2 receive P17: UART2 transmit Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P22: SMIIC0 clock input/output P23: SMIIC0 bus input/output/data input P24: SMIIC0 data output (used in 3-wire SIO mode) P25: Timer 4 output P26: Timer 5 output Interrupt acknowledge type INT4, INT5: H level, L level, H edge, L edge, both edges Port 3 P30 to P33 I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P30: INT0 input/HOLD release/timer 2L capture input P31: INT1 input/HOLD release/timer 2H capture input P32: INT2 input/HOLD release/timer 2 event input/timer 2L capture input P33: INT3 input/HOLD release/timer 2 event input/timer 2H capture input Interrupt acknowledge type INT0 to INT3: H level, L level, H edge, L edge, both edges Continued on next page. No.A1951-8/31 LC88F58B0A Continued from preceding page. Pin Name Port 4 P40 to P47 I/O I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P40: INT6 input/HOLD release input P41: INT7 input/HOLD release input P43: SIO1 data output P44: SIO1 data input/bus input/output P45: SIO1 clock input/output P46: PWM00 output P47: PWM01 output Interrupt acknowledge type INT6, INT7: H level, L level, H edge, L edge, both edges Port 6 P60 to P67 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN0 (P60) to AN7 (P67): AD converter input port Port 7 P70 to P72 I/O • 3-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN8 (P70) to AN10 (P72): AD converter input port Port A PA0 to PA3 I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Multiplexed pin functions PA0: USM0 output 0 PA1: USM0 output 1 PA2: USM0 output 2 PA3: USM0 output 3 Port C PC0 to PC2 I/O • 3-bit I/O port (on output: Nch-open drain (PC0 to PC1), CMOS (PC2)) • I/O specifiable in 1-bit units • Pin functions PC0: 32.768kHz crystal oscillator input PC1: 32.768kHz crystal oscillator output PC2: FILT TEST I/O • TEST pin • Used to communicate with on-chip debugger. • Connects an external 100kΩ pull-down resistor. RESB CF1 CF2 I I O Reset pin Ceramic oscillator input pin Ceramic oscillator output pin Description No.A1951-9/31 LC88F58B0A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P60 to P67 P70 to P72 PA0 to PA3 PC2 PC0 PC1 CMOS N-channel open drain (32.768kHz crystal oscillator input) N-channel open drain (32.768kHz crystal oscillator output) None None 2 N-channel open drain Option Selected in Units of 1 bit Option Type No. 1 CMOS Output Type Pull-up Resistor Programmable * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2 and VSS3 pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. LSI Power supply For buckup VDD1 PC2/FILT VDD2 + VDD3 VSS1 VSS2 VSS3 1k Ω 2.2μF Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. LSI Power supply For buckup VDD1 PC2/FILT VDD2 + VDD3 VSS1 VSS2 VSS3 1kΩ 2.2μF No.A1951-10/31 LC88F58B0A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage VI(1) VIO(1) CF1, RESB Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C Peak output current IOPH(1) Ports 0, 1, 2 P70 to P72 P40 to P45 PA0 to PA3 IOPH(2) IOPH(3) P46, P47 Port 6 P30 to P33 PC2 Average output current (Note 1-1) IOMH(2) IOMH(3) High level output current IOMH(1) Ports 0, 1, 2 P70 to P72 P36 to P37 P40 to P45 PA0 to PA3 P46, P47 Port 6 P30 to P33 PC2 Total output current ΣIOAH(2) ΣIOAH(3) Port 6 Port 6 P30 to P33 PC2 ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) ΣIOAH(8) ΣIOAH(9) Ports 0, 1 P25 to P27 P20 to P24 Ports 0, 1, 2 P40 to P45 PA0 to PA3 P46 to P47 P70 to P72 Port 4 P70 to P72 PA0 to PA3 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins -45 -25 -25 -45 -25 -25 ΣIOAH(1) P30 to P33, PC2 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins -20 -15 -15 mA Per applicable pin Per applicable pin -3 -10 CMOS output selected Per applicable pin -7.5 Per applicable pin Per applicable pin -5 -20 CMOS output selected Per applicable pin -10 -0.3 VDD +0.3 Symbol VDD max Applicable Pin /Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD +0.3 unit V Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page. No.A1951-11/31 LC88F58B0A Continued from preceding page. Parameter Peak output current Symbol IOPL(1) Applicable Pin /Remarks Ports 0, 1, 4 P70 to P72 PA0 to PA3 P20, P21, P24 to P27 IOPL(2) IOPL(3) P22, P23 P30 to P33 Port 6 PC0 to PC2 Average output current (Note 1-1) IOML(2) IOML(3) Low level output current IOML(1) Ports 0, 1, 4 P70 to P72 PA0 to PA3 P20, P21, P24 to P27 P22, P23 P30 to P33 Port 6 PC0 to PC2 Total output current ΣIOAL(2) ΣIOAL(3) ΣIOAL(1) P30 to P34 PC0 to PC2 Port 6 Port 6 P30 to P33 PC0 to PC2 ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) ΣIOAL(7) ΣIOAL(8) ΣIOAL(9) Ports 0, 1 P25 to P27 P20 to P24 Ports 0, 1, 2 P40 to P45 PA0 to PA3 P46 to P47 P70 to P72 Port 4 P70 to P72 PA0 to PA3 Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 Pd max SQFP64 (10×10) Ta=-40 to +85°C 200 +85 °C +125 mW Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins 80 45 45 80 45 45 Total of currents at applicable pins Total of currents at applicable pins Total of currents at applicable pins 20 15 mA 15 Per applicable pin Per applicable pin 7.5 20 Per applicable pin 15 Per applicable pin Per applicable pin 10 25 Conditions VDD[V] Per applicable pin 20 min Specification typ max unit Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. No.A1951-12/31 LC88F58B0A Allowable Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(2) VIH(3) VIH(4) Low level input voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock DUTY50±5% • CF2 pin open • System clock frequency division ratio=1/2 Oscillation frequency range (Note 2-3) FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 12MHz ceramic oscillator mode See Fig. 1. 10MHz ceramic oscillator mode See Fig. 1. FmCF(3) CF1, CF2 4MHz ceramic oscillator mode See Fig. 1. FmRC FmSLRC FsX'tal XT1, XT2 Internal RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillator mode See Fig. 2. 2.2 to 5.5 32.768 2.2 to 5.5 2.2 to 5.5 0.5 18 1.0 30 2.0 45 kHz 2.2 to 5.5 4 3.0 to 5.5 10 MHz 4.5 to 5.5 12 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 0.1 0.2 0.2 0.2 2 24 20 4 MHz tCYC VIL(1) VIH(1) Ports 0, 1, 2, 3, 4 Port A Ports 6, 7, PC2 CF1, RESB PC0, PC1 P22, P23 I C side When ports 1, 2, 3, 4 and port A, PnFSAn=0 Ports 0, 6, 7, PC2 When ports 1, 2, 3, 4 and port A, PnFSAn=1 CF1, RESB PC0, PC1 P22, P23 I C side 2 2 Symbol VDD(1) Applicable Pin /Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.081μs≤tCYC≤66μs 0.098μs≤tCYC≤66μs 0.490μs≤tCYC≤66μs min 4.5 3.0 2.2 2.0 0.3VDD +0.7 0.3VDD +0.7 0.75VDD 0.7VDD VSS VSS VSS VSS VSS VSS 0.081 0.098 0.490 0.1 0.1 Specification typ max 5.5 5.5 5.5 5.5 unit VHD VDD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 4.0 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 VDD VDD VDD V VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.25VDD 0.3VDD 66 66 66 12 10 μs Note 2-1: VDD≥3.0V must be maintained when making onboard programming into flash ROM. Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Note 2-3: See Tables 1 and 2 for oscillator constant values. No.A1951-13/31 LC88F58B0A Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Applicable Pin /Remarks Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C RESB IIH(2) Low level input current IIL(1) CF1 Ports 0, 1, 2 Ports 3, 4 Ports 6, 7 Ports A, C RESB IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistor Rpu(1) Rpu(2) Hysteresis voltage VHYS Ports 6, C P30 to P33 Ports 0, 1, 2, 3 Ports 4, 6, 7 Ports A, PC2 RESB When ports 1, 2, 3, 4, A PnFSAn=1 Pin capacitance CP All pins Pins other than that under test VIN=VSS f=1MHz Ta=25°C 2.2 to 5.5 10 pF 2.2 to 5.5 0.1VDD V 2.2 to 4.5 18 55 150 VOL(1) Ports 0, 1 Ports 4, 7 P20 to P21, P24 to P27 PA0 to PA3 P22, P23 IOL=1.6mA IOL=1.0mA IOL=11mA IOL=3.0mA IOL=1.3mA IOL=1.6mA IOL=1.0mA VOH=0.9VDD 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 15 35 0.4 0.4 1.5 0.4 0.4 0.4 0.4 80 kΩ Port 6 P30 to P33 PC2 P46, P47 CF1 Ports 0, 1, 2 PA0 to PA3 P40 to P45 Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr. off leakage current) VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr. off leakage current) VIN=VSS IOH=-1.0mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1.0mA IOL=10mA 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 V 1.5 2.2 to 5.5 -1 2.2 to 5.5 15 μA 2.2 to 5.5 1 min Specification typ max unit No.A1951-14/31 LC88F58B0A Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Period Low level pulse width High level pulse width Input clock tSCKH(1) tSCKHA(1) • Automatic communication mode • See Fig. 6. tSCKHBSY(1a) • Automatic communication mode • See Fig. 6. tSCKHBSY(1b) • Mode other than automatic communication mode • See Fig. 6. Serial clock Period Low level pulse width High level pulse width Output clock tSCKHA(2) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(2a) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(2b) • Mode other than automatic communication mode • See Fig. 6. Data setup time Serial input tsDI(1) SI0 (P11), SB0 (P11) Data hold time thDI(1) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 5.5 0.03 Output Input clock delay time tdD0(1) SO0 (P10), SB0 (P11) • (Note 4-1-2) 1tCYC +0.05 2.2 to 5.5 1tCYC +0.05 μs 0.03 4 4 23 tCYC 2.2 to 5.5 6 tSCKH(2) tSCK(2) tSCKL(2) SCK0 (P12) • CMOS output selected • See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.2 to 5.5 tCYC 6 Symbol tSCK(1) tSCKL(1) Applicable Pin/Remarks SCK0 (P12) Conditions VDD[V] • See Fig. 6. min 4 2 2 Specification typ max unit Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. Output clock tdDO(2) • (Note 4-1-2) No.A1951-15/31 LC88F58B0A SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Parameter Period Serial clock Input clock Low level pulse width High level pulse width Data setup time Serial input tSCKH(3) tSCKHBSY(3) tsDI(2) SI0 (P11), SB0 (P11) Data hold time thDI(2) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 5.5 0.03 μs Serial output Output Input clock delay time tdD0(3) SO0 (P10), SB0 (P11) 2.2 to 5.5 • (Note 4-2-2) 1tCYC +0.05 0.03 Symbol tSCK(3) tSCKL(3) 2.2 to 5.5 Applicable Pin/Remarks SCK0 (P12) Conditions VDD[V] • See Fig. 6. min 2 1 1 2 Specification typ max unit tCYC Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig.6. No.A1951-16/31 LC88F58B0A SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Period Low level pulse width High level pulse width Input clock tSCKH(4) tSCKHA(4) • Automatic communication mode • See Fig. 6. tSCKHBSY(4a) • Automatic communication mode • See Fig. 6. tSCKHBSY(4b) • Mode other than automatic communication mode • See Fig. 6. Serial clock Period Low level pulse width High level pulse width Output clock tSCKHA(5) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(5a) • Automatic communication mode • CMOS output selected • See Fig. 6. tSCKHBSY(5b) • Mode other than automatic communication mode • See Fig. 6. Data setup time Serial input tsDI(3) SI1(P44), SB1(P44) Data hold time thDI(3) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 5.5 0.03 Output Input clock delay time tdD0(4) SO1(P43), SB1(P44) • (Note 4-3-2) 1tCYC +0.05 2.2 to 5.5 1tCYC +0.05 μs 0.03 μs 4 4 23 tCYC 2.2 to 5.5 6 tSCKH(5) tSCK(5) tSCKL(5) SCK1(P45) • CMOS output selected • See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.2 to 5.5 tCYC 6 Symbol tSCK(4) tSCKL(4) Applicable Pin/Remarks SCK1(P45) Conditions VDD[V] • See Fig. 6. min 4 2 2 Specification typ max unit Serial output tdDO(5) Output clock • (Note 4-3-2) Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1951-17/31 LC88F58B0A SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Parameter Period Serial clock Input clock Low level pulse width High level pulse width Data setup time Serial input tSCKH(6) tSCKHBSY(6) tsDI(4) SI1(P44), SB1(P44) Data hold time thDI(4) • Specified with respect to rising edge of SIOCLK • See Fig. 6. 2.2 to 5.5 0.03 μs Serial output Output Input clock delay time tdD0(6) SO1(P43), SB1(P44) 2.2 to 5.5 • (Note 4-4-2) 1tCYC +0.05 0.03 Symbol tSCK(6) tSCKL(6) 2.2 to 5.5 Applicable Pin/Remarks SCK1(P45) Conditions VDD[V] • See Fig. 6. min 2 1 1 2 Specification typ max unit tCYC Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(5) SM0DA(P23) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(5) 2.2 to 5.5 0.03 Output delay Serial output time tdD0(7) SM0DO(P24), SM0DA(P23) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts changing. • See Fig. 6. 2.2 to 5.5 1tCYC +0.05 μs 0.03 tSCKH(8) tSCK(8) tSCKL(8) SM0CK(P22) • CMOS output selected • See Fig. 6. 2.2 to 5.5 tSCKH(7) Symbol tSCK(7) tSCKL(7) Applicable Pin/Remarks SM0CK(P22) See Fig. 6. Conditions VDD[V] min 8 2.2 to 5.5 4 tCYC 4 8 1/2 tSCK 1/2 Specification typ max unit Note 4-5-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A1951-18/31 LC88F58B0A SMIIC0 I2C Mode Input/Output Characteristics Parameter Period Input clock Low level pulse width High level pulse width Period Output clock Low level pulse width High level pulse width SM0CK and SM0DA pins input spike suppression time Bus release start and stop Input time between tBUF SM0CK(P22) SM0DA(P23) 2.5 Tfilt • See Fig. 8. tsp SM0CK(P22) SM0DA(P23) • See Fig. 8. 1 Tfilt tSCLHx tSCLx tSCLLx SM0CK(P22) • Specified as interval up to time when output state starts changing. 2.2 to 5.5 tSCLH Symbol tSCL tSCLL Applicable Pin/Remarks SM0CK(P22) • See Fig. 8. Conditions VDD[V] min 5 2.2 to 5.5 2.5 Tfilt 2 10 1/2 tSCL 1/2 Specification typ max unit Clock tBUFx Output SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 5.5 5.5 μs 1.6 Start/restart condition hold time Input tHD;STA SM0CK(P22) SM0DA(P23) • When SMIIC register control bit, I2CSHDS=0 • See Fig. 8. • When SMIIC register control bit, I CSHDS=1 • See Fig. 8. 2 2.0 Tfilt 2.5 2.2 to 5.5 4.1 μs 1.0 tHD;STAx Output SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. Restart time Input condition setup tSU;STA SM0CK(P22) SM0DA(P23) • See Fig. 8. 1.0 Tfilt tSU;STAx Output SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 5.5 5.5 μs 1.6 Continued on next page. No.A1951-19/31 LC88F58B0A Continued from preceding page Parameter Stop condition Input setup time Symbol tSU;STO Applicable Pin/Remarks SM0CK(P22) SM0DA(P23) • See Fig. 8. 1.0 Tfilt Conditions VDD[V] min Specification typ max unit tSU;STOx Output SM0CK(P22) SM0DA(P23) • Standard clock mode • Specified as interval up to time when output state starts changing. • High-speed clock mode • Specified as interval up to time when output state starts changing. 2.2 to 5.5 4.9 μs 1.1 Data hold time Input tHD;DAT SM0CK(P22) SM0DA(P23) • See Fig. 8. 0 2.2 to 5.5 1 1.5 Tfilt tHD;DATx Output SM0CK(P22) SM0DA(P23) • Specified as interval up to time when output state starts changing. Data setup time Input tSU;DAT SM0CK(P22) SM0DA(P23) • See Fig. 8. 1 2.2 to 5.5 1tSCL -1.5Tfilt Tfilt tSU;DATx Output SM0CK(P22) SM0DA(P23) • Specified as interval up to time when output state starts changing. SM0CK and SM0DA pins fall time Input tF SM0CK(P22) SM0DA(P23) • See Fig. 8. 2.2 to 5.5 300 tF SM0CK (P22) SM0DA (P23) • When SMIIC register control bits, PSLW=1, P5V=1 • When SMIIC register control bits, PSLW=1, P5V=0 • SM0CK, SM0DA port output FAST mode • Cb≤400pF 5 3 20 +0.1Cb 20 +0.1Cb 250 250 ns Output 3 to 5.5 100 Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 0 0 1 1 BRP0 0 1 0 1 Tfilt tCYC×1 tCYC×2 tCYC×3 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt >140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1951-20/31 LC88F58B0A UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer rate Symbol UBR2 Applicable Pin/Remarks U2RX(P16), U2TX(P17) Conditions VDD[V] 2.2 to 5.5 min 8 Specification typ max 4096 unit tBGCYC Note 4-7: tBGCYC denotes one cycle of the baudrate clock source. UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer rate Symbol UBR0 Applicable Pin/Remarks U0RX(P13), U0TX(P14), U0BRG(P07) 2.2 to 5.5 4 8 tBGCYC Conditions VDD[V] min Specification typ max unit Note 4-8: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Applicable Pin/Remarks INT0(P30), INT1(P31), INT2(P32), INT3(P33), INT4(P20), INT5(P21), INT6(P40), INT7(P41) tPIL(2) RESB Resetting is enabled. 2.2 to 5.5 10 μs Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timers 2 and 3 are enabled. 2.2 to 5.5 2 tCYC Specification min typ max unit No.A1951-21/31 LC88F58B0A AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V 12-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD12 Applicable Pin /Remarks AN0(P60) to AN7(P67), AN8(P70) to AN11(P72) (Note 6-1) Conversion time calculated Conditions VDD[V] 2.9 to 5.5 2.9 to 5.5 4.7 to 5.5 4.0 to 5.5 2.9 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 17 27 67 VSS min Specification typ 12 ±16 209 209 209 VDD 1 V μA μs max unit bit LSB Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bit AD Conversion Mode Parameter Resolution Absolute accuracy Conversion time Symbol NAD ETAD TCAD8 Applicable Pin /Remarks AN0(P60) to AN7(P67), AN8(P70) to AN11(P72) (Note 6-1) Conversion time calculated Conditions VDD[V] 2.9 to 5.5 2.9 to 5.5 4.7 to 5.5 4.0 to 5.5 2.9 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 11 17 42 VSS min typ 8 ±1.5 129 129 129 VDD 1 V μA μs Specification max unit bit LSB Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1951-22/31 LC88F58B0A Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V typ: 5.0V (VDD=4.5V to 5.5V), 3.3V (VDD=3.0V to 4.5V, 2.2V to 4.5V) Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Applicable Pin/Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] • FmCF=12MHz ceramic oscillation mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz • Internal RC oscillation stopped • 1/1 frequency division mode • FmCF=10MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode IDDOP(3) • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(4) • FmCF=4MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode IDDOP(5) • System clock set to 4MHz • Internal RC oscillation stopped • 1/2 frequency division mode IDDOP(6) IDDOP(7) IDDOP(8) • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to internal RC oscillation • 1/1 frequency division mode • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDOP(9) • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(10) • FmCF=12MHz ceramic oscillation mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz • Internal RC oscillation stopped • PLL oscillation mode • 1/1 frequency division mode IDDOP(11) • FmCF=10MHz ceramic oscillation mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz IDDOP(12) • Internal RC oscillation stopped • PLL oscillation mode • 1/1 frequency division mode 3.0 to 4.5 5.9 13.0 4.5 to 5.5 10.3 17.0 mA 4.5 to 5.5 11.0 17.5 2.2 to 4.5 39 102 4.5 to 5.5 63 155 μA 2.2 to 4.5 2.5 4.6 4.5 to 5.5 3.8 5.6 3.0 to 4.5 5.0 8.3 mA 4.5 to 5.5 8.5 14.4 4.5 to 5.5 9.3 15.0 min Specification typ max unit 4.5 to 5.5 2.2 to 4.5 2.5 1.7 5.6 4.6 Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. Continued on next page. No.A1951-23/31 LC88F58B0A Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Applicable Pin/Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=12MHz ceramic mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(2) • HALT mode • FmCF=10MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode IDDHALT(3) • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDHALT(4) • HALT mode • FmCF=4MHz ceramic oscillator mode • FmX'tal=32.768kHz crystal oscillator mode IDDHALT(5) • System clock set to 4MHz • Internal RC oscillation stopped • 1/2 frequency division mode IDDHALT(6) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDHALT(7) • System clock set to internal RC oscillation • 1/1 frequency division mode IDDHALT(8) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode IDDHALT(9) • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode HOLD mode consumption current HOLDX mode consumption current IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 HOLD mode • CF1=VDD or open (external clock mode) HOLDX mode • CF1=VDD or open (external clock mode) • FmX'tal=32.768kHz crystal oscillator mode 4.5 to 5.5 2.2 to 4.5 4.5 to 5.5 2.2 to 4.5 0.05 0.03 15 4 20 15 58 35 μA 2.2 to 4.5 10 40 4.5 to 5.5 23 90 μA 2.2 to 4.5 0.20 0.85 4.5 to 5.5 0.42 1.25 2.2 to 4.5 0.40 1.1 4.5 to 5.5 0.90 1.6 3.0 to 4.5 1.3 3.0 mA 4.5 to 5.5 2.5 4.2 4.5 to 5.5 2.9 4.4 Conditions VDD[V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. No.A1951-24/31 LC88F58B0A F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1=VSS2=VSS3=0V Parameter Onboard programming current Onboard programming time tFW(2) tFW(1) • 128-/1K-byte erase operation • 2-byte programming operation 3.0 to 5.5 3.0 to 5.5 20 40 30 60 ms μs Symbol IDDFW(1) Applicable Pin/Remarks VDD1 Conditions VDD[V] • Microcontroller erase current current is excluded. 3.0 to 5.5 5 10 mA min Specification typ max unit Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible. • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF or larger. • The VDD1 and VSS1 traces must be thicker than the other traces. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ Power Pin Treatment Conditions 2 (VDD(2, 3), VSS(2, 3)) Connect capacitors that meet the following condition between the VDD (2, 3) and VSS (2, 3) pins: • Connect among the VDD (2, 3) and VSS (2, 3) pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible. • The capacitance of C3 should be approximately 0.1μF or larger. • The VDD (2, 3) and VSS (2, 3) traces must be thicker than the other traces. L3 VSS (2, 3) C3 VDD (2, 3) L3’ No.A1951-25/31 LC88F58B0A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Frequency Vendor Name Circuit Constant Resonator C3 [pF] 12MHz CSTCE12M0G52-R0 CSTCE10M0G52-R0 10MHz CSTLS10M0G53-B0 MURATA 8MHz CSTLS8M00G53-B0 CSTCR4M00G53-R0 4MHz CSTLS4M00G53-B0 (15) (15) OPEN 1.5k 2.3 to 5.5 0.02 0.2 (15) (15) (15) (15) OPEN OPEN 1k 1.5k 2.5 to 5.5 2.2 to 5.5 0.02 0.02 0.2 0.2 CSTCE8M00G52-R0 (15) (10) (15) (10) OPEN OPEN 680 470 2.6 to 5.5 2.3 to 5.5 0.02 0.02 0.2 0.2 (10) (10) C4 [pF] (10) (10) Rf [Ω] OPEN OPEN Rd2 [Ω] 220 470 Operating Voltage Range [V] 2.4 to 5.5 2.4 to 5.5 Oscillation Stabilization Time typ [ms] 0.02 0.02 max [ms] 0.2 0.2 C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Nominal Frequency Vendor Name EPSON TOYOCOM Circuit Constant Oscillator Name C3 [pF] 32.768kHz MC-306 10 C4 [pF] 10 Rf2 [Ω] OPEN Rd2 [Ω] 0 Operating Voltage Range [V] 2.2 to 5.5 Oscillation Stabilization Time typ [s] 0.4 max [s] 2.0 Applicable CL value=7.0pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. No.A1951-26/31 LC88F58B0A CF1 CF2 XT1 XT2 Rf1 Rd1 Rf2 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1951-27/31 LC88F58B0A VDD Operating VDD lower limit 0V Reset time RESB Power Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Reset Time and Oscillation Stabilization Time HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 State HOLD HALT Instruction execution HOLD Release and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Timing Charts No.A1951-28/31 LC88F58B0A VDD RRES RES CRES Note: Reset signal must be present when power supply rises. Determine the value of CRES and RRES so that the reset signal is present for 10μs after the supply voltage gets stabilized. Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 Data transfer period DO8 DOx (SIO0 and SIO1 only) tSCK SIOCLK: tSCKL tsDI DATAIN: tdDO DATAOUT: Data transfer period tSCKH thDI (SIO0 and SIO1 only) SIOCLK: tSCKL tsDI thDI tSCKHA DATAIN: tdDO DATAOUT: * Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1951-29/31 LC88F58B0A P SDA tBUF tHD;STA tR tF tHD;STA tsp S Sr P SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing 1k Ω PC2/FILT + 2.2μF Cfs VSS1 Cfs=OPEN Figure 9 Recommended FILT Circuit * Take at least 50ms to oscillation to stabilize after PLL is started. No.A1951-30/31 LC88F58B0A SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2008. Specifications and information herein are subject to change without notice. PS No.A1951-31/31