LC88F58B0A

Ordering number : ENA1228 LC88F83B0A Overview CMOS IC FROM 128K byte, RAM 4096K byte on-chip 16-bit 1-chip Microcontroller The LC88F83B0A is a 16-bit microcontroller, centered around an Xstormy16 CPU, integrates on a single chip a number of hardware features such as 32-bit program counter, 16 bits × 16 general purpose register, 128K-byte flash ROM (onboard programmable), 4096-byte RAM, LCD display dedicated RAM, LCD dot matrix driver, on-chip debugging function, programmable timer, a base timer serving as a time-of-day clock, a synchronous SIO interface with automatic transmission capability, an asynchronous SIO (UART) interface, a 12-/8-bit resolution 4-channel AD converter, and a 12-source 11-vector interrupt feature. Features Flash ROM • 128K × 8bit (Table data reside in the same space.) RAM • 4240 × 8bit • For data • For display 4096 × 8bit 72 × 16bit LCD Display • 64 segment × 16 common/72 segment × 8 common (1/4 bias) * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.0.7 40611HKIM 20110328-S00003 No.A1228-1/25 LC88F83B0A Instruction Execution Time (min) • 31.0μs : 32.768kHz crystal used • 15.6μs (typ) : Low speed RC oscillation (typ: 64kHz) • 0.25μs : 4.0MHz ceramic filter oscillation • 1.00μs (typ) : High speed RC oscillation (typ: 1MHz) Power Supply Voltage • 2.3V to 5.5V (Ta =-20 to 75°C) • 2.3V to 5.5V (Ta =0 to 60°C) • 2.4V to 5.5V (Ta =-20 to 75°C) • 2.3V to 5.5V (Ta =0 to 60°C) • 2.4V to 5.5V (Ta =-20 to 75°C) : 32.768kHz crystal used : Low speed RC oscillation (typ: 64kHz) : 4.0MHz ceramic filter oscillation : High-speed RC oscillation (typ: 1MHz) : When LCD ON Consumption Current (3.0V): • 10.5μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, 1/1 dividing frequency, HALT, LCD: ON) • 300μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, HALT, LCD: ON) • 2200μA (typ) (Ta=25°C, crystal oscillation 32.768kHz, CF 4MHz, 1/2 dividing frequency, continuous operation, LCD: ON) Ports • Normal withstand voltage I/O ports 20 (P0n, P1n, P20 to P23) • LCD (COM8/SEG0 to COM15/SEG7 pins are multiplexed with COMMON and SEGMENT) LCD drive bias power supply port 4 (VLCD1 to VLCD4) Step-up capacitor port 2 (CUP00, CUP01) 16 common mode Segment output 64 (SEG8 to SEG71) Common output 16 (COM0 to COM15) 8 common mode Segment output 72 (SEG0 to SEG71) Common output 8 (COM0 to COM7) • Oscillation pins 4 (XT1, XT2, CF1, CF2) • Reset pin 1 (RESB) • Test pin 1 (TST) • LCD port power pins 2 (LCDVSS0, LCDVSS1) • Power pins 2 (VDD, VSS) LCD • LCD power supply • Number of dots • Contrast • LCD frame frequency : Capacitor step-up type : 1024 (64 segments × 16 commons) / 576 (72 segments × 8 commons) : Adjustable in 16 steps : Selectable from 4 types No.A1228-2/25 LC88F83B0A Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) With 5-bit prescaler 2) 8-bit PWM × 2/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) With 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) With 8-bit prescaler 2) 8-bit timer × 2ch/8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Watchdog Timer 1) Driven by the base timer + internal watchdog timer dedicated counter. 2) Interrupt or reset mode selectable SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) It is possible to communicate with 8 bits or less. (1 to 8 bits specifiable in 1-bit units) 3) Built-in 8-bit baudrate generator (transfer clock cycle 4 tCYC to 512 tCYC) 4) Automatic continuous data transmission (9 to 32768 bits specifiable in 1-bit units) 5) Interval function (interval time: 0 to 64 SIOCLKs specifiable in 1 SIOCLK units) 6) Wakeup function UART2: Asynchronous SIO 1) Full duplex transmission 2) Start bit 1, data bit 8 (LSB first), stop bit 1 3) Parity bit: None/even parity/odd parity 4) Transfer rate: 8 to 4096 tCYC 5) Baudrate source clock: systemclock/OSC0/OSC1 6) Wakeup function AD converter: 12bit × 4 channels 1) 12-/8-bit resolution selectable 2) Analog input: 4 channels 3) Comparator mode 4) Automatic reference voltage generation No.A1228-3/25 LC88F83B0A Interrupts • 12 sources, 11 vector addresses 1) Provides three levels of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 11 Vector Address 08000H 08004H 08008H 08018H 0801CH 08020H 08024H 08028H 0802CH 08030H 0803CH WATCHDOGTIMER BASETIMER TIMER0 SIO0 TIMER1 UART2 TIMER3 TIMER4 TIMER5 ADC P00 to P05 SEG71 to SEG64 Interrupt Source • The priority level can be specified by three levels. • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels • Max- whole RAM area (Stack is set in RAM) Oscillation Circuits • OSC1: For system clock ceramic oscillation with external CGC, CDC or RC oscillation (external RCR1) • OSC0: For low-speed system clock, base timer count, for LCD display 32kHz crystal oscillation with external CGX, CDX or RC oscillation (external RCR0) • Internal oscillation circuit: Internal RC * Depends on control resister for each oscillator operation and stop. Initial setting - External oscillation stop, internal RC oscillation operation No.A1228-4/25 LC88F83B0A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, internal RC and X’tal oscillators automatically stop operation. 2) There are the following methods of resetting the HOLD. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the SIO0 (3) Having an interrupt source established in the UART2 (4) Having an interrupt source established in the P00 to P05 (5) Having an interrupt source established in the SEG71 to SEG64 • X’tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except using OSC0. 1) The OSC1 and internal RC oscillators automatically stop operation. 2) The state of OSC0 oscillation established when the X'tal HOLD mode is entered is retained. 3) There are the following methods of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Having an interrupt source established in the base timer circuit (3) Having an interrupt source established in the timers 0, 1, 3, 4, 5 (4) Having an interrupt source established in the SIO0 (5) Having an interrupt source established in the UART2 (6) Having an interrupt source established in the P00 to P05 (7) Having an interrupt source established in the SEG71 to SEG64 On-chip debugger • Supports software debugging with the IC mounted on the target board. • Supports tracing, realtime monitoring, and breakpoint setting. • Single-wire communication Package Form • TQFP120(14×14): Lead-free type Development Tools • On-chip debugger : EOCUIF1 + LC88F83B0A • Programming boards : Package Dimensions unit : mm (typ) 3257A 16.0 14.0 120 1 0.4 (1.2) 1.2MAX (1.0) 0.15 14.0 16.0 0.125 0.1 SANYO : TQFP120(14X14) 0.5 No.A1228-5/25 LC88F83B0A Pad Assignment • Chip size (X × Y) • Pad size • Pad pitch • Chip thickness : 3.40mm × 3.19mm : 59μm : 80μm : 280μm ± 20μm 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Y X (0, 0) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note: Pin numbers assigned to a package differ from pad numbers assigned to a chip. Numbers in the above figure show the pad numbers of the chip. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 102 103 104 97 98 99 100 101 No.A1228-6/25 LC88F83B0A Pad Coordinates Table Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin Name P20 P21 P22 P23 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 LCDVSS1 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 Coordinates X μm 1567.4 1567.4 1567.4 1567.4 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1606.99 1567.4 1567.4 1567.4 1567.4 1567.4 1567.4 1567.4 1567.4 1567.4 1567.4 1190 1088 1008 928 848 768 688 608 528 448 368 288 208 128 48 -32 -112 Y μm -1308 -1228 -1147 -1067 -951.8 -863.6 -775.4 -606.8 -518.6 -430.4 -342.2 -254 -165.8 -77.6 10.6 98.8 187 275.2 363.4 451.6 573 653 733 813 893 973 1053 1133 1213 1293 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 Pad No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Pin Name SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 COM15/SEG7 COM14/SEG6 COM13/SEG5 COM12/SEG4 COM11/SEG3 COM10/SEG2 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCDVSS0 Coordinates X μm -192 -272 -352 -432 -512 -592 -672 -752 -832 -912 -992 -1072 -1152 -1232 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 -1567.4 Y μm 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1462.4 1335 1255 1175 1095 1015 935 855 775 615 455 295 135 -25 -185 -345 -505 -585 -665 -745 -825 -905 -985 -1065 -1145 -1240 Continued on next page. No.A1228-7/25 LC88F83B0A Continued from preceding page. Pad No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Pin Name CUP00 CUP01 VLCD4 VLCD3 VLCD2 VLCD1 TST XT2 XT1 RESB VDD CF1 CF2 VSS Coordinates X μm -1567.4 -1567.4 -1295.45 -1215.45 -1130.8 -1050.8 -965 -723 -643 -563 -383.5 -272.5 -172 -92 3 108 Y μm -1335.8 -1415.8 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 Pad No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Coordinates X μm 205 285 365 445 525 605 685 765 845 925 1005 1085 1165 1245 1325 1405 Y μm -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 -1462.4 Note: • Pad coordinates shown in above table are referenced at the center of the IC-chip as an origin. • There are two pads for each VDD and VSS, and each set of pads needs double-bonding. Pin Assignment SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 LCDVSS1 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG8 SEG9 COM15/SEG7 COM14/SEG6 COM13/SEG5 COM12/SEG4 COM11/SEG3 COM10/SEG2 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LCDVSS0 CUP00 CUP01 LC88F83B0A XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI P01/P0LI P02/P0LI P03/P0LI P04/P0HLI P05/P0HLI P06/T0PWML P07/T0PWMH P10/SI0O P11/SI0IO P12/SI0CLK P13/T3OL P14/T3OH P15 P16/U2RX P17/U2TX VLCD4 VLCD3 VLCD2 VLCD1 TST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56/SNO15/SGIN15 SEG57/SNO14/SGIN14 SEG58/SNO13/SGIN13 SEG59/SNO12/SGIN12 SEG60/SNO11/SGIN11 SEG61/SNO10/SGIN10 SEG62/SNO9/SGIN9 SEG63/SNO8/SGIN8 SEG64/SNO7/SGIN7/SGINT7 SEG65/SNO6/SGIN6/SGINT6 SEG66/SNO5/SGIN5/SGINT5 SEG67/SNO4/SGIN4/SGINT4 SEG68/SNO3/SGIN3/SGINT3 SEG69/SNO2/SGIN2/SGINT2 SEG70/SNO1/SGIN1/SGINT1/T3IH SEG71/SNO0/SGIN0/SGINT0/T3IL P23/AN3 P22/AN2 P21/AN1/T5O P20/AN0/T4O Top view SANYO: TQFP120(14×14) “Lead-free Type” No.A1228-8/25 LC88F83B0A Pin No. 1 2 3 4 5 Name VLCD4 VLCD3 VLCD2 VLCD1 TST Pin No. 31 32 33 34 35 Name P20/AN0/T4O P21/AN1/T5O P22/AN2 P23/AN3 SEG71/SNO0 /SGIN0/SGINT0 /T3IL 6 36 SEG70/SNO1 /SGIN1/SGINT1 /T3IH 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 XT2 XT1 RESB VDD CF1 CF2 VSS P00/P0LI P01/P0LI P02/P0LI P03/P0LI P04/P0HLI P05/P0HLI P06/T0PWML P07/T0PWMH P10/SI0O P11/SI0IO P12/SI0CLK P13/T3OL P14/T3OH P15 P16/U2RX P17/U2TX 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SEG69/SNO2 /SGIN2/SGINT2 SEG68/SNO3 /SGIN3/SGINT3 SEG67/SNO4 /SGIN4/SGINT4 SEG66/SNO5 /SGIN5/SGINT5 SEG65/SNO6 /SGIN6/SGINT6 SEG64/SNO7 /SGIN7/SGINT7 SEG63/SNO8 /SGIN8 SEG62/SNO9 /SGIN9 SEG61/SNO10 /SGIN10 SEG60/SNO11 /SGIN11 SEG59/SNO12 /SGIN12 SEG58/SNO13 /SGIN13 SEG57/SNO14 /SGIN14 SEG56/SNO15 /SGIN15 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 81 82 83 84 85 86 87 88 89 90 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 111 112 113 114 115 116 117 118 119 120 COM5 COM4 COM3 COM2 COM1 COM0 LCDVSS0 CUP00 CUP01 80 SEG27 110 COM6 79 SEG28 109 COM7 78 SEG29 108 COM8/SEG0 77 SEG30 107 COM9/SEG1 76 SEG31 106 COM10/SEG2 75 SEG32 105 COM11/SEG3 74 SEG33 104 COM12/SEG4 73 SEG34 103 COM13/SEG5 72 SEG35 102 COM14/SEG6 71 SEG36 101 COM15/SEG7 70 SEG37 100 SEG8 69 SEG38 99 SEG9 68 SEG39 98 SEG10 67 SEG40 97 SEG11 66 SEG41 96 SEG12 Pin No. 61 62 63 64 65 Name LCDVSS1 SEG45 SEG44 SEG43 SEG42 Pin No. 91 92 93 94 95 SEG16 SEG15 SEG14 SEG13 Name No.A1228-9/25 LC88F83B0A System Block Diagram Interrupt control RESB System control TST Standby control IR XT1 XT2 CF1 CF2 OSC0 X’tal RC Clock CF RC ROM (128K×8bit) OSC1 Internal RC PC Base timer RAM WD timer (4K×8bit) LCD display RAM 72×16bit PSW SEG 0 to 71 SEG 71 to 56 COM 0 to 15 LCD segment driver 72 terminals (I/O 16 terminals) Common driver 16 terminals ALU R0 to R15 Timer 0 CUP00, 01 LCD power supply Timer 1 Timer 3 VLCD1 to 4 Timer 4 P00 to 07 I/O Port Timer 5 P10 to 17 I/O Port UART2 P20 to 23 I/O Port (ADC 4 terminals) SIO0 On-chip debugger No.A1228-10/25 LC88F83B0A Pin Description Pin Name VDD VSS VLCD1 to 4 LCDVSS0, LCDVSS1 CUP00, 01 OSC0 XT1 XT2 OSC1 CF1 CF2 PORT 0 P00 to P07 I/O + power supply pin - power supply pin LCD bias power port (capacitor connection port) LCD power supply pin Description I O I O I/O Switching pin for generating LCD driving voltage Connect capacitor between both ports. Oscillator circuit for system clock (low speed) • 32.768kHz crystal oscillator and capacitor for oscillation connection • XT1: Resistor connection for RC oscillation (RC model) Oscillator circuit for system clock (high speed) • Ceramic oscillator and capacitor for oscillator connection • CF1: Resistance connection for RC oscillator (RC model) • 8-bit I/O port • I/O specifiable in 1-bit units • Shared pins P00 to P05 : Interrupt function P06: Timer 0 PWML output P07: Timer 0 PWMH output PORT 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Shared pins P10: SIO0 data output P11: SIO0 data input/Bus I/O P12: SIO0 Clock I/O P13: Timer 3 PWML output P14: Timer 3 PWMH output P16: UART 2 receive P17: UART 2 send PORT 2 P20 to P23 I/O • 4-bit I/O port • I/O specifiable in 1-bit units P20 to P23: AD converter input ports (AN0 to AN3) • Shared pins P20: Timer 4 output P21: Timer 5 output COM0 to COM7 COM8/SEG0 to COM15/SEG7 SEG8 to SEG55 SEG56 to SEG71 O O O I/O • LCD common output port • LCD common output port/segment output port common output/segment output is switched according to the register. • LCD segment output port • LCD segment output port • SEG71 to SEG56: General purpose Nch OD output/General purpose input SEG71 to SEG56 can switch LCD output, a general-purpose Nch OD output, and a general-purpose input (every 4 bits). • SEG71 to SEG64: Interrupt function (every 4 bits) Selecting sampling frequency for chattering removal (every 4 bits) Level/edge selection (every 4 bits) Hi/Low level or rise/fall selection (every 1 bit) • SEG71 to SEG70: Timer 3 external input RESB I • Input terminal for system initialization It operates reset by the “LOW” input. with pull-up resistor TST I/O • TEST pin • On-chip debugger communication terminal Used with pull-down or VSS *Connect 100kΩ between this pin and VSS when on-chip debugger is used. No.A1228-11/25 LC88F83B0A Application circuit LCD panel 64×16/72×8 COM0 COM7 SEG8 COM15/SEG7 COM8/SEG0 SEG71 CUP01 CUP00 C1 C2 C3 C4 C5 I/O P00 P01 P02 P03 P04 P05 P06 P07 VLCD4 VLCD3 VLCD2 VLCD1 LC88F83B0A I/O UART device P10 (SIO0-OUT) P11 (SIO0-IN) P12 (SIO0-CLK) P13 P14 P15 P16 (UART2-RX) P17 (UART2-TX) 2.3V to 5.5V VDD + CDEN CRES RESB Pulse output I/O P20 P21 P22 P23 VSS LCDVSS0 LCDVSS1 XT2 RTST CF2 CF1 XT1 On-chip debugger TST CF CDC CCR1 RCR1 CGC *3 X'tal CDX *1: Crystal oscillation *2: Internal RC oscillation *3: Ceramic oscillation CGX *1 CCR0 RCR0 *5 *4 X'tal CGX CDX RCR0 CCR0 (**1) CF CGC CDC RCR1 CCR1 C1 to C5 CDEN CRES RTST Crystal oscillator Trimmer capacitor Capacitance for X’tal Resistor for low-speed oscillation Capacitor for low-speed oscillation *4: RC oscillation specification *4: RC oscillation specification (**1) 0.1μF capacitor is recommended when using XT1/XT2 as a system clock. Ceramic oscillator Capacitance for CF Capacitance for CF Resistor for high-speed oscillation *5: RC oscillation specification Capacitor for high-speed oscillation *5: RC oscillation specification Capacitor Electrolytic capacitor Capacitance for RESB Resister when on-chip debugger is used No.A1228-12/25 LC88F83B0A Absolute Maximum Ratings at Ta = 25°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Maximum supply voltage LCD supply voltage LCD maximum supply voltage Input voltage Input/output voltage Peak output current High level output current IOPH(2) Mean output current (Note 1-1) Total output current IOMH(2) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) Peak output current Low level output current Mean output current (Note 1-1) Total output current ΣIOAL(2) ΣIOAL(3) Allowable power dissipation Operating ambient temperature Storage ambient temperature Tstg Topg -20 -65 Pd max PORT1 PORT 0, 1, 2 TQFP120(14×14) Total of all pins Total of all pins Ta=-20 to +75°C ΣIOAL(1) PORT0, 2 Total of all pins IOPL(1) IOPL(2) IOML(1) IOML(2) PORT1 PORT0, 2 PORT1 PORT 0, 1, 2 PORT0, 2 PORT1 PORT0, 2 PORT1 IOMH(1) PORT1 PORT0, 2 IOPH(1) VI(1) VIO(1) LCD max SEG0 to SEG71 COM0 to COM15 RESB, XT1, CF1 PORT 0, 1, 2 SEG71 to SEG56 PORT0, 2 CMOS output selected Current at each pin CMOS output selected Current at each pin CMOS output selected Current at each pin CMOS output selected Current at each pin Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Current at each pin Current at each pin VDD, VLCD4 VLCD max VLCD2 to VLCD4 VDD Symbol VDD max Pin/Remarks VDD VDD Conditions VDD[V] min -0.3 -0.3 -0.3 -0.3 -0.3 -5 -14 -3 -9 22.5 25 47.5 13 17 7.5 10.5 35 60 80 250 75 °C 125 mW mA Specification typ max +6.5 +6.5 +6.5 VDD+0.3 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. Note: We assume that the measurements for the allowable operating ranges and electrical characteristics described in this document are performed with the chip mounted in a package. Although this product is shipped in chip form, the characteristic values listed in this document are measured with this IC mounted on a SANYO-designated package at operating ambient temperature range of -20°C to +70°C. The specifications of this product in package form or in chip forms are basically identical, however, the characteristics of the product in chip form may vary depending on the board on which the product is mounted, the bonding pressure, and the type of mold resin used. No.A1228-13/25 LC88F83B0A Allowable Operating Conditions at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Operating supply voltage (Note2-1) LCD drive voltage Memory sustaining supply voltage High level input voltage VIH(2) Low level input voltage VIL(2) Oscillating frequency range (Note2-3) FOSC1 CF1, CF2 FOSC0 RESB XT1, XT2 Crystal oscillation Low speed RC oscillation (Note2-2) Ceramic oscillation High-speed RC oscillation (Note2-2) FINTRC Internal RC oscillation 2.3 to 5.5 2.3 to 5.5 2.4 to 5.5 2.4 to 5.5 2.3 to 5.5 30 400 400 400 1000 VIL(1) RESB Port 0, 1 Output disabled VIH(1) Port 0, 1 Output disabled 0.30VDD +0.70 0.75VDD VSS VSS 32.768 80 4200 4200 1100 kHz VDD VDD 0.10VDD +0.40 0.25VDD VHD VDD RAM and register contents sustained in HOLD mode. 2.0 5.5 V VLCD(1) VLCD2 to VLCD4 Symbol VDD(1) VDD Pin /Remarks Conditions VDD[V] 0.238μs≤tCYC≤100μs 0.476μs≤tCYC≤100μs 0.909μs≤tCYC≤100μs min 2.6 2.4 2.3 Ratings typ max 5.5 5.5 5.5 5.5 unit Note2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode. Note2-2: Ta=0°C to 60°C Note2-3: The parts value of oscillation circuit is shown in table 1 and table 2. No.A1228-14/25 LC88F83B0A Electrical Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks PORT 0, 1, 2 Conditions VDD[V] Output disabled Pull-up resister OFF VIN=VDD (including OFF state leak current of the output Tr.) IIH(2) Low level input current IIL(1) RESB PORT 0, 1, 2 VIN=VDD Output disabled Pull-up resister OFF VIN=VSS (including OFF state leak current of the output Tr.) IIL(2) IIL(3) IIL(4) IIL(5) High level output current IOH(1) IOH(2) IOH(3) IOH(4) Low level output current IOL(1) IOL(2) IOL(3) IOL(4) IOL(5) IOL(6) Common output current Segment output current Hysterisis voltage Pin capacitance IOH(5) IOL(7) IOH(6) IOL(8) VHYS(1) CP PORT 0, 1, 2 RESB All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF SEG0 to SEG71 COM0 to COM15 VOH(2)=VLCD4-0.05V VOL(2)=VSS+0.05V VOH(2)=VLCD4-0.05V VOL(2)=VSS+0.05V 2.7 to 5.5 SEG71 to SEG56 PORT1 CMOS output mode PORT0, 2 CMOS output mode PORT1 PORT0, 2 VOL(1)=VSS+1.0V RESB PORT 0, 1, 2 Output disabled Pull-up resister ON VIN=VSS (including OFF state leak current of the output Tr.) VOH(1)=VDD-1.0V 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 4.5 to 5.5 2.7 to 3.0 2.7 to 5.5 25 2.7 to 5.5 10 0.1VDD V -10 10 4.4 14.5 6.5 0.5 0.5 -25 μA -117 -31 -10.2 -6.3 -25 -5.8 -3.7 -2.4 -3.7 -1.6 -10 -4.5 mA 2.7 to 5.5 -1 μA 2.7 to 5.5 1 2.7 to 5.5 1 min Specification typ max unit No.A1228-15/25 LC88F83B0A LCD Drive Voltage at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter LCD drive voltage Symbol VLCD1 Pin/Remarks VDD VLCD1 Conditions VDD[V] Contrast “00” Contrast “01” Contrast “02” Contrast “03” Contrast “04” Contrast “05” Contrast “06” Contrast “07” Contrast “08” Contrast “09” Contrast “10” Contrast “11” Contrast “12” Contrast “13” Contrast “14” Contrast “15” VLCD2 VLCD3 VLCD4 2.4 to 5.5 Typ ×0.88 min typ 1.030 1.045 1.060 1.075 1.090 1.105 1.120 1.135 1.150 1.165 1.180 1.195 1.210 1.225 1.240 1.255 2×VLCD1 3×VLCD1 4×VLCD1 Typ ×1.10 V Special notes: 0.1μF capacitor must be connected to VLCD1, VLCD2, VLCD3, and VLCD4. (with no panel load) Specification max unit No.A1228-16/25 LC88F83B0A Serial I/O Characteristics at Ta = -20°C to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V 1. SIO0 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(1) Automatic communication mode See Fig. 6. tSCKHBSY(1a) Automatic communication mode See Fig. 6. tSCKHBSY(1b) Serial clock Excluding Automatic communication mode See Fig. 6. Frequency Low level pulse width High level pulse width Output clock tSCKHA(2) Automatic communication mode CMOS output selected See Fig. 6. tSCKHBSY(2a) Automatic communication mode CMOS output selected See Fig. 6. tSCKHBSY(2b) Excluding automatic communication mode See Fig. 6. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) Must be specified with respect to rising edge of SIOCLK. See Fig. 6. 2.3 to 5.5 0.03 Output Input clock delay time tdD0(1) SO0(P10), SB0(P11) (Note4-1-2) 1tCYC +0.05 2.3 to 5.5 1tCYC +0.05 μs 0.03 4 4 23 tCYC 2.3 to 5.5 6 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected See Fig. 6. 4 1/2 tSCK 1/2 4 23 2.3 to 5.5 6 tCYC tSCKH(1) Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 4 2 2 Specification typ max unit Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. Output clock tdDO(2) (Note4-1-2) No.A1228-17/25 LC88F83B0A 2. SIO1 Serial I/O Characteristics (Wake-up function is not in use) (Note 4-2-1) Parameter Frequency Serial clock Low level pulse width High level pulse width tSCKHBSY(3) Data setup time Serial input tsDI(2) SI0(P11), SB0(P11) Data hold time thDI(2) Must be specified with respect to rising edge of SIOCLK. See Fig. 6. 2.3 to 5.5 0.03 μs Serial output Output Input clock delay time tdD0(3) SO0(P10), SB0(P11) 2.3 to 5.5 (Note4-2-2) 1tCYC +0.05 0.03 tSCKH(3) Symbol tSCK(3) tSCKL(3) 2.3 to 5.5 1 2 Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 2 1 tCYC Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6. UART2 Operating Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Transfer rate Symbol UBR2 Pin/Remarks URX2(P16), UTX2(P17) Conditions VDD[V] 2.3 to 5.5 min 8 Specification typ max 4096 unit tCYC Pulse Input Conditions at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter High/low level pulse width Symbol tPIL(1) Pin/Remarks RESB Conditions VDD[V] Resetting is enabled. 2.3 to 5.5 min 50 Specification typ max unit μs Input clock No.A1228-18/25 LC88F83B0A AD Converter Characteristics at VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog ports input current IAINH IAINL VAIN=VDD VAIN=VSS N ET TCAD VAIN Symbol Pin/Remarks AN0(SEG71) to AN3(SEG68) (Note7-1) See Conversion time calculation formulas. (Note7-2) Conditions VDD[V] 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 90 VSS min Specification typ 12 ±16 130 VDD 1 max unit bit LSB μs V μA Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog ports input current IAINH IAINL VAIN=VDD VAIN=VSS N ET TCAD VAIN Symbol Pin/Remarks AN0(SEG71) to AN3(SEG68) (Note7-1) See Conversion time calculation formulas. (Note7-2) Conditions VDD[V] 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 2.9 to 5.5 -1 55 VSS min Specification typ 8 ±1.5 75 VDD 1 max unit bit LSB μs V μA 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(Division ratio))+2) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(Division ratio))+2) × tCYC External Oscillator FmCF[MHz] CF-4 Operating Supply Voltage Range VDD[V] 2.9 to 4.0 System Division Ratio (SYSDIV) 1/1 1/2 Cycle Time tCYC [ns] 250 500 AD Division Ratio (ADDIV) 1/8 1/4 AD Conversion Time (TCAD)[μs] 12-bit AD 104.5 105.0 8-bit AD 64.5 65.0 Note 7-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 7-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: • The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. No.A1228-19/25 LC88F83B0A Consumption Current Characteristics at Ta = -20 to +75°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Consumption current during normal operation (Note 8-1) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD Conditions VDD[V] Crystal oscillation mode • FOSC0=32.768kHz • System clock: FOSC0 • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1frequency division ratio. [No panel load] Ceramic oscillation mode • FOSC1=4MHz • System clock: FOSC1 IDDOP(6) • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/2 frequency division ratio. IDDOP(7) Internal RC oscillation mode • System clock: Internal RC • Internal RC oscillates IDDOP(8) • FOSC0=0Hz (Oscillation stop) • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio IDDOP(9) High-speed RC oscillation mode *Ta=0 to 60°C • FOSC1=1MHz RCR1=470kΩ IDDOP(10) • System clock: FOSC1 • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDOP(11) Low-speed RC oscillation mode *Ta=0 to 60°C • FOSC0=64kHz RCR0=910kΩ IDDOP(12) • System clock: FOSC0 • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. 2.3 to 3.6 70 110 2.3 to 5.5 110 170 2.3 to 3.6 1200 1700 2.3 to 5.5 1700 2300 2.3 to3.6 1200 2000 2.3 to 5.5 1900 3000 μA 2.4 to 3.6 2200 2900 2.4 to5.5 3000 4100 LCD Display OFF LCD Display ON 2.4 to 5.5 2.4 to 3.6 2.3 to 5.5 2.3 to 3.6 min Specification typ 70 50 70 40 max 150 80 120 70 unit Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1228-20/25 LC88F83B0A Continued from preceding page. Parameter Consumption current during HALT mode (Note 8-1) IDDHALT(3) IDDHALT(4) IDDHALT(5) IDDHALT(2) Symbol IDDHALT(1) Pin/ Remarks VDD HALT mode Crystal oscillation mode • FOSC0=32.768kHz • System clock: FOSC0 • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1frequency division ratio. [No panel load] HALT mode Ceramic oscillation mode • FOSC1=4MHz IDDHALT(6) • System clock: FOSC1 • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/2 frequency division ratio. IDDHALT(7) HALT mode Internal RC oscillation mode • System clock: Internal RC IDDHALT(8) • Internal RC oscillates • FOSC0=0Hz (Oscillation stop) • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDHALT(9) HALT mode High-speed RC oscillation mode *Ta=0 to 60°C • FOSC1=1MHz RCR1=470kΩ IDDHALT(10) • System clock: FOSC1 • Internal RC oscillation stopped • FOSC0=0Hz (Oscillation stop) • 1/1 frequency division ratio. IDDHALT(11) HALT mode Low-speed RC oscillation mode *Ta=0 to 60°C • FOSC0=64kHz RCR0=910kΩ IDDHALT(12) • System clock: FOSC0 • Internal RC oscillation stopped • FOSC1=0Hz (Oscillation stop) • 1/1 frequency division ratio. Consumption current during HOLD mode Consumption current during clock HOLD mode IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD VDD HOLD mode • CF1=VDD or OPEN (External clock mode) Clock HOLD mode • CF1=VDD or OPEN (External clock mode) • FmX’tal=32.768kHz crystal oscillation mode 2.3 to 5.5 2.3 to 3.6 2.3 to 5.5 2.3 to 3.6 16 3 12 5 55 16 2.3 to 3.6 10 30 2.3 to 5.5 20 50 2.3 to 3.6 100 200 2.3 to 5.5 200 400 μA 2.3 to 3.6 200 300 2.3 to 5.5 400 700 2.4 to 3.6 300 500 2.4 to 5.5 700 1100 LCD Display OFF Condition VDD[V] LCD Display ON 2.4 to 5.5 2.4 to 3.6 2.3 to 5.5 2.3 to 3.6 min Specification typ 32 15 22 6 max 93 35 59 21 unit Note 8-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS = LCDVSS0 = LCDVSS1 = 0V Parameter Onboard programming current Programming time tFW(1) tFW(2) Erasing time: 128 bytes Programming time: 2 bytes 2.7 to 5.5 2.7 to 5.5 20 40 30 60 ms μs Symbol IDDFW(1) Pin/ Remarks VDD Conditions VDD[V] The consumption current of the microcomputer is excluded. 2.7 to 5.5 5 10 mA min Specification typ max unit No.A1228-21/25 LC88F83B0A Characteristics of a Sample OSC1 System Clock Oscillation Circuit Given below are the characteristics of a sample OSC1 system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample OSC1 System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Oscillator Name CSTCR4M00G53-R0 CSTLS4M00G53-B0 4.000MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 C1 [pF] 4.194MHz MURATA (15) (15) (15) (15) Circuit Constant C2 [pF] (15) (15) (15) (15) Rf1 [Ω] OPEN OPEN OPEN OPEN Rd1 [Ω] 0 0 0 0 Operating Voltage Range [V] 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 0.1 0.1 0.1 max [ms] 0.5 0.5 0.5 0.5 Internal C1,C2 Internal C1,C2 Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the following reference timing points: (See Figure 4) • VDD goes above the operating voltage lower limit. • An instruction for starting the OSC1 clock oscillator circuit is executed. • Oscillation starts after the microcontroller exits the X'tal HOLD mode with the ENOSC1 bit (OCR0 register, bit 1) set to 1. Characteristics of a Sample OSC0 System Clock Oscillator Circuit Given below are the characteristics of a sample OSC0 system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample OSC0 System Clock Oscillator Circuit with a CF Oscillator Nominal Frequency Circuit Constant Vendor Name Oscillator Name C3 [pF] 32.768kHz EPSON TOYOCOM MC-306 18 C4 [pF] 18 Rf2 [Ω] OPEN Rd2 [Ω] 390k Operating Voltage Range [V] 2.3 to 5.5 Oscillation Stabilization Time typ [s] 1.3 max [s] Applicable 3.0 CL value=12.5pF SMD-type Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the OSC0 clock oscillation circuit is executed. (See Figure 4) Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. Rf1 CF1 CF2 XT1 Rf2 XT2 Rd1 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1228-22/25 LC88F83B0A Power supply VDD Operating VDD lower limit 0V Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A1228-23/25 LC88F83B0A VDD RRES RESB CRES Note: Select CRES and RRES values to assure that at least 50μs reset time is provided after the VDD becomes higher than the minimum operating voltage. Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 Data RAM transfer period DO8 DOx (SIO0 only) tSCK SIOCLK: tSCKL tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period tSCKH thDI (SIO0 only) SIOCLK: tSCKL tsDI thDI tSCKHA DATAIN: tdDO DATAOUT: *: Remarks: DIx and DOx are the final communication bits. X = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1228-24/25 LC88F83B0A Note: The oscillation frequency changes with the board pattern and used parts when OSC1 and OSC0 are used as the RC oscillation. It also greatly depends on the product shape (chip and plastic package) and the board capacitance, and it is recommended to evaluate the resistor value with an actual product. Use the following characteristics as only for a reference. Frequency - Resistor Ta=25°C, typ 10 7 5 3 1000 7 5 3 Frequency - Resistor Ta=25°C, typ Frequency - MHz 2 Frequency - kHz 200 400 600 800 1000 1200 2 1.0 7 5 3 2 100 7 5 3 2 0.1 0 10 0 200 400 600 800 1000 1200 Resistor - kΩ ILC05650 Resistor - kΩ ILC05651 Figure 8 Characteristics of Resistor v.s. Frequency of OSC1 Figure 9 Characteristics of Resistor v.s. Frequency of OSC0 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2011. Specifications and information herein are subject to change without notice. PS No.A1228-25/25