LB11826-E

Ordering number : EN7109A LB11826 Monolithic Digital IC For OA Products http://onsemi.com Three-Phase Brushless Motor Driver Overview The LB11826 is a three-phase brushless motor driver that is optimal for driving drum and paper feed motors in laser printers and plain paper copiers. This IC adopts a direct PWM drive technique for minimal power loss. Flexible control of motor speed in response to an externally provided clock frequency (corresponding to the FG frequency) can be implemented by using the LB11826 in conjunction with the Sanyo LB11825M. Features • Three-phase bipolar drive (30V, 2.5V) • Direct PWM drive • Built-in low side inductive kickback absorbing diode • Speed discriminator + PLL speed control • Speed locked state detection output • Built-in forward/reverse switching circuit • Full complement of built-in protection circuits, including current limiter circuit, thermal protection circuit, and motor constraint protection circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Allowable power dissipation Symbol Conditions VCC max IO max Ratings Unit 30 T ≤ 500ms Pd max1 Independent IC Pd max2 When infinitely large heat sink V 2.5 A 3 W 20 W Operating temperature Topr -20 to +80 °C Storage temperature Tstg -55 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Semiconductor Components Industries, LLC, 2013 May, 2013 71608 MS PC/O0503AS (OT) No.7109-1/11 LB11826 Allowable Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range 1 VCC 9.5 to 28 V Voltage output current IREG 0 to -30 mA ILD 0 to 15 mA LDn output current Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Parameter Symbol Ratings Conditions min Supply current 1 ICC1 Supply current 2 ICC2 typ Unit max 23 30 mA Stop mode 3.5 5 mA 2.5 Output block Output saturation voltage 1 VO sat1 IO = 1.0A, VO (sink) + (source) 2.0 Output saturation voltage 2 VO sat2 IO = 2.0A, VO (sink) + (source) 2.6 Output leakage current IO leak V 3.2 V 100 μA Lower side diode forward voltage 1 VD1 ID = -1.0A 1.2 1.5 V Lower side diode forward voltage 2 VD2 ID = -2.0A 1.5 2.0 V VREG IO = -5mA 5.00 5.35 V 5V Voltage output Output voltage 4.65 Voltage regulation ΔVREG1 VCC = 9.5 to 28V 30 100 mV Load regulation ΔVREG2 IO = -5 to -20mA 20 100 mV Hall Amplifier Input bias current Common-mode input voltage range IHB -2 VICM 1.5 Hall input sensitivity μA -0.5 VREG-1.5 80 V mVp-p Hysteresis width ΔVIN Input voltage low → high VSLH 12 mV Input voltage high → low VSHL -12 mV 15 24 42 mV PWM oscillator circuit Output H level voltage VOH (PWM) 2.5 2.8 3.1 Output L level voltage VOL (PWM) 1.2 1.5 1.8 C = 3900pF 18 V V Oscillator frequency f (PWM) kHz Amplitude V (PWM) 1.05 1.30 1.55 Vp-p VOH (CSD) 3.6 3.9 4.2 V -17 -12 -9 μA CSD circuit Operating voltage External C charge current Operating time ICHG T (CSD) C = 10μF, Design target value* 3.3 s Current limiter operation Limiter VRF VCC-VM 0.45 0.5 0.55 V TSD Design target value* (junction temperature) 150 180 °C ΔTSD Design target value* (junction temperature) 50 °C Thermal shutdown operation Thermal shutdown operating temperature Hysteresis width FG amplifier Input offset voltage Input bias current VIO (FG) -10 IB (FG) 10 mV 1 μA 0.8 1.2 V 180 250 mV 2 kHz -1 Output H level voltage VOH (FG) IFGO = -0.2mA Output L level voltage VOL (FG) IFGO = 0.2mA FG input sensitivity Gain 100-fold Schmitt amplitude for the next stage Design target value* VREG-1.2 VREG-0.8 3 100 mV Operation frequency range Open-loop gain f (FG) = 2kHz V 45 51 dB Note : * These items are design target values and are not tested. Continued on next page. No.7109-2/11 LB11826 Continued from preceding page. Parameter Symbol Ratings Conditions min typ VREG-1.0 VREG-0.7 Unit max Speed discriminator Output H level voltage VOH (D) IDO = -0.1mA Output L level voltage VOL (D) IDO = 0.1mA 0.8 Number of counts V 1.1 V 512 PLL output Output H level voltage VOH (P) IPO = -0.1mA VREG-1.8 VREG-1.5 VREG-1.2 V Output L level voltage VOL (P) IDO = 0.1mA 1.2 1.5 1.8 V VOL (LD) ILD = 10mA 0.15 0.5 Lock detection Output L level voltage Lock range 6.25 V % Integrator Input bias current IB (INT) -0.4 Output H level voltage VOH (INT) IINTO = -0.2mA Output L level voltage VOL (INT) IINTO = 0.2mA Open-loop gain f (INT) = 1kHz Gain width product Design target value* Reference voltage Design target value* VREG-1.2 0.4 VREG-0.8 0.8 45 51 -5% VREG/2 μA V 1.2 V dB 450 kHz 5% V Clock input pin Operating frequency range fOSC 1 L level pin voltage VOSCL IOSC = -0.5mA H level pin current IOSCH VOSC = VOSCL + 0.5V MHz 1.55 V 0.4 mA Start/Stop pin H level input voltage range VIH (S/S) 3.5 VREG V L level input voltage range VIL (S/S) 0 1.5 V Input open voltage VIO (S/S) VREG-0.5 Hysteresis width ΔVIN VREG V 0.50 0.65 V -10 0 10 μA -280 -210 0.35 H level input current IIH (S/S) V (S/S) = VREG L level input current IIL(S/S) V (S/S) = 0V μA Forward/Reverse pin H level input voltage range VIH (F/R) 3.5 VREG V L level input voltage range VIL (F/R) 0 1.5 V Input open voltage VIO (F/R) VREG-0.5 Hysteresis width ΔVIN H level input current IIH (F/R) V (F/R) = VREG L level input current IIL(F/R) V (F/R) = 0V VREG V 0.35 0.50 0.65 V -10 0 10 μA -280 -210 μA Note : * These items are design target values and are not tested. No.7109-3/11 LB11826 Package Dimensions unit : mm (typ) 3174C Pd max – Ta 15 12.7 11.2 8.4 28 Allowable power dissipation, Pd max – W 24 0.4 R1.7 1 14 20.0 4.0 4.0 26.75 (1.81) 0.6 1.78 Infinitely large heat sink 20 16 12 8 4 3 With no heat sink 0 – 20 0 1.0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : DIP28H(500mil) Pin Assignment OUT1 28 F/R 27 IN3+ 26 IN325 IN2+ 24 IN223 IN1+ 22 IN121 GND1 20 S/S 19 FGIN+ FGIN- FGOUT 18 17 16 LD 15 LB11826 Top view 1 2 3 OUT2 OUT3 GND2 4 5 6 7 8 9 10 VCC VM VREG PWM CSD XI XO 11 12 INTOUT INTIN 13 14 POUT DOUT Truth Table Source F/R= L Sink IN1 F/R= H IN2 IN3 IN1 IN2 IN3 1 OUT2 → OUT1 H L H L H L 2 OUT3 →OUT1 H L L L H H 3 OUT3 → OUT2 H H L L L H 4 OUT1 → OUT2 L H L H L H 5 OUT1 → OUT3 L H H H L L 6 OUT2 → OUT3 L L H H H L The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation. fFG (servo) = fCLK/ = fCLK/512 No.7109-4/11 GND1 FGIN+ FGIN- XI Xtal OSC VREF FG RST VREG XO + - CLK IN (LB11825MOUT) + - FG AMP FGOUT S/S S/S VREG/2 BGP VREF VREG 5VREG PLL IN1 H LOGIC CSD CIRCUIT INT.OUT CSD COMP + H IN2 H IN3 HALL HYS AMP INT AMP + - DOUT INT.IN SPEED DISCRI F/R F/R POUT 1/512 LOCK DET LD LD CURR LIM GND2 DRIVER TSD PWM OSC Rf OUT3 OUT2 OUT1 VM VCC PWM + VCC LB11826 Block Diagram and Peripheral Circuits No.7109-5/11 LB11826 Pin Functions Pin No. Pin name 28 OUT1 Motor drive output pin. Pin function 1 OUT2 Connect the Schottky diode between the output - 2 OUT2 VCC. 3 GND2 Output GND pin. 5 VM Equivalent circuit VCC 300Ω VM 5 Power and output current detection pins of the output. Connect a low resistance (Rf) between this pin and VCC. 1 The output current is limited to the current value set 2 28 with IOUT = VRF/Rf. 3 4 VCC 6 VREG Power pin (Other than the output). Stabilized power supply output pin (5V output). VCC Connect a capacitor (about 0.1μF) between this pin and GND for stabilization. 6 7 PWM Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND. VREG This can be set to about 18kHz with C = 3900pF. 200Ω 7 2kΩ 8 CSD Pin to set the operation time of motor lock protection circuit. VREG Connection of a capacitor (about 10μF) between CSD and GND can set the protection operation time of about 3.3seconds. 300Ω 8 1kΩ Continued on next page. No.7109-6/11 LB11826 Continued from preceding page. Pin No. Pin name Pin function 9 XI Clock input pin, which enters the clock signal (1MHz 10 XO or less) to the XI pin via resistor (about 5.1kΩ). Equivalent circuit VREG Keep the XO pin open. 10 9 11 INTOUT Integrating amplifier output (speed control pin). VREG 40kΩ 11 PWM Comparator 12 INTIN Integrating amplifier input pin. VREG 300Ω 13 POUT PLL output pin. 12 VREG 300Ω 13 Continued on next page. No.7109-7/11 LB11826 Continued from preceding page. Pin No. Pin name 14 DOUT Pin function Equivalent circuit Speed discriminator output. VREG Accelerate : high, decelerate : low. 300Ω 15 LD Speed lock detection output. 14 VREG L when the motor speed is within the speed lock range (±6.25%). 15 Voltage resistance 30V max. 16 FGOUT FG amplifier output pin. VREG 40kΩ 16 FG schmitt comparator 17 18 FGINFGIN+ FG amplifier input pin. Connection of a capacitor (about 0.1μF) between VREG FGIN and GND causes initial reset to the logic 20kΩ circuit. FG Reset 18 300Ω 300Ω 17 20kΩ 19 S/S Start/stop control pin. Low : 0V to 1.5V VREG High : 3.5V to VREG H level when open. Hysteresis width about 0.5V. 22kΩ 2kΩ 20 GND1 19 GND pin (Other than the output). Continued on next page. No.7109-8/11 LB11826 Continued from preceding page. Pin No. 22 21 24 Pin name IN1+ IN1IN2+ 26 IN2IN3+ 25 IN3- 23 Pin function F/R VREG the input low state. It is recommended that the Hall signal has an amplitude of 100mVp-p (differential) or more. Connect a capacitor between the IN+ and IN- inputs if there is noise in the Hall sensor signals. 27 Equivalent circuit Hall amplifier input. IN+ > IN- is the input high state, and the reverse is Forward/reverse control pin. Low : 0V to 1.5V 21 23 25 300Ω 300Ω 22 24 26 VREG High : 3.5V to VREG H level when open. Hysteresis width about 0.5V. 22kΩ 2kΩ 27 LB11826 Description 1. Speed control circuit This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase error signal once for each cycle of FG. As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock frequency. fFG (servo) = fCLK/512 fCLK : Clock frequency This IC achieves variable speed control with ease when combined with LB11825M. 2. Output drive circuit This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky diode externally. 3. Current limiting circuit The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5Vtyp, Rf : current detector resistance) (that is, this circuit limits the peak current). Limiting operation includes decrease in the output on-duty to suppress the current. 4. Power save circuit This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given. 5. Reference clock This is entered from the external signal source (1MHz max) via a resistor (reference : about 5.1kΩ) in series with the XI pin. The XO pin is left open. Input signal source levels : Low-level voltage : 0 to 0.8V High-level voltage : 2.5 to 5.0V No.7109-9/11 LB11826 6. Speed lock range The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive output changes according to the speed error, causing control to keep the motor speed within the lock range. 7. PWM frequency PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin. fPWM ≈ 1/ (14,400 × C) It is recommended to keep the PWM frequency at 15k - 20kHz. 8. Hall input signal The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42mV max). Considering the effect of noise, the input with the amplitude of 100mV or more is recommended. 9. F/R changeover Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay attention to following points. • For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is necessary to prevent exceeding of the rated voltage (30V) due to rise of VCC voltage at a time of changeover (because the motor current returns instantaneously to the power supply). When this problem exists, increase the capacity of a capacitor between VCC and GND. • When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (2.5A). (F/R changeover at high motor speed is dangerous.) 10. Motor lock protection circuit A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked. When the LD output is “H” (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with the capacity of 10μF (variance about ±30%). Set time (s) ≈ 0.33 × C (μF) When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time, etc. Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock protection circuit is not to be used, connect the CSD pin to GND. When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to restart in the motor start transient condition.) Stop time (ms) ≥ 15 × C (μF) 11. Power supply stabilization This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is therefore necessary to connect a capacitor with a sufficient capacity between the VCC pin and GND for stabilization. When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power line is particularly readily oscillated. The larger capacity need be selected. 12. Constant of integrating amplifier parts Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange them by keeping the largest possible distance from the motor. No.7109-10/11 LB11826 ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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