C540U

C540U C541U 8-Bit CMOS Microcontroller tp :/ Se /ww mw ic .s on ie du me ct ns or .d / e/ User's Manual 10.97 ht C540U/C541U User’s Manual Revision History : Previous Releases : Page (previous version) Page (new version) 1997-10-01 Original Version Subjects (changes since last revision) Edition 1997-10-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. General Information C541U Table of Contents 1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.4 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 5 5.1 5.2 5.3 5.4 6 6.1 6.1.1 6.1.1.1 6.1.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.2 6.2.1 6.2.1.1 6.2.1.2 6.2.1.3 6.2.1.4 6.2.1.5 6.3 6.3.1 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . . . .4-3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 SSC Interface (C541U only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 Semiconductor Group I-1 General Information C541U Table of Contents 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.6.1 6.3.6.2 6.3.7 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.4.2.2.1 6.4.2.2.2 6.4.2.3 6.4.3 6.4.4 6.4.5 6.4.6 6.4.6.1 6.4.6.2 6.4.6.3 6.4.7 6.4.7.1 6.4.7.2 6.4.7.3 6.4.8 6.4.9 6.4.10 6.4.10.1 6.4.10.2 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 8 8.1 8.1.1 Page Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 Write Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27 USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-32 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-33 USB Memory Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34 Single Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 USB Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35 USB Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37 Dual Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-40 USB Memory Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-47 USB Memory Buffer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-48 Initialization of USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-52 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53 Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57 Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64 On-Chip USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-73 Detection of Connected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75 Detach / Attach Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Self-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Bus-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76 Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9 Interrupt Prioritiy Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Programmable Watchdog Timer (C541U only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2 Semiconductor Group I-2 General Information C541U Table of Contents 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.2.1 9.2.2.2 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.5 10.6 10.7 10.8 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 Page Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5 Functionality of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 Entering Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Exit from Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5 Entering Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 Exit from Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 Exit via Pin P3.2/INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 Exit via UBS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12 OTP Verify with Protection Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-4 AC Characteristics of Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12 OTP Verification Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16 USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-20 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 Semiconductor Group I-3 Introduction C540U / C541U 1 Introduction The C540U and C541U are members of the Siemens C500 family of 8-bit microcontrollers They are fully compatible to the standard 80C51 architecture. The C540U/C541U especially provide an on-chip USB module compliant to the USB specification, which is capable to operate either in low or full speed mode. The five endpoints can be easily controlled by the CPU via special function registers. Due to the on-chip USB transceiver circuits the C540U/C541U can be directly connected to the USB bus. Figure 1-1 shows the different functional units of the C540U/C541U and figure 1-2 shows the simplified logic symbol of the C540U/C541U. On-Chip Emulation Support Module Oscillator Watchdog Watchdog Timer SSC T0 RAM 256 x 8 Port 0 I/O Port 1 CPU I/O Power Saving Modes USB Module USB Transceiver D+ D- T1 OTP Prog. Memory C540U : 4 k x 8 C541U : 8 k x 8 Port 2 I/O Port 3 I/O The shaded units are not available in the C540U. MCA03373 Figure 1-1 C540U/C541U Functional Units Semiconductor Group 1-1 1997-10-01 Introduction C540U / C541U Listed below is a summary of the main features of the C541U : • • • • • • • • • • • • • • • • • Enhanced 8-bit C500 CPU – Full software/toolset compatible to standard 80C51/80C52 microcontrollers 12 MHz external operating frequency – 500 ns instruction cycle Built-in PLL for USB synchronization On-chip OTP program memory – C540U : 4K byte – C541U : 8K byte – Alternatively up to 64K byte external program memory – Optional memory protection Up to 64K byte external data memory 256 byte on-chip RAM Four parallel I/O ports – P-LCC-44 package : three 8-bit ports and one 6-bit port – P-SDIP-52 package : four 8-bit ports – LED current drive capability for 3 pins (10 mA) Two 16-bit timer/counters (C501 compatible) On-chip USB module – Compliant to USB specification – Full speed or low speed operation – Five endpoints : one bidirectional control endpoint four versatile programmable endpoints – Registers are located in special function register area – On-chip USB transceiver SSC synchronous serial interface (SPI compatible) (only C541U) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 1.5 MBaud transfer rate at 12 MHz operating frequency 7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels Enhanced fail safe mechanisms – Programmable watchdog timer (only C541U) – Oscillator watchdog Power saving modes – idle mode – software power down mode with wake-up capability through INT0 pin or USB On-chip emulation support logic (Enhanced Hooks Technology TM) P-LCC-44 and P-SDIP-52 packages Power supply voltage range : 4.0V to 5.5V Temperature Range : SAB-C540U TA = 0 to 70 °C SAB-C541U TA = 0 to 70 °C Semiconductor Group 1-2 1997-10-01 Introduction C540U / C541U V CC V SS XTAL2 XTAL1 ALE PSEN EA RESET D+ DC540U C541U Port 0 8-Bit Digital I / O Port 1 P-LCC-44 : 6-Bit Digital I / O P-SDIP-52 : 8-Bit Digital I / O Port 2 8-Bit Digital I / O Port 3 8-Bit Digital I / O MCL03374 Figure 1-2 Logic Symbol Semiconductor Group 1-3 1997-10-01 Introduction C540U / C541U 1.1 Pin Configuration This section describes the pin configrations of the C540U/C541U in the P-LCC-44 and P-SDIP-52 packages. P1.1 / LED1 P1.0 / LED0 DD+ V SSU V CCU P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 6 5 4 3 2 1 44 43 42 41 40 P1.2 / SCLK V CC V SS RESET P3.0 / LED2 P1.3 / SRI P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C540U C541U 18 19 20 21 22 23 24 25 26 27 28 P3.6 / WR P3.7 / RD XTAL2 XTAL1 V SS V CC P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 This pin functionality ist not available for the C540U. MCP03343 Figure 1-3 Pin Configuration P-LCC-44 Package (top view) Semiconductor Group 1-4 1997-10-01 Introduction C540U / C541U V CCU V SSU D+ DN.C. N.C. P1.0 / LED0 P1.1 / LED1 P1.2 / SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 N.C. P1.5 / SLS P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO P1.7 ALE PSEN N.C. N.C. P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 N.C. MCP03344 V CC V SS RESET P3.0 / LED2 P1.3 / SRI P1.6 P3.1 / DADD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD XTAL2 XTAL1 C540U C541U V SS V CC This pin functionality ist not available for the C540U. Figure 1-4 Pin Configuration P-SDIP-52 Package (top view) Semiconductor Group 1-5 1997-10-01 Introduction C540U / C541U 1.2 Pin Definitions and Functions This section describes all external signals of the C541U with its function. Table 1-1 Pin Definitions and Functions Symbol D+ 3 Pin Numbers P-LCC-44 P-SDIP-52 3 I/O USB D+ Data Line The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip). USB D- Data Line The pin D- can be directly connected to USB cable (transceiver is integrated on-chip). Port 1 is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasibidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC (C541U only). The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / LED0 LED0 output P1.1 / LED1 LED1 output P1.2 / SCLK SSC Master Clock Output / SSC Slave Clock Input (C541U only) P1.3 / SRI SSC Receive Input (C541U only) P1.4 / STO SSC Transmit Output (C541U only) P1.5 / SLS SSC Slave Select Inp. (C541U only) P1.6 (P-SDIP-52 only) P1.7 (P-SDIP-52 only) I/O*) Function D- 4 4 I/O P1.0 - P1.4 5 - 7, 7 - 9, 14, 41, I/O 12, 34, 44 51, 15, 40 5 6 7 12 34 44 – – *) I = Input O = Output 7 8 9 13 41 51 15 40 Semiconductor Group 1-6 1997-10-01 Introduction C540U / C541U Table 1-1 Pin Definitions and Functions Symbol RESET 10 Pin Numbers P-LCC-44 (cont’d) I/O*) Function I RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C540U/C541U. A small internal pulldown resistor permits power-on reset using only a capacitor connected to VCC . Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / LED2 LED2 output P3.1 / DADD Device attached input P3.2 / INT0 External interrupt 0 input / timer 0 gate control input External interrupt 1 input / P3.3 / INT1 timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory XTAL2 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. P-SDIP-52 12 P3.0 - P3.7 11, 13 - 19 13, 16 - 22 I/O XTAL2 20 23 – *) I = Input O = Output Semiconductor Group 1-7 1997-10-01 Introduction C540U / C541U Table 1-1 Pin Definitions and Functions Symbol XTAL1 21 Pin Numbers P-LCC-44 (cont’d) I/O*) Function – XTAL1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. P-SDIP-52 24 P2.0 - P2.7 24 - 31 28 - 35 I/O PSEN 32 38 O ALE 33 39 O *) I = Input O = Output Semiconductor Group 1-8 1997-10-01 Introduction C540U / C541U Table 1-1 Pin Definitions and Functions Symbol EA 35 Pin Numbers P-LCC-44 (cont’d) I/O*) Function I External Access Enable When held high, the C540U/C541U executes instructions from the internal ROM as long as the PC is less than 1000H for the C540U or less than 2000H for the C541U. When held low, the C540U/ C541U fetches all instructions from external program memory. For the C540U-L/C541U-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Supply voltage for the on-chip USB transceiver circuitry. Ground (0V) for the on-chip USB transceiver circuitry. Supply voltage for ports and internal logic circuitry during normal, idle, and power down mode. Ground (0V) for ports and internal logic circuitry during normal, idle, and power down mode. P-SDIP-52 42 P0.0 - P0.7 44 - 36 50 - 43 I/O VCCU VSSU VCC 1 2 8, 23 1 2 10, 26 – – – VSS 9, 22 11, 25 – *) I = Input O = Output Semiconductor Group 1-9 1997-10-01 Introduction C540U / C541U Semiconductor Group 1-10 1997-10-01 Fundamental Structure C540U / C541U 2 Fundamental Structure The C540U/C541U is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining the typical architectural characteristics of the C501, the C541U incorporates a SSC synchronous serial interface, a versatile USB module as well as some enhancements in the Fail Save Mechanism Unit. Functionally, the C540U is a subset of the C541U with a smaller OTP program memory and without the SSC interface and the watchdog timer. Figure 2-1 shows a block diagram of the C540U/C541U. Oscillator Watchdog X TAL2 XTAL1 ALE PSEN EA RESET Progr. Watchdog Timer (C541U only) Timer 0 Timer 1 CPU OSC & Timing RAM 256 x 8 OTP Memory 4k x 8 (C540U) 8k x 8 (C541U) Emulation Support Logic Port 0 Port 0 8-Bit Digit. I/O Port 1 1) 6- / 8-Bit Digit. I/O Port 2 8-Bit Digit. I/O Port 3 8-Bit Digit. I/O Port 1 SSC (SPI) Interface (C541U only) Transceiver PLL USB Module Port 2 D+ D- Port 3 Interrupt Unit 1) C540U C541U MCB03345 P -LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port Figure 2-1 Block Diagram of the C540U/C541U Semiconductor Group 2-1 1997-10-01 Fundamental Structure C540U / C541U 2.1 CPU The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires six oscillator cycles (this number of oscillator cycles differs from other members of the C500 microcontroller family). The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set. The C541U uses five addressing modes: direct access, immediate, register, register indirect access, and for accessing the external data or program memory portions a base register plus index-register indirect addressing. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz clock, 58% of the instructions execute in 500 ns. The CPU (Central Processing Unit) of the C540U/C541U consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jumpif-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Accumulator A CC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Semiconductor Group 2-2 1997-10-01 Fundamental Structure C540U / C541U Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Semiconductor Group 2-3 1997-10-01 Fundamental Structure C540U / C541U 2.2 CPU Timing The C540U/C541U has no clock prescaler. Therefore, a machine cycle of the C540U/C541U consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Semiconductor Group 2-4 1997-10-01 Fundamental Structure C540U / C541U S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 OSC (XTAL2) ALE Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) S5 S6 Read Next Opcode Again (a) 1-Byte, 1-Cycle Instruction, e. g. INC A Read Opcode S1 S2 S3 S4 Read 2nd Byte S5 S6 Read Next Opcode (b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA Read Opcode S1 S2 S3 S4 Read Next Opcode (Discard) Read Next Opcode Again S4 S5 S6 S5 S6 S1 S2 S3 (c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR Read Opcode (MOVX) S1 S2 S3 S4 Read Next Opcode (Discard) S5 ADDR S6 S1 Read Next Opcode Again No Fetch No Fetch No ALE S2 DATA MCD03287 S3 S4 S5 S6 (d) MOVX (1-Byte, 2-Cycle) Access of External Memory Figure 2-2 Fetch Execute Sequence Semiconductor Group 2-5 1997-10-01 Fundamental Structure C540U / C541U Semiconductor Group 2-6 1997-10-01 Memory Organization C540U / C541U 3 Memory Organization The C540U/C541U CPU manipulates operands in the following four address spaces: – – – – – 8 or 4 KByte on-chip OTP program memory Totally up to 64 Kbyte internal/external program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area Figure 3-3 illustrates the memory address spaces of the C540U/C541U. FFFF H FFFF H External External Indirect Addr. Internal RAM 2000 H 1) 1FFF H 1) Internal (EA = 1) External (EA = 0) 0000 H "Code Space" 0000 H "External Data Space" Internal RAM 00 H "Internal Data Space" MCD03375 FF H Direct Addr. Special Function Register FF H 80 H 7F H 80 H 1) For the C504U the int. / ext. program memory boundary is at 0FFF H / 1000 H . Figure 3-3 C540U/C541U Memory Map Semiconductor Group 3-1 1997-10-01 Memory Organization C540U / C541U 3.1 Program Memory, "Code Space" The C541U has 8 Kbyte (C540U : 4 Kbyte) of OTP program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C541U executes program code out of the internal OTP program memory unless the program counter address exceeds 1FFFH (C540U : 0FFFH). Address locations 2000H through FFFFH (C540U : 1000H through 0FFFH) are then fetched from the external program memory. If the EA pin is held low, the C540U/C541U fetches all instructions from the external 64K byte program memory. 3.2 Data Memory, "Data Space" The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by MOVX instructions that use a 16-bit or an 8-bit address. Note :The registers of the USB module are accessed through special function registers in the SFR area. 3.3 General Purpose Registers The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. Semiconductor Group 3-2 1997-10-01 Memory Organization C540U / C541U 3.4 Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C540U/C541U (PCON1) is located in the mapped special function register area. All other SFRs are located in the standard special function register area. For accessing PCON1 in the mapped special function register area, bit RMAP in special function register SYSCON must be set. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX10XXXXB LSB 0 – SYSCON 6 – 5 EALE 4 RMAP 3 – 2 – 1 – The functions of the shaded bits are not described in this section. Bit RMAP Function Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area (PCON1) is enabled. As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U are listed in table 3-2 and table 3-3. In table 3-2 they are organized in groups which refer to the functional blocks of the C540U/C541U. Table 3-3 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group 3-3 1997-10-01 Memory Organization C540U / C541U Table 3-2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP VR0 VR1 VR2 SYSCON IEN0 IEN1 IP0 IP1 ITCON P0 P1 P2 P3 TCON TH0 TH1 TL0 TL1 TMOD SSCCON STB SRB SCF SCIEN SSCMOD Name Accumulator B Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Version Register 0 Version Register 1 Version Register 2 System Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 External Interrupt Trigger Condition Register Port 0 Port 1 Port 2 Port 3 Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register Watchdog Timer Control Register Watchdog Timer Reload Register Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H FCH FDH FEH B1H A8H1) A9H B8H 1) B9H) 9AH 80H 1) 90H 1) A0H 1) B0H 1) 88H 1) 8CH 8DH 8AH 8BH 89H 93H 1) 94H 95H ABH 1) ACH 96H C0H 1) 86H 00H 00H 00H 00H 00H 07H C5H C1H YYH 3) XX10XXXXB 2) 0XXX0000B 2) XXXXX000B 2) XXXX0000B 2) XXXXX000B 2) XXXX1010B 2) FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H 07H XXH 2) XXH 2) XXXXXX00B 2) XXXXXX00B 2) 00H XXXX0000B 2) 00H Interrupt System Ports Timer 0 / Timer 1 SSC Interface (C541U only) Watchdog WDCON (C541U WDTREL only) 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01H for the first step) 4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 3-4 1997-10-01 Memory Organization C540U / C541U Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Pow. Sav. Modes USB Module Symbol PCON PCON1 EPSEL USBVAL ADROFF GEPIR DCR DPWDR DIER DIRR FNRL FNRH EPBCn 1) EPBSn 1) EPIEn 1) EPIRn 1) EPBAn 1) EPLENn 1) Name Power Control Register Power Control Register 1 USB Endpoint Select Register USB Data Register USB Address Offset Register USB Global Endpoint Interrupt Request Reg. USB Device Control Register USB Device Power Down Register USB Device Interrupt Control Register USB Device Interrupt Request Register USB Frame Number Register, Low Byte USB Frame Number Register, High Byte USB Endpoint n Buffer Control Register USB Endpoint n Buffer Status Register USB Endpoint n Interrupt Enable Register USB Endpoint n Interrupt Request Register USB Endpoint n Base Address Register USB Endpoint n Buffer Length Register Address Contents after Reset 87H 88H 4) D2H D3H D4H D6H C1H C2H C3H C4H C6H C7H C1H C2H C3H C4H C5H C6H X00X0000B 2) 0XX0XXXXB 2) 80H 00H 00H 2) 00H 000X0000B 00H 00H 00H XXH 00000XXXB 00H 20H 00H 10H 3) 00H 0XXXXXXXB 1) These register are multiple registers (n=0-4) with the same SFR address; selection of register “n“ is done by SFR EPSEL. 2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. 3) The reset value of EPIR0 is 11H. Semiconductor Group 3-5 1997-10-01 Memory Organization C540U / C541U Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Reset Bit 7 Value1) 80H 2) P0 81H 82H 83H 86H 4) 87H SP DPL DPH FFH 07H 00H .7 .7 .7 .7 WDT PSEL – TF1 Bit 6 .6 .6 .6 .6 .6 PDS TR1 Bit 5 .5 .5 .5 .5 .5 IDLS TF0 – M1 .5 .5 .5 .5 SLS MSTR .5 .5 0 – .5 – – – Bit 4 .4 .4 .4 .4 .4 – TR0 WS M0 .4 .4 .4 .4 STO CPOL .4 .4 0 – .4 – – – Bit 3 .3 .3 .3 .3 .3 GF1 IE1 – GATE .3 .3 .3 .3 SRI CPHA .3 .3 0 I1ETF .3 ET1 – – Bit 2 .2 .2 .2 .2 .2 GF0 IT1 – C/T .2 .2 .2 .2 SCLK BRS2 .2 .2 0 I1ETR .2 EX1 EUDI – Bit 1 .1 .1 .1 .1 .1 PDE IE0 – M1 .1 .1 .1 .1 LED1 BRS1 .1 .1 0 I0ETF .1 ET0 EUEI Bit 0 .0 .0 .0 .0 .0 IDLE IT0 – M0 .0 .0 .0 .0 LED0 BRS0 .0 .0 LSBSM I0ETR .0 EX0 ESSC 00H WDTREL 00H X00X0000B 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH PCON 88H 2) TCON 88H 2) 3) PCON1 TMOD TL0 TL1 TH0 TH1 EWPD – GATE .7 .7 .7 .7 .7 SCEN .7 .7 – .7 EA – – C/T .6 .6 .6 .6 .6 TEN .6 .6 – .6 – – – 89H 8AH 8BH 8CH 8DH 90H2) P1 93H 4) SSCCON 07H XXH 94H 4) STB 95H 9AH 4) SRB 96H 4) XXH SSCMOD 00H ITCON XXXX1010B FFH 0XXX0000B XXXXX000B XXXXXX00B LOOPB TRIO A0H2) P2 A8H2) IEN0 A9H IEN1 ABH SCF 4) WCOL TC 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is only available in the C541U. Semiconductor Group 3-6 1997-10-01 Memory Organization C540U / C541U Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Reset Bit 7 Value1) ACH SCIEN 4) Bit 6 – WR – – – – Bit 5 – T1 EALE – – – Bit 4 – T0 RMAP – – – Bit 3 – INT1 – PT1 – Bit 2 – INT0 – PX1 PUDI Bit 1 Bit 0 XXXXXX00B FFH – RD – – – – WCEN TCEN DADD – PT0 PUEI LED2 – PX0 PSSC 4) B0H2) P3 B1H SYSCON XX10XXXXB XXXX0000B XXXX0000B XXXX0000B 00H B8H2) IP0 B9H C0H 2) IP1 WDCON OWDS WDTS WDT SWDT C1H to C7H D0H 2) USB Device and Endpoint Register definition see table 3-3 CY EPS7 .7 7) PSW EPSEL AC 0 .6 0 0 .6 .6 1 1 .6 F0 0 .5 AO5 0 .5 .5 0 0 .5 RS1 0 .4 AO4 EPI4 .4 .4 0 0 .4 RS0 0 .3 AO3 EPI3 .3 .3 0 0 .3 OV EPS2 .2 AO2 EPI2 .2 .2 1 0 .2 F1 EPS1 .1 AO1 EPI1 .1 .1 0 0 .1 P EPS0 .0 AO0 EPI0 .0 .0 1 1 .0 D2H D3H D4H 80H USBVAL 00H ADROFF 00H D6H GEPIR 00H E0H2) ACC 00H F0H2) B 00H C5H C1H 6) 0 0 .7 .7 1 1 .7 FCH VR0 3) 5) FDH VR1 3) 5) FEH 3) 5) VR2 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR respectively bit is only available in the C541U. 5) These are read-only registers 6) The content of this SFR varies with the actual of the step C541U (e.g. 01H for the first step) 7) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. Semiconductor Group 3-7 1997-10-01 Memory Organization C540U / C541U Table 3-4 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) Addr Register Reset Value C1H DCR 000X. 0000B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EPSEL = 1XXX.XXXXB Device Registers SPEED 0 SE0IE SE0I DA 0 DAIE DAI SWR 0 DDIE DDI SUSP 0 SBIE SBI DINIT 0 SEIE SEI RSM 0 STIE STI UCLK TPWD SUIE SUI PCLK RPWD SOFIE SOFI C2H DPWDR 00H C3H DIER 00H C4H DIRR C5H reserved C6H FNRL C7H FNRH 00H FNR7 XXH 0 0000. 0XXXB FNR6 0 FNR5 0 FNR4 0 FNR3 0 FNR2 FNR10 FNR1 FNR9 FNR0 FNR8 EPSEL = 0XXX.X000B C1H EPBC0 C2H EPBS0 C3H EPIE0 C4H EPIR0 C5H EPBA0 00H 20H 00H 11H Endpoint 0 Registers STALL0 0 UBF0 AIE0 ACK0 CBF0 NAIE0 NACK0 0 L06 0 DIR0 RLEIE0 RLE0 0 L05 GEPIE0 ESP0 SOFDE0 INCE0 0 DBM0 SETRD0 SETWR0 CLREP0 DONE0 DNRIE0 NODIE0 EODIE0 SODIE0 DNR0 A06 L03 NOD0 A05 L02 EOD0 A04 L01 SOD0 A03 L00 – – 0 L04 PAGE0 00H C6H EPLEN0 0XXX. 0 XXXXB C7H reserved EPSEL = 0XXX.X001B C1H EPBC1 C2H EPBS1 C3H EPIE1 C4H EPIR1 C5H EPBA1 00H 20H 00H 10H Endpoint 1 Registers STALL1 0 UBF1 AIE1 ACK1 CBF1 NAIE1 NACK1 0 L16 0 DIR1 RLEIE1 RLE1 0 L15 GEPIE1 ESP1 SOFDE1 INCE1 0 DBM1 SETRD1 SETWR1 CLREP1 DONE1 DNRIE1 NODIE1 EODIE1 SODIE1 DNR1 A16 L13 NOD1 A15 L12 EOD1 A14 L11 SOD1 A13 L10 – – 0 L14 PAGE1 00H C6H EPLEN1 0XXX. 0 XXXXB C7H reserved Semiconductor Group 3-8 1997-10-01 Memory Organization C540U / C541U Table 3-4 Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont’d) Addr Register Reset Value EPSEL = 0XXX.X010B C1H EPBC2 C2H EPBS2 C3H EPIE2 C4H EPIR2 C5H EPBA2 00H 20H 00H 10H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Endpoint 2 Registers STALL2 0 UBF2 AIE2 ACK2 CBF2 NAIE2 NACK2 0 L62 0 DIR2 RLEIE2 RLE2 0 L52 GEPIE2 ESP2 SOFDE2 INCE2 0 DBM2 SETRD2 SETWR2 CLREP2 DONE2 DNRIE2 NODIE2 EODIE2 SODIE2 DNR2 A62 L32 NOD2 A52 L22 EOD2 A42 L12 SOD2 A32 L02 – – 0 L42 PAGE2 00H C6H EPLEN2 0XXX. 0 XXXXB C7H reserved EPSEL = 0XXX.X011B C1H EPBC3 C2H EPBS3 C3H EPIE3 C4H EPIR3 C5H EPBA3 00H 20H 00H 10H Endpoint 3 Registers STALL3 0 UBF3 AIE3 ACK3 CBF3 NAIE3 NACK3 0 L63 0 DIR3 RLEIE3 RLE3 0 L53 GEPIE3 ESP3 SOFDE3 INCE3 0 DBM3 SETRD3 SETWR3 CLREP3 DONE3 DNRIE3 NODIE3 EODIE3 SODIE3 DNR3 A63 L33 NOD3 A52 L23 EOD3 A43 L13 SOD3 A33 L03 – – 0 L43 PAGE3 00H C6H EPLEN3 0XXX. 0 XXXXB C7H reserved EPSEL = 0XXX.X100B C1H EPBC4 C2H EPBS4 C3H EPIE4 C4H EPIR4 C5H EPBA4 00H 20H 00H 10H Endpoint 4 Registers STALL4 0 UBF4 AIE4 ACK4 CBF4 NAIE4 NACK4 0 L64 0 DIR4 RLEIE4 RLE4 0 L54 GEPIE4 ESP4 SOFDE4 INCE4 0 DBM4 SETRD4 SETWR4 CLREP4 DONE4 DNRIE4 NODIE4 EODIE4 SODIE4 DNR4 A64 L34 NOD4 A54 L24 EOD4 A44 L14 SOD4 A34 L04 – –4 0 L44 PAGE4 00H C6H EPLEN4 0XXX. 0 XXXXB C7H reserved Semiconductor Group 3-9 1997-10-01 Memory Organization C540U / C541U Semiconductor Group 3-10 1997-10-01 External Bus Interface C540U / C541U 4 External Bus Interface The C540U/C541U allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture. 4.1 Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). 4.1.1 Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods. Semiconductor Group 4-1 1997-10-01 External Bus Interface C540U / C541U a) S1 ALE One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN RD PCH OUT INST. IN PCL OUT PCL OUT valid b) S1 ALE INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN PCL OUT PCL OUT valid PCH OUT INST. IN (A) without MOVX P2 P0 One Machine Cycle S2 S3 S4 S5 S6 S1 One Machine Cycle S2 S3 S4 S5 S6 PSEN (B) with MOVX PCH OUT INST. IN PCL OUT PCL OUT valid INST. IN DPL or Ri valid DPH OUT OR P2 OUT DATA IN PCL OUT PCL OUT valid PCH OUT INST. IN MCT03220 RD P2 P0 Figure 4-1 External Program Memory Execution Semiconductor Group 4-2 1997-10-01 External Bus Interface C540U / C541U 4.1.2 Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. 4.1.3 External Program Memory Access The external program memory is accessed under two conditions: – - whenever signal EA is active (low); or – - whenever the program counter (PC) content is greater than 7FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). 4.2 PSEN, Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b). 4.3 Overlapping External Data and Program Memory Spaces In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C540U/C541U the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle. Semiconductor Group 4-3 1997-10-01 External Bus Interface C540U / C541U 4.4 ALE, Address Latch Enable The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 4-1 b). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. The C540U/C541U allows to switch off the ALE output signal. If the internal ROM is used (EA=1) and ALE is switched off by EALE=0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 0FFFH for the C540U or greater than 1FFFH for the C541U (external code memory fetches). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H – Reset Value : XX10XXXXB LSB 0 – SYSCON 6 – 5 EALE 4 RMAP 3 – 2 – 1 – The function of the shaded bit is not described in this section. Bit – EALE Function Not implemented. Reserved for future use. Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions and code memory accesses with an address greater 0FFFH (C540U) or greater 1FFFH. EALE = 1 : ALE generation is enabled If EA=0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. Semiconductor Group 4-4 1997-10-01 External Bus Interface C540U / C541U 4.5 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensures that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1) “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 4-5 1997-10-01 External Bus Interface C540U / C541U Semiconductor Group 4-6 1997-10-01 Reset / System Clock C540U / C541U 5 5.1 Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C540U/C541U allows for an easy automatic startup at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power down mode is to be terminated. Additional to the hardware reset, which is applied externally to the device, there are two internal reset sources, the watchdog timer (C541U only) and the oscillator watchdog. This chapter deals only with the external hardware reset. The RESET input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated or driven externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the RESET pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained when VCC is applied by connecting the RESET pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Semiconductor Group 5-1 1997-10-01 Reset / System Clock C540U / C541U VCC + a) C540U C541U RESET b) C540U C541U RESET & VCC VCC + c) C540U C541U RESET MCD03376 Figure 5-3 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished the port latches of ports 0 to 3 are set to FFH. This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1 and 3) output a one (1). Port 2 lines output a zero (or one) after reset, if EA is held low (or high). The content of the internal RAM of the C540U/C541U is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off. A reset operation of the USB module in the C540U/C541U can only be achieved under software control. A hardware reset operation puts only the internal CPU interface of the USB module and its MMU into a well defined reset state. The software reset, which must be executed after a hardware reset, is initiated by setting bit SWR in SFR DCR by software. Bit SWR is reset automatically by hardware when the software reset operation of the USB module is finished. Further, with the reset of bit SWR, bit DINIT in DCR is set indicating the CPU that it has to initialize the endpoints of USB module. Semiconductor Group 5-2 1997-10-01 Reset / System Clock C540U / C541U 5.2 Fast Internal Reset after Power-On The C540U/C541U uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C540U/C541U the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-4). Under worst case conditions (fast VCC rise time - e.g. 1 µs, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : – Typ.: – Max.: 18 µs 34 µs The RC oscillator will already run at a VCC below 4.0V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-4, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-4, III). However, an externally applied reset still remains active (figure 5-4, IV) and the device does not start program execution (figure 5-4, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – – Termination of software power down mode Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-4). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficent in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin. Semiconductor Group 5-3 1997-10-01 Semiconductor Group 5-4 1997-10-01 Figure 5-4 Power-On Reset of the C541U Ports Undef. RESET On-Chip Osc. RC Osc. V CC RESET Ι ΙΙ Clock from RC-Oscillator; RESET at Ports ΙΙΙ On-Chip Osc. starts; Final RESET Sequence by Osc.-WD; (max. 768 RC Clock Cycles) ΙV Port remains in RESET because of active ext. RESET Signal V Reset / System Clock C540U / C541U Power On; undef. Ports typ. 18 µ s max. 34 µ s Start of Program Execution MCT02627 Reset / System Clock C540U / C541U 5.3 Hardware Reset Timing This section describes the timing of the hardware RESET signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When RESET is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this time the C540U/C541U remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external program memory) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-5 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. One Machine Cycle S4 S5 S6 S1 P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 RESET P0 PCL OUT PCH OUT Inst. in PCL OUT PCH OUT P2 ALE MCT02092 Figure 5-5 CPU Timing after Reset Semiconductor Group 5-5 1997-10-01 Reset / System Clock C540U / C541U 5.4 Oscillator and Clock Circuit The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-6. The crystal oscillator generates the system clock for the microcontroller. The USB module can be provided with the following clocks : – Full speed operation : 48 MHz with a data rate of 12 Mbit/s – Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s The low speed clock is generated by a dividing the system clock by 2. The full speed clock is generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock. XTAL1 12 MHz XTAL2 Pin Pin Crystal 12 MHz Oscillator System Clock of the Microcontroler Divider by 2 6 MHz PLL x4 48 MHz 1 0 Enable PCLK DCR.0 to USB Module SPEED DCR.7 UCLK DCR.1 MCB03377 C540U / C541U Figure 5-6 Block Diagram of the Clock Generation Circuitry In low speed mode the PLL is not required. Therefore, the PLL should be always disabled in low speed mode. This also reduces the power consumption and the EMC of the C540U/C541U when used in low speed mode. Note: For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The microcontroller (except the USB module) is capaable to operate down to 2 MHz Semiconductor Group 5-6 1997-10-01 Reset / System Clock C540U / C541U After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module : – Full speed mode USB PLL is switched on by setting bit PCLK waiting 3 ms for PLL being locked setting bit UCLK setting bit UCLK only – Low speed mode The switch-on procedure after hardware reset assures a proper operation of the USB clock system. A software reset operation of the USB module must follow this clock system switch-on procedure. Details of the software reset operation are described in chapter 6.??. XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-7 shows the recommended oscillator circuit. C XTAL2 C540U C541U XTAL1 C = 20 pF 10 pF for crystal operation MCS03424 12 MHz C Figure 5-7 Recommended Crystal Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-8). lt operates in fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. Semiconductor Group 5-7 1997-10-01 Reset / System Clock C540U / C541U To Internal Timing Circuitry XTAL2 12 MHz XTAL1 C540U C541U C1 C2 MCD03395 Figure 5-8 On-Chip Oscillator Circuiry To drive the C540U/C541U with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-9. XTAL2 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL1. V CC N.C. C540U C541U XTAL2 External Clock Signal XTAL1 MCD03396 Figure 5-9 External Clock Source Semiconductor Group 5-8 1997-10-01 On-Chip Peripheral Components C540U / C541U 6 On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C540U/C541U except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package port 1 is a 6-bit I/O port only. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the capability of driving external LEDs in the output low state. Semiconductor Group 6-1 1997-10-01 On-Chip Peripheral Components C540U / C541U 6.1.1 Port Structures The C540U/C541U allows for digital I/O on 30 lines (P-LCC-44) or 32 lines (P-SDIP-52) grouped into 4 bidirectional 8-/6-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P3 are performed via their corresponding special function registers P0 to P3. Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 4 I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P3) activate the "read-latch" signal, while others activate the "read-pin" signal. Read Latch Int. Bus Write to Latch D Port Latch CLK Q Port Driver Circuit Port Pin Q MCS01822 Read Pin Figure 6-10 Basic Structure of a Port Circuitry Semiconductor Group 6-2 1997-10-01 On-Chip Peripheral Components C540U / C541U Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-11). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-11: Q=0), which turns off the output driver FET n1. Then, for ports 1, 2 and 3, the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current (IIL or ITL). For this reason these ports are sometimes called "quasi-bidirectional". Read Latch VCC Internal Pull Up Arrangement Q Bit Latch CLK Pin Int. Bus Write to Latch D Q n1 MCS01823 Read Pin Figure 6-11 Basic Output Driver Circuit of Ports 1, 2, and 3 Semiconductor Group 6-3 1997-10-01 On-Chip Peripheral Components C540U / C541U In fact, the pullups mentioned before and included in figure 6-11 are pullup arrangements as shown in figure 6-12. One n-channel pulldown FET and three pullup FETs are used: Delay = 1 State VCC =1 _