CYW305OXCT

W305B Frequency Controller with System Recovery for Intel® Integrated Core Logic Features • Thirteen copies of SDRAM clock • Single chip FTG solution for Intel Solano/810E/810 • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog timer time-out • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte read/write and block read/write operations to simplify system BIOS development • Vendor ID and Revision ID support • Eight copies of PCI clock • One copy of synchronous APIC clock • Three copies of 66-MHz outputs • Three copies of 48-MHz outputs • One copy of double strength 14.31818-MHz reference clock • One RESET output for system recovery • SMBus interface for turning off unused clocks Key Specifications CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter:................................................... 500 ps • Programmable drive strength for SDRAM and PCI output clocks CPU, 3V66 Output Skew: ........................................... 175 ps • Programmable output skew between CPU, AGP, PCI and SDRAM PCI Output Skew: ....................................................... 500 ps • Maximized EMI suppression using Cypress’s Spread Spectrum Technology CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns • Low jitter and tightly controlled clock skew • Two copies of CPU clock SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns PCI to APIC Skew..................................................... ± 0.5 ns Pin Configuration [1] Block Diagram VDDQ3 X1 X2 REF2X/FS3 XTAL OSC PLL REF FREQ VDDQ2 SMBus Logic CPU0:1 2 APIC (FS0:4) VDDQ3 3 PLL 1 3V66_0:2 PCI0/FS0 PCI1/FS1 PCI2/FS2 5 PCI3:7 SDRAM0:12 13 RST# VDDQ3 48MHz PLL2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 W305B SDATA SCLK Divider, Delay, and Phase Control Logic GND VDDQ3 REF2X/FS3^ X1 X2 VDDQ3 3V66_0 3V66_1 3V66_2 GND PCI0/FS0^ PCI1/FS1^ PCI2/FS2^ GND PCI3 PCI4 VDDQ3 PCI5 PCI6 PCI7 GND 48MHz 48MHz/FS4^ 24_48MHz/SEL24_48MHz#* VDDQ3 SDATA GND VDDQ3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 APIC GND VDDQ2 CPU0 CPU1 GND SDRAM0 SDRAM1 SDRAM2 VDDQ3 GND SDRAM3 SDRAM4 SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 SDRAM10 VDDQ3 GND SDRAM11 SDRAM12 RST# SCLK 48MHz/FS4 /2 24_48MHz/SEL24_48MHz# 1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH or LOW. ........................ Document #: 38-07262 Rev. *B Page 1 of 20 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com W305B Pin Definitions Pin No. Pin Type REF2X/FS3 3 I/O X1 4 I Crystal Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 O Crystal Output. An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI0/FS0 11 I/O PCI Clock 0/Frequency Selection 0. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI1/FS1 12 I/O PCI Clock 1/Frequency Selection 1. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI2/FS2 13 I/O PCI Clock 2/Frequency Selection 2. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 15, 16, 18, 19, 20 O PCI Clock 3 through 7. 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via SMBus interface. 7, 8, 9 O 66-MHz Clock Output. 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 5). Pin Name PCI3:7 3V66_0:2 Pin Description Reference Clock with 2x Drive/Frequency Select 3. 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 5. 48MHz 22 O 48MHz. 3.3V 48-MHz non-spread spectrum output. 48MHz/FS4 23 I/O 48-MHz Output/Frequency Selection 4. 3.3V 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 24_48MHz/SEL24 _48MHz# 24 I/O 24- or 48-MHz Output/Select 24 or 48MHz. 3.3V 24 or 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine the output frequency for 24_48MHz output. RST# 30 CPU0:1 Reset#. Open-drain RESET# output. O (open-d rain) 52, 51 O 49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35, 32, 31 O APIC 55 O Synchronous APIC Clock Outputs. Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. SDATA 26 I/O Data pin for SMBus circuitry. SCLK 29 I Clock pin for SMBus circuitry. VDDQ3 2, 6, 17, 25, 28, 34, 40, 46 P 3.3V Power Connection. Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. VDDQ2 53, 56 P 2.5V Power Connection. Power supply for APIC and CPU output buffers. Connect to 2.5V. 1, 10, 14, 21, 27, 33, 39, 45, 50, 54 G Ground Connections. Connect all ground pins to the common system ground plane. SDRAM0:12, GND CPU Clock Outputs. Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM Clock Outputs. 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 5). ........................ Document #: 38-07262 Rev. *B Page 2 of 20 W305B Output Strapping Resistor Series Termination Resistor Clock Load W305B Power-on Reset Timer Output Buffer Hold Output Low Output Three-state Q 10 k D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Overview The W305B is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic. Functional Description I/O Pin Operation Upon power-up the power on strap option pins act as a logic input. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. 10 ns 0 ns Offsets Among Clock Signal Groups Figure 2, Figure 3, and Figure 4 represent the phase relationship among the different groups of clock outputs from W305B under different frequency modes. 30 ns 40 ns CPU 66 Period CPU 66-MHz SDRAM 100-MHz 3V66 66-MHz 20 ns After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. SDRAM 100 Period Hub-PCI PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 16.6-MHz Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock) ........................ Document #: 38-07262 Rev. *B Page 3 of 20 W305B 10 ns 0 ns 20 ns 30 ns 40 ns CPU 100 Period CPU 100-MHz SDRAM 100 Period SDRAM 100-MHz 3V66 66-MHz Hub-PC PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC16.6-MHz Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock) 0 ns 10 ns 20 ns 30 ns Cycle Repeats CPU 133-MHz SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz APIC 16.6-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM) ........................ Document #: 38-07262 Rev. *B Page 4 of 20 40 ns W305B 0 ns 10 ns 20 ns 30 ns 40 ns Cycle Repeat CPU 133-MHz SDRAM 133MHz 3V66 66-MHz PCI 33-MHz APIC 16.6-MHz REF 14.318-MHz USB 48-MHz DOT 48-MHz Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM) Serial Data Interface The W305B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word write and byte read operations, system controller can access individual indexed byte. The offset of the indexed byte is encoded in the command code. The definition for the command code is given in Table 1. Table 1. Command Code Definition Bit Descriptions 7 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation 6:0 Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at ‘0000000’. Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bit Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bit 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bit ‘00000000’ stands for block operation 11:18 Command Code – 8 bit ‘00000000’ stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits 46 Acknowledge from slave ... Data Byte N/Slave Acknowledge... ........................ Document #: 38-07262 Rev. *B Page 5 of 20 21:27 Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 38 39:46 Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits W305B Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit ... Description Data Byte N – 8 bits ... Acknowledge from slave ... Stop Block Read Protocol Bit 47 48:55 56 Description Acknowledge Data byte from slave – 8 bits Acknowledge ... Data bytes from slave/Acknowledge ... Data byte N from slave – 8 bits ... Not Acknowledge ... Stop Table 3. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 Description Start Word Read Protocol Bit 1 Slave address – 7 bit Write Acknowledge from slave Command Code – 8 bit ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low– 8 bits Acknowledge from slave 2:8 Description Start Slave address – 7 bit 9 Write 10 Acknowledge from slave 11:18 19 20 21:27 Command Code – 8 bit ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Data byte high – 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38 Stop 30:37 38 39:46 Data byte low from slave – 8 bits Acknowledge Data byte high from slave – 8 bits 47 NOT acknowledge 48 Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description Start Slave address – 7 bit Byte Read Protocol Bit 1 2:8 Description Start Slave address – 7 bit 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bit ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bit ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop ........................ Document #: 38-07262 Rev. *B Page 6 of 20 21:27 28 Slave address – 7 bits Read W305B Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Byte Read Protocol Description Bit 29 30:37 Description Acknowledge from slave Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop W305B Serial Configuration Map Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0 The serial bits will be read by the clock driver in the following order: All unused register bits (reserved and N/A) should be written to a “0” level. Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 All register bits labeled “Initialize to 0” must be written to zero during initialization. Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register 0 Bit Pin# Name Default Description Bit 7 - SEL4 0 See Table 5 Bit 6 - SEL3 0 See Table 5 Bit 5 - SEL2 0 See Table 5 Bit 4 - SEL1 0 See Table 5 Bit 3 - SEL0 0 See Table 5 Bit 2 - Spread Select2 0 ‘000’ = Normal (spread off) Bit 1 - Spread Select1 0 ‘001’ = Test Mode Bit 0 - Spread Select0 0 ‘010’ = Reserved ‘011’ = Three-Stated ‘100’ = –0.5% ‘101’ = ±0.5% ‘110’ = ±0.25% ‘111’ = ±0.38% Byte 1: Control Register 1 Bit Pin# Bit 7 23 Name Latched FS4 input Default X Description Latched FS[4:0] inputs. These bits are read only. Bit 6 3 Latched FS3 input X Bit 5 13 Latched FS2 input X Bit 4 12 Latched FS1 input X Bit 3 11 Latched FS0 input X Bit 2 - Reserved 0 Reserved Bit 1 3 REF2X 1 (Active/Inactive) Bit 0 - Reserved 0 Reserved Byte 2: Control Register 2 Bit Pin# Name Default Description Bit 7 20 PCI7 1 (Active/Inactive) Bit 6 19 PCI6 1 (Active/Inactive) Bit 5 18 PCI5 1 (Active/Inactive) Bit 4 16 PCI4 1 (Active/Inactive) ........................ Document #: 38-07262 Rev. *B Page 7 of 20 W305B Byte 2: Control Register 2 (continued) Bit Pin# Name Default Description Bit 3 15 PCI3 1 (Active/Inactive) Bit 2 13 PCI2 1 (Active/Inactive) Bit 1 12 PCI1 1 (Active/Inactive) Bit 0 11 PCI0 1 (Active/Inactive) Byte 3: Control Register 3 Bit Pin# Name Default Description Bit 7 9 3V66_2 1 (Active/Inactive) Bit 6 8 3V66_1 1 (Active/Inactive) Bit 5 7 3V66_0 1 (Active/Inactive) Bit 4 55 APIC 1 (Active/Inactive) Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 51 CPU1 1 (Active/Inactive) Bit 0 52 CPU0 1 (Active/Inactive) Byte 4: Control Register 4 Bit Pin# Name Default Description Bit 7 38 SDRAM7 1 (Active/Inactive) Bit 6 41 SDRAM6 1 (Active/Inactive) Bit 5 42 SDRAM5 1 (Active/Inactive) Bit 4 43 SDRAM4 1 (Active/Inactive) Bit 3 44 SDRAM3 1 (Active/Inactive) Bit 2 47 SDRAM2 1 (Active/Inactive) Bit 1 48 SDRAM1 1 (Active/Inactive) Bit 0 49 SDRAM0 1 (Active/Inactive) Byte 5: Control Register 5 Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 31 SDRAM12 1 (Active/Inactive) Bit 3 32 SDRAM11 1 (Active/Inactive) Bit 2 35 SDRAM10 1 (Active/Inactive) Bit 1 36 SDRAM9 1 (Active/Inactive) Bit 0 37 SDRAM8 1 (Active/Inactive) ........................ Document #: 38-07262 Rev. *B Page 8 of 20 W305B Byte 6: Vendor ID & Revision ID Register (Read Only) Bit Name Default Pin Description Bit 7 Revision_ID3 0 Revision ID bit[3] Bit 6 Revision_ID2 0 Revision ID bit[2] Bit 5 Revision_ID1 0 Revision ID bit[1] Bit 4 Revision_ID0 0 Revision ID bit[0] Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Byte 7: Control Register 7 Bit Pin# Name Default Pin Description Bit 7 - Reserved 0 Reserved Bit 6 24 24_48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 5 23 48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 4 22 48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 3 24 24_48MHz 1 (Active/Inactive) Bit 2 23 48 MHz 1 (Active/Inactive) Bit 1 22 48 MHz 1 (Active/Inactive) Bit 0 -- Reserved 0 Reserved Byte 8: Watchdog Timer Register Bit Name Default Bit 7 PCI_Skew1 0 Bit 6 PCI_Skew0 0 Bit 5 WD_TIMER4 1 Bit 4 WD_TIMER3 1 Bit 3 WD_TIMER2 1 Bit 2 WD_TIMER1 1 Bit 1 WD_TIMER0 1 Bit 0 WD_PRE_SCALER 0 Pin Description PCI skew control 00 = Normal 01 = –500ps 10 = Reserved 11 = +500ps These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec. to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. 0 = 150 ms 1 = 2.5 sec Byte 9: System RESET and Watchdog Timer Register Bit Name Default Pin Description Bit 7 SDRAM_DRV 0 SDRAM clock output drive strength 0 = Normal 1 = High Drive Bit 6 PCI_DRV 0 PCI clock output drive strength 0 = Normal 1 = High Drive Bit 5 FS_Override 0 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings ........................ Document #: 38-07262 Rev. *B Page 9 of 20 W305B Byte 9: System RESET and Watchdog Timer Register (continued) Bit Name Default Pin Description Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Bit 2 WD_TO_STATUS 0 Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) Bit 1 WD_EN 0 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. Bit 0 Reserved 0 Reserved Byte 10: Skew Control Register Bit Name Default Bit 7 CPU_Skew2 0 Bit 6 CPU_Skew1 0 Bit 5 CPU_Skew0 0 Bit 4 SDRAM_Skew2 0 Bit 3 SDRAM_Skew1 0 Bit 2 SDRAM_Skew0 0 Bit 1 AGP_Skew1 0 Bit 0 AGP_Skew0 0 Description CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps SDRAM skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps AGP skew control 00 = Normal 01 = –150ps 10 = +150ps 11 = +300ps ......................Document #: 38-07262 Rev. *B Page 10 of 20 W305B Byte 11: Recovery Frequency N-Value Register Bit Name Default Pin Description If ROCV_FREQ_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305Bwill change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 7 ROCV_FREQ_N7 0 Bit 6 ROCV_FREQ_N6 0 Bit 5 ROCV_FREQ_N5 0 Bit 4 ROCV_FREQ_N4 0 Bit 3 ROCV_FREQ_N3 0 Bit 2 ROCV_FREQ_N2 0 Bit 1 ROCV_FREQ_N1 0 Bit 0 ROCV_FREQ_N0 0 Byte 12: Recovery Frequency M-Value Register Bit Name Default Pin Description ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Bit 6 ROCV_FREQ_M6 0 Bit 5 ROCV_FREQ_M5 0 Bit 4 ROCV_FREQ_M4 0 Bit 3 ROCV_FREQ_M3 0 Bit 2 ROCV_FREQ_M2 0 Bit 1 ROCV_FREQ_M1 0 Bit 0 ROCV_FREQ_M0 0 If ROCV_FREQ_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305B will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 7 Byte 13: Programmable Frequency Select N-Value Register Default Pin Description Bit 7 Bit CPU_FSEL_N7 Name 0 Bit 6 CPU_FSEL_N6 0 Bit 5 CPU_FSEL_N5 0 Bit 4 CPU_FSEL_N4 0 Bit 3 CPU_FSEL_N3 0 Bit 2 CPU_FSEL_N2 0 Bit 1 CPU_FSEL_N1 0 If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 0 CPU_FSEL_N0 0 ...................... Document #: 38-07262 Rev. *B Page 11 of 20 W305B Byte 14: Programmable Frequency Select M-Value Register Bit Name Default Description Bit 7 Pro_Freq_EN 0 Programmable output frequencies enabled 0 = disabled 1 = enabled Bit 6 CPU_FSEL_M6 0 Bit 5 CPU_FSEL_M5 0 Bit 4 CPU_FSEL_M4 0 Bit 3 CPU_FSEL_M3 0 Bit 2 CPU_FSEL_M2 0 Bit 1 CPU_FSEL_M1 0 Bit 0 CPU_FSEL_M0 0 If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Byte 15: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 1 Reserved. Write with ‘1’ Bit 0 - Reserved 1 Reserved. Write with ‘1’ Byte 16: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 0 Reserved Byte 17: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 0 Reserved ......................Document #: 38-07262 Rev. *B Page 12 of 20 W305B Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 SEL3 SEL2 SEL1 SEL0 CPU SDRAM 3V66 PCI APIC PLL Gear Constants (G) 0 0 0 0 0 66.6 100.0 66.6 33.3 16.6 32.00494 0 0 0 0 1 120.0 120.0 80.0 40.0 20.0 48.00741 0 0 0 1 0 66.8 100.2 66.8 33.4 16.7 32.00494 0 0 0 1 1 68.3 102.5 68.3 34.2 17.1 32.00494 0 0 1 0 0 70.0 105.0 70.0 35.0 17.5 32.00494 0 0 1 0 1 75.0 112.5 75.0 37.5 18.8 32.00494 0 0 1 1 0 80.0 120.0 80.0 40.0 20.0 32.00494 0 0 1 1 1 83.0 124.5 83.0 41.5 20.8 32.00494 0 1 0 0 0 100.0 100.0 66.6 33.3 16.6 48.00741 0 1 0 0 1 124.0 124.0 82.6 41.3 20.6 48.00741 0 1 0 1 0 100.2 100.2 66.8 33.4 16.7 48.00741 0 1 0 1 1 103.0 103.0 68.9 34.3 17.2 48.00741 0 1 1 0 0 105.0 105.0 70.0 35.0 17.5 48.00741 0 1 1 0 1 110.0 110.0 73.3 36.7 18.3 48.00741 0 1 1 1 0 115.0 115.0 76.6 38.3 19.1 48.00741 0 1 1 1 1 200.0 200.0 66.6 33.3 16.6 96.01482 1 0 0 0 0 133.3 133.3 66.6 33.3 16.6 64.00988 1 0 0 0 1 166.6 166.6 83.3 41.6 20.8 64.00988 1 0 0 1 0 133.6 133.6 66.8 33.4 16.7 64.00988 1 0 0 1 1 137.0 137.0 68.5 34.3 17.1 64.00988 1 0 1 0 0 140.0 140.0 70.0 35.0 17.5 64.00988 1 0 1 0 1 145.0 145.0 72.5 36.2 18.1 64.00988 1 0 1 1 0 150.0 150.0 75.0 37.5 18.7 64.00988 1 0 1 1 1 160.0 160.0 80.0 40.0 20.0 64.00988 1 1 0 0 0 133.3 100.0 66.6 33.3 16.6 64.00988 1 1 0 0 1 166.6 125.0 83.3 41.7 20.8 64.00988 1 1 0 1 0 133.6 100.2 66.8 33.4 16.7 64.00988 1 1 0 1 1 137.0 102.8 68.5 34.3 17.1 64.00988 1 1 1 0 0 66.6 100.0 66.6 33.3 16.6 32.00494 1 1 1 0 1 100.0 100.0 66.6 33.3 16.6 48.00741 1 1 1 1 0 133.3 133.3 66.6 33.3 16.6 64.00988 1 1 1 1 1 133.3 100.0 66.6 33.3 16.6 64.00988 ......................Document #: 38-07262 Rev. *B Page 13 of 20 W305B Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Table 6. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = disabled (default) 1 = enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. ......................Document #: 38-07262 Rev. *B Page 14 of 20 W305B Table 6. Register Summary (continued) Name Description WD_EN 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note. W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec. when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec RST_EN_WD This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 5. The following table lists the recommended frequency output ranges for each PLL Gear Constant and its associated Bus Frequency Ratio so that the maximum AGP and PCI output frequencies are less than or equal to 83.1 MHz and 41.5 MHz, respectively. Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio Recommended Output Frequency Range (CPU/SDRAM/AGP/PCI) Gear Constants Bus Frequency Ratio (CPU/SDRAM/AGP/PCI) Lower Limits (N=77, M=48) Upper Limits (N=106, M=39) G1 (32.00494) 66 / 100 / 66 / 33 50.2 / 75.8 / 50.2 / 25.1 83.1 / 124.7 / 83.1 / 41.5 G2 (48.00741) 100 / 100 / 66 / 33 75.3 / 75.3 / 50.2 / 25.1 124.6 / 124.6 / 83.1 / 41.5 G3 (64.00988) 133 / 133 / 66 / 33 or 133 / 100 / 66 / 33 100.4 / 100.4 / 50.2 / 25.1 or 100.4 / 75.3 / 50.2 / 25.1 166.1 / 166.1 / 83.1 / 41.5 or 166.1 / 124.5 / 83.1 / 41.5 G4 (96.01482) 200 / 200 / 66 / 33 150.6 / 150.6 / 50.2 / 25.1 249.2 / 249.2 / 83.1 / 41.5 ......................Document #: 38-07262 Rev. *B Page 15 of 20 W305B Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDDQ3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V TS Storage Temperature –65 150 °C Absolute Maximum DC I/O Parameter Vi/o3 Description 3.3V Core Supply Voltage Min. Max. Unit –0.5 4.6 V 3.6 Vi/o3 2.5V I/O Supply Voltage –0.5 ESD prot. Input ESD Protection 2000 V V DC Electrical Characteristics [2] DC parameters must be sustainable under steady state (DC) conditions. DC Operating Requirements Parameter Description Condition Min. Max. Unit VDD3 3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V VDD3 VDD3 = 3.3V±5% Vih3 3.3V Input High Voltage Vil3 3.3V Input Low Voltage Iil Input Leakage Current[3] Voh2 Vol2 2.0 VDD + 0.3 V VSS – 0.3 0.8 V 0