SI1026-A-GM

Si102x/3x Ultra Low Power 128K, LCD MCU Family Ultra Low Power at 3.6V - - 110 µA/MHz IBAT; DC-DC enabled 110 nA sleep current with data retention; POR monitor enabled 400 nA sleep current with smaRTClock (internal LFO) 700 nA sleep current with smaRTClock (external XTAL) 2 µs wake-up from any sleep mode Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode External pin or internal VREF (no external capacitor required) On-chip PGA allows measuring voltages up to twice the reference voltage Autonomous burst mode with 16-bit automatic averaging accumulator Integrated temperature sensor Programmable hysteresis and response time Configurable as interrupt or reset source Up to ±500 µA; source and sink capability Enhanced resolution via PWM interpolation Supports up to 128 segments (32x4) Integrated charge pump for contrast control DC-DC buck converter allows dynamic voltage scaling for  maximum efficiency (250 mW output) Sleep-mode pulse accumulator with programmable switch  de-bounce and pull-up control interfaces directly to metering sensor Dedicated Packet Processing Engine (DPPE) includes hardware AES, DMA, CRC, and encoding blocks for acceleration of wireless protocols Manchester and 3 out of 6 encoder hardware for power efficient implementation of the wireless M-bus specification ® Frequency range = 240–960 MHz Sensitivity = –121 dBm FSK, GFSK, and OOK modulation Max output power = +20 dBm or +13 dBm 12-Bit; 16 Ch. Analog-to-Digital Converter RF power consumption 18.5 mA receive 18 mA @ +1 dBm transmit 30 mA @ +13 dBm transmit 85 mA @ +20 dBm transmit Data rate = 0.123 to 256 kbps Auto-frequency calibration (AFC) Antenna diversity and transmit/receive switch control Programmable packet handler TX and RX 64-byte FIFOs Frequency hopping capability On-chip crystal tuning Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 128 kB Flash; In-system programmable; Full read/write/erase functionality over the entire supply range Up to 8 kB internal data RAM 53 port I/O; All 5 V tolerant with high sink  current and programmable drive strength Hardware SMBus™ (I2C™ compatible), 2 x SPI™, and UART serial ports available concurrently Four general-purpose 16-bit counter/timers Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer Precision internal oscillators: 24.5 MHz with ±2% accuracy supports UART operation; spread-spectrum mode for reduced EMI Low power internal oscillator: 20 MHz External oscillator: Crystal, RC, C, CMOS clock smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal LFO with three independent alarms On-chip debug circuitry facilitates full-speed, non-intrusive, in-system debug (no emulator required) Provides 4 breakpoints, single stepping –85 pin LGA (6 x 8 mm) High-Speed 8051 µC Core - Memory Two Low Current Comparators Internal 6-Bit Current Reference Integrated LCD Controller (Si102x Only) Metering-Specific Peripherals Digital Peripherals Clock Sources On-Chip Debug EZRadioPRO Transceiver Packages Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 128/64/32/16 kByte ISP Flash Program Memory 256 Byte SRAM 8192/4096 Byte XRAM DMA Analog Power Port I/O Configuration Digital Peripherals UART Timers 0/1/2/3 PCA/ WDT SMBus SPI 0 Crossbar Control LCD (4x32) Port 0-1 Drivers Port 2 Drivers 16 P0.0...P1.7 4 P2.4...P2.7 32 C2CK/RST Debug / Programming Hardware C2D Priority Crossbar Decoder Port 3-6 Drivers Port 7 Driver P3.0...P6.7 P7.0/C2D VBAT VDC VBAT VDD CRC Engine AES Engine Encoder RF XCVR (240-960 MHz, +20/+13 dBm) VCO VREG Digital Power PA TX AGC VBATDC IND GNDDC DC/DC Buck Converter Precision 24.5 MHz Oscillator LCD Charge Pump XTAL1 XTAL2 Low Power 20 MHz Oscillator External Oscillator Circuit Enhanced smaRTClock Oscillator SYSCLK SFR Bus EMIF Pulse Counter EZRadioPro SPI 1 LNA Mixer PGA RXp RXn CAP Analog Peripherals Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - ADC Digital Modem Delta Sigma Modulator Digital Logic GND XTAL3 XTAL4 12-bit 75ksps ADC 3 SDN nIRQ GPIOx XOUT XIN System Clock Configuration 30 MHz + - Comparators Rev. 0.3 11/11 Copyright © 2011 by Silicon Laboratories Si102x/3x This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si102x/3x 2 Rev. 0.3 Si102x/3x Table of Contents 1. System Overview ..................................................................................................... 26 1.1. Typical Connection Diagram ............................................................................. 29 1.2. CIP-51™ Microcontroller Core .......................................................................... 30 1.2.1. Fully 8051 Compatible .............................................................................. 30 1.2.2. Improved Throughput................................................................................ 30 1.2.3. Additional Features ................................................................................... 30 1.3. Port Input/Output ............................................................................................... 31 1.4. Serial Ports ........................................................................................................ 32 1.5. Programmable Counter Array............................................................................ 32 1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode................................................................ 33 1.7. Programmable Current Reference (IREF0)....................................................... 34 1.8. Comparators...................................................................................................... 34 2. Ordering Information ............................................................................................... 36 3. Pinout and Package Definitions ............................................................................. 37 3.1. LGA-85 Package Specifications ........................................................................ 46 3.1.1. Package Drawing ...................................................................................... 46 3.1.2. Land Pattern.............................................................................................. 48 3.1.3. Soldering Guidelines ................................................................................. 49 4. Electrical Characteristics ........................................................................................ 50 4.1. Absolute Maximum Specifications..................................................................... 50 4.2. MCU Electrical Characteristics .......................................................................... 51 4.3. EZRadioPRO® Peripheral Electrical Characteristics......................................... 70 4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 77 5. SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode ................................................................... 78 5.1. Output Code Formatting .................................................................................... 78 5.2. Modes of Operation ........................................................................................... 80 5.2.1. Starting a Conversion................................................................................ 80 5.2.2. Tracking Modes......................................................................................... 80 5.2.3. Burst Mode................................................................................................ 82 5.2.4. Settling Time Requirements...................................................................... 83 5.2.5. Gain Setting .............................................................................................. 83 5.3. 8-Bit Mode ......................................................................................................... 84 5.4. 12-Bit Mode ....................................................................................................... 84 5.5. Low Power Mode............................................................................................... 85 5.6. Programmable Window Detector....................................................................... 91 5.6.1. Window Detector In Single-Ended Mode .................................................. 93 5.6.2. ADC0 Specifications ................................................................................. 94 5.7. ADC0 Analog Multiplexer .................................................................................. 95 5.8. Temperature Sensor.......................................................................................... 97 5.8.1. Calibration ................................................................................................. 97 5.9. Voltage and Ground Reference Options ......................................................... 100 Rev. 0.3 3 Si102x/3x 5.10. External Voltage Reference........................................................................... 101 5.11. Internal Voltage Reference............................................................................ 101 5.12. Analog Ground Reference............................................................................. 101 5.13. Temperature Sensor Enable ......................................................................... 101 5.14. Voltage Reference Electrical Specifications .................................................. 102 6. Comparators........................................................................................................... 103 6.1. Comparator Inputs........................................................................................... 103 6.2. Comparator Outputs ........................................................................................ 104 6.3. Comparator Response Time ........................................................................... 105 6.4. Comparator Hysterisis ..................................................................................... 105 6.5. Comparator Register Descriptions .................................................................. 106 7. Programmable Current Reference (IREF0).......................................................... 110 7.1. PWM Enhanced Mode..................................................................................... 110 7.2. IREF0 Specifications ....................................................................................... 111 7.3. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112 8. CIP-51 Microcontroller........................................................................................... 115 8.1. Instruction Set.................................................................................................. 116 8.1.1. Instruction and CPU Timing .................................................................... 116 8.2. CIP-51 Register Descriptions .......................................................................... 121 9. Memory Organization ............................................................................................ 124 9.1. Program Memory............................................................................................. 124 9.1.1. MOVX Instruction and Program Memory ................................................ 127 9.2. Data Memory ................................................................................................... 127 9.2.1. Internal RAM ........................................................................................... 128 9.2.2. External RAM .......................................................................................... 128 10. External Data Memory Interface and On-Chip XRAM ....................................... 130 10.1. Accessing XRAM........................................................................................... 130 10.1.1. 16-Bit MOVX Example .......................................................................... 130 10.1.2. 8-Bit MOVX Example ............................................................................ 130 10.2. Configuring the External Memory Interface ................................................... 131 10.3. Port Configuration.......................................................................................... 131 10.4. Multiplexed and Non-Multiplexed Selection................................................... 135 10.4.1. Multiplexed Configuration...................................................................... 135 10.4.2. Non-Multiplexed Configuration.............................................................. 135 10.5. Memory Mode Selection................................................................................ 136 10.5.1. Internal XRAM Only .............................................................................. 137 10.5.2. Split Mode without Bank Select............................................................. 137 10.5.3. Split Mode with Bank Select.................................................................. 137 10.5.4. External Only......................................................................................... 137 10.6. Timing .......................................................................................................... 138 10.6.1. Non-Multiplexed Mode .......................................................................... 140 10.6.2. Multiplexed Mode .................................................................................. 143 11. Direct Memory Access (DMA0)........................................................................... 147 11.1. DMA0 Architecture ........................................................................................ 148 11.2. DMA0 Arbitration ........................................................................................... 149 4 Rev. 0.3 Si102x/3x 11.2.1. DMA0 Memory Access Arbitration ........................................................ 149 11.2.2. DMA0 Channel Arbitration .................................................................... 149 11.3. DMA0 Operation in Low Power Modes ......................................................... 149 11.4. Transfer Configuration................................................................................... 150 12. Cyclic Redundancy Check Unit (CRC0)............................................................. 161 12.1. 16-bit CRC Algorithm..................................................................................... 161 12.3. Preparing for a CRC Calculation ................................................................... 164 12.4. Performing a CRC Calculation ...................................................................... 164 12.5. Accessing the CRC0 Result .......................................................................... 164 12.6. CRC0 Bit Reverse Feature............................................................................ 168 13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 169 13.1. Polynomial Specification................................................................................ 169 13.2. Endianness.................................................................................................... 170 13.3. CRC Seed Value ........................................................................................... 171 13.4. Inverting the Final Value................................................................................ 171 13.5. Flipping the Final Value ................................................................................. 171 13.6. Using CRC1 with SFR Access ...................................................................... 172 13.7. Using the CRC1 module with the DMA ......................................................... 172 14. Advanced Encryption Standard (AES) Peripheral ............................................ 176 14.1. Hardware Description .................................................................................... 177 14.1.1. AES Encryption/Decryption Core .......................................................... 178 14.1.2. Data SFRs............................................................................................. 178 14.1.3. Configuration sfrs .................................................................................. 179 14.1.4. Input Multiplexer.................................................................................... 179 14.1.5. Output Multiplexer ................................................................................. 179 14.1.6. Internal State Machine .......................................................................... 179 14.2. Key Inversion................................................................................................. 180 14.2.1. Key Inversion using DMA...................................................................... 181 14.2.2. Key Inversion using SFRs..................................................................... 182 14.2.3. Extended Key Output Byte Order.......................................................... 183 14.2.4. Using the DMA to unwrap the extended Key ........................................ 184 14.3. AES Block Cipher .......................................................................................... 185 14.4. AES Block Cipher Data Flow......................................................................... 186 14.4.1. AES Block Cipher Encryption using DMA ............................................. 187 14.4.2. AES Block Cipher Encryption using SFRs ............................................ 188 14.5. AES Block Cipher Decryption ........................................................................ 189 14.5.1. AES Block Cipher Decryption using DMA............................................. 189 14.5.2. AES Block Cipher Decryption using SFRs............................................ 190 14.6. Block Cipher Modes ...................................................................................... 191 14.6.1. Cipher Block Chaining Mode................................................................. 191 14.6.2. CBC Encryption Initialization Vector Location....................................... 193 14.6.3. CBC Encryption using DMA .................................................................. 193 14.6.4. CBC Decryption .................................................................................... 196 14.6.5. Counter Mode ....................................................................................... 199 14.6.6. CTR Encryption using DMA .................................................................. 201 Rev. 0.3 5 Si102x/3x 15. Encoder/Decoder ................................................................................................. 208 15.1. Manchester Encoding.................................................................................... 209 15.2. Manchester Decoding.................................................................................... 210 15.3. Three-out-of-Six Encoding............................................................................ 211 15.4. Three-out-of-Six Decoding ............................................................................ 212 15.5. Encoding/Decoding with SFR Access ........................................................... 213 15.6. Decoder Error Interrupt.................................................................................. 213 15.7. Using the ENC0 module with the DMA.......................................................... 214 16. Special Function Registers................................................................................. 217 16.1. SFR Paging ................................................................................................... 217 16.2. Interrupts and SFR Paging ............................................................................ 217 16.3. SFR Page Stack Example ............................................................................. 219 17. Interrupt Handler.................................................................................................. 238 17.1. Enabling Interrupt Sources ............................................................................ 238 17.2. MCU Interrupt Sources and Vectors.............................................................. 238 17.3. Interrupt Priorities .......................................................................................... 239 17.4. Interrupt Latency............................................................................................ 239 17.5. Interrupt Register Descriptions ...................................................................... 241 17.6. External Interrupts INT0 and INT1................................................................. 248 18. Flash Memory....................................................................................................... 250 18.1. Programming the Flash Memory ................................................................... 250 18.1.1. Flash Lock and Key Functions .............................................................. 250 18.1.2. Flash Erase Procedure ......................................................................... 250 18.1.3. Flash Write Procedure .......................................................................... 251 18.1.4. Flash Write Optimization ....................................................................... 252 18.2. Non-volatile Data Storage ............................................................................. 253 18.3. Security Options ............................................................................................ 253 18.4. Determining the Device Part Number at Run Time ....................................... 255 18.5. Flash Write and Erase Guidelines ................................................................. 256 18.5.1. VDD Maintenance and the VDD Monitor .............................................. 256 18.5.2. PSWE Maintenance .............................................................................. 258 18.5.3. System Clock ........................................................................................ 258 18.6. Minimizing Flash Read Current ..................................................................... 259 19. Power Management ............................................................................................. 264 19.1. Normal Mode ................................................................................................. 265 19.2. Idle Mode....................................................................................................... 265 19.3. Stop Mode ..................................................................................................... 266 19.4. Low Power Idle Mode .................................................................................... 266 19.5. Suspend Mode .............................................................................................. 270 19.6. Sleep Mode ................................................................................................... 270 19.7. Configuring Wakeup Sources........................................................................ 271 19.8. Determining the Event that Caused the Last Wakeup................................... 271 19.9. Power Management Specifications ............................................................... 275 20. On-Chip DC-DC Buck Converter (DC0).............................................................. 276 20.1. Startup Behavior............................................................................................ 277 6 Rev. 0.3 Si102x/3x 20.4. Optimizing Board Layout ............................................................................... 278 20.5. Selecting the Optimum Switch Size............................................................... 278 20.6. DC-DC Converter Clocking Options .......................................................... 278 20.7. Bypass Mode................................................................................................. 279 20.8. DC-DC Converter Register Descriptions ....................................................... 279 20.9. DC-DC Converter Specifications ................................................................... 283 21. Voltage Regulator (VREG0)................................................................................. 284 21.1. Voltage Regulator Electrical Specifications ................................................... 284 22. Reset Sources ...................................................................................................... 285 22.1. Power-On Reset ............................................................................................ 286 22.2. Power-Fail Reset ........................................................................................... 287 22.3. External Reset ............................................................................................... 290 22.4. Missing Clock Detector Reset ....................................................................... 290 22.5. Comparator0 Reset ....................................................................................... 290 22.6. PCA Watchdog Timer Reset ......................................................................... 290 22.7. Flash Error Reset .......................................................................................... 291 22.8. SmaRTClock (Real Time Clock) Reset ......................................................... 291 22.9. Software Reset .............................................................................................. 291 23. Clocking Sources................................................................................................. 293 23.1. Programmable Precision Internal Oscillator .................................................. 294 23.2. Low Power Internal Oscillator........................................................................ 294 23.3. External Oscillator Drive Circuit..................................................................... 294 23.3.1. External Crystal Mode........................................................................... 294 23.3.2. External RC Mode................................................................................. 296 23.3.3. External Capacitor Mode....................................................................... 297 23.3.4. External CMOS Clock Mode ................................................................. 297 23.4. Special Function Registers for Selecting and  Configuring the System Clock ....................................................................... 298 24. SmaRTClock (Real Time Clock).......................................................................... 302 24.1. SmaRTClock Interface .................................................................................. 303 24.1.1. SmaRTClock Lock and Key Functions.................................................. 304 24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock  Internal Registers ................................................................................. 304 24.1.3. SmaRTClock Interface Autoread Feature ............................................. 304 24.1.4. RTC0ADR Autoincrement Feature........................................................ 304 24.2. SmaRTClock Clocking Sources .................................................................... 307 24.2.1. Using the SmaRTClock Oscillator with a Crystal or  External CMOS Clock ........................................................................... 307 24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 308 24.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 308 24.2.4. Programmable Load Capacitance......................................................... 308 24.2.5. Automatic Gain Control (Crystal Mode Only) and  SmaRTClock Bias Doubling ................................................................. 309 24.2.6. Missing SmaRTClock Detector ............................................................. 311 24.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 311 Rev. 0.3 7 Si102x/3x 24.3. SmaRTClock Timer and Alarm Function ....................................................... 311 24.3.1. Setting and Reading the SmaRTClock Timer Value ............................. 311 24.3.2. Setting a SmaRTClock Alarm ............................................................... 312 24.3.3. Software Considerations for using the  SmaRTClock Timer and Alarm ............................................................. 312 25. Low-Power Pulse Counter .................................................................................. 319 25.1. Counting Modes ............................................................................................ 320 25.2. Reed Switch Types........................................................................................ 321 25.3. Programmable Pull-Up Resistors .................................................................. 322 25.4. Automatic Pull-Up Resistor Calibration ......................................................... 324 25.5. Sample Rate.................................................................................................. 324 25.6. Debounce ...................................................................................................... 324 25.7. Reset Behavior .............................................................................................. 325 25.8. Wake up and Interrupt Sources..................................................................... 325 25.9. Real-Time Register Access ........................................................................... 326 25.10. Advanced Features ..................................................................................... 326 25.10.1. Quadrature Error ................................................................................. 326 25.10.2. Flutter Detection.................................................................................. 327 26. LCD Segment Driver (Si102x Only) .................................................................... 341 26.1. Configuring the LCD Segment Driver ............................................................ 341 26.2. Mapping Data Registers to LCD Pins............................................................ 342 26.3. LCD Contrast Adjustment.............................................................................. 345 26.3.1. Contrast Control Mode 1 (Bypass Mode).............................................. 345 26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode) ............................ 346 26.3.3. Contrast Control Mode 3 (Constant Contrast Mode)............................. 346 26.3.4. Contrast Control Mode 4 (Auto-Bypass Mode) ..................................... 347 26.4. Adjusting the VBAT Monitor Threshold ......................................................... 351 26.5. Setting the LCD Refresh Rate ....................................................................... 352 26.6. Blinking LCD Segments................................................................................. 353 26.7. Advanced LCD Optimizations........................................................................ 355 27. Port Input/Output ................................................................................................. 358 27.1. Port I/O Modes of Operation.......................................................................... 359 27.1.1. Port Pins Configured for Analog I/O...................................................... 359 27.1.2. Port Pins Configured For Digital I/O...................................................... 359 27.1.3. Interfacing Port I/O to High Voltage Logic............................................. 360 27.1.4. Increasing Port I/O Drive Strength ........................................................ 360 27.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 360 27.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 360 27.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 361 27.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 361 27.3. Priority Crossbar Decoder ............................................................................. 362 27.4. Port Match ..................................................................................................... 368 27.5. Special Function Registers for Accessing and Configuring Port I/O ............. 370 28. SMBus................................................................................................................... 388 28.1. Supporting Documents .................................................................................. 389 8 Rev. 0.3 Si102x/3x 28.2. SMBus Configuration..................................................................................... 389 28.3. SMBus Operation .......................................................................................... 389 28.3.1. Transmitter Vs. Receiver....................................................................... 390 28.3.2. Arbitration.............................................................................................. 390 28.3.3. Clock Low Extension............................................................................. 390 28.3.4. SCL Low Timeout.................................................................................. 390 28.3.5. SCL High (SMBus Free) Timeout ......................................................... 391 28.4. Using the SMBus........................................................................................... 391 28.4.1. SMBus Configuration Register.............................................................. 391 28.4.2. SMB0CN Control Register .................................................................... 395 28.4.3. Hardware Slave Address Recognition .................................................. 397 28.4.4. Data Register ........................................................................................ 400 28.5. SMBus Transfer Modes................................................................................. 400 28.5.1. Write Sequence (Master) ...................................................................... 400 28.5.2. Read Sequence (Master) ...................................................................... 401 28.5.3. Write Sequence (Slave) ........................................................................ 402 28.5.4. Read Sequence (Slave) ........................................................................ 403 28.6. SMBus Status Decoding................................................................................ 404 29. UART0 ................................................................................................................... 409 29.1. Enhanced Baud Rate Generation.................................................................. 410 29.2. Operational Modes ........................................................................................ 411 29.2.1. 8-Bit UART ............................................................................................ 411 29.2.2. 9-Bit UART ............................................................................................ 411 29.3. Multiprocessor Communications ................................................................... 412 30. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 418 30.1. Signal Descriptions........................................................................................ 419 30.1.1. Master Out, Slave In (MOSI)................................................................. 419 30.1.2. Master In, Slave Out (MISO)................................................................. 419 30.1.3. Serial Clock (SCK) ................................................................................ 419 30.1.4. Slave Select (NSS) ............................................................................... 419 30.2. SPI0 Master Mode Operation ........................................................................ 419 30.3. SPI0 Slave Mode Operation .......................................................................... 421 30.4. SPI0 Interrupt Sources .................................................................................. 422 30.5. Serial Clock Phase and Polarity .................................................................... 422 30.6. SPI Special Function Registers ..................................................................... 424 31. EZRadioPRO® Serial Interface ........................................................................... 431 31.1. Signal Descriptions........................................................................................ 432 31.1.1. Master Out, Slave In (MOSI)................................................................. 432 31.1.2. Master In, Slave Out (MISO)................................................................. 432 31.1.3. Serial Clock (SCK) ................................................................................ 432 31.1.4. Slave Select (NSS) ............................................................................... 432 31.2. SPI1 Master Mode Operation ........................................................................ 433 31.3. SPI Slave Operation on the EZRadioPRO Peripheral Side........................... 433 31.4. SPI1 Interrupt Sources .................................................................................. 433 31.5. Serial Clock Phase and Polarity .................................................................... 434 Rev. 0.3 9 Si102x/3x 31.6. Using SPI1 with the DMA .............................................................................. 435 31.7. Master Mode SPI1 DMA Transfers................................................................ 435 31.8. Master Mode Bidirectional Data Transfer ...................................................... 435 31.9. Master Mode Unidirectional Data Transfer.................................................... 437 31.10. SPI Special Function Registers ................................................................... 437 32. EZRadioPRO® 240–960 MHz Transceiver.......................................................... 443 32.1. EZRadioPRO Operating Modes .................................................................... 444 32.1.1. Operating Mode Control ....................................................................... 445 32.2. Interrupts ...................................................................................................... 447 32.3. System Timing............................................................................................... 448 32.3.1. Frequency Control................................................................................. 449 32.3.2. Frequency Programming....................................................................... 449 32.3.3. Easy Frequency Programming for FHSS.............................................. 451 32.3.4. Automatic State Transition for Frequency Change ............................... 452 32.3.5. Frequency Deviation ............................................................................. 452 32.3.6. Frequency Offset Adjustment................................................................ 453 32.3.7. Automatic Frequency Control (AFC) ..................................................... 453 32.3.8. TX Data Rate Generator ....................................................................... 455 32.4. Modulation Options........................................................................................ 455 32.4.1. Modulation Type.................................................................................... 455 32.4.2. Modulation Data Source........................................................................ 456 32.4.3. PN9 Mode ............................................................................................. 460 32.5. Internal Functional Blocks ............................................................................. 460 32.5.1. RX LNA ................................................................................................. 460 32.5.2. RX I-Q Mixer ......................................................................................... 460 32.5.3. Programmable Gain Amplifier ............................................................... 460 32.5.4. ADC ..................................................................................................... 461 32.5.5. Digital Modem ....................................................................................... 461 32.5.6. Synthesizer ........................................................................................... 462 32.5.7. Power Amplifier ..................................................................................... 463 32.5.8. Crystal Oscillator ................................................................................... 464 32.5.9. Regulators............................................................................................. 464 32.6. Data Handling and Packet Handler ............................................................... 465 32.6.1. RX and TX FIFOs.................................................................................. 465 32.6.2. Packet Configuration............................................................................. 466 32.6.3. Packet Handler TX Mode ...................................................................... 467 32.6.4. Packet Handler RX Mode...................................................................... 467 32.6.5. Data Whitening, Manchester Encoding, and CRC ................................ 469 32.6.6. Preamble Detector ................................................................................ 470 32.6.7. Preamble Length ................................................................................... 470 32.6.8. Invalid Preamble Detector..................................................................... 471 32.6.9. Synchronization Word Configuration..................................................... 471 32.6.10. Receive Header Check ....................................................................... 472 32.6.11. TX Retransmission and Auto TX......................................................... 472 32.7. RX Modem Configuration .............................................................................. 473 10 Rev. 0.3 Si102x/3x 32.7.1. Modem Settings for FSK and GFSK ..................................................... 473 32.8. Auxiliary Functions ........................................................................................ 473 32.8.1. Smart Reset .......................................................................................... 473 32.8.2. Output Clock ......................................................................................... 474 32.8.3. General Purpose ADC .......................................................................... 475 32.8.4. Temperature Sensor ............................................................................. 476 32.8.5. Low Battery Detector............................................................................. 478 32.8.6. Wake-Up Timer and 32 kHz Clock Source ........................................... 479 32.8.7. Low Duty Cycle Mode ........................................................................... 481 32.8.8. GPIO Configuration............................................................................... 482 32.8.9. Antenna Diversity .................................................................................. 483 32.8.10. RSSI and Clear Channel Assessment ................................................ 483 32.9. Reference Design.......................................................................................... 484 32.10. Application Notes and Reference Designs .................................................. 487 32.11. Customer Support ....................................................................................... 487 32.12. Register Table and Descriptions ................................................................. 488 32.13. Required Changes to Default Register Values............................................ 490 33. Timers ................................................................................................................... 491 33.1. Timer 0 and Timer 1 ...................................................................................... 493 33.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 493 33.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 494 33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 494 33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 495 33.2. Timer 2 .......................................................................................................... 501 33.2.1. 16-bit Timer with Auto-Reload............................................................... 501 33.2.2. 8-bit Timers with Auto-Reload............................................................... 502 33.2.3. Comparator 0/SmaRTClock Capture Mode .......................................... 502 33.3. Timer 3 .......................................................................................................... 507 33.3.1. 16-bit Timer with Auto-Reload............................................................... 507 33.3.2. 8-Bit Timers with Auto-Reload .............................................................. 508 33.3.3. SmaRTClock/External Oscillator Capture Mode ................................... 508 34. Programmable Counter Array............................................................................. 513 34.1. PCA Counter/Timer ....................................................................................... 514 34.2. PCA0 Interrupt Sources................................................................................. 515 34.3. Capture/Compare Modules ........................................................................... 516 34.3.1. Edge-triggered Capture Mode............................................................... 517 34.3.2. Software Timer (Compare) Mode.......................................................... 518 34.3.3. High-Speed Output Mode ..................................................................... 519 34.3.4. Frequency Output Mode ....................................................................... 520 34.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes.............. 521 34.3.6. 16-Bit Pulse Width Modulator Mode..................................................... 523 34.4. Watchdog Timer Mode .................................................................................. 524 34.4.1. Watchdog Timer Operation ................................................................... 524 34.4.2. Watchdog Timer Usage ........................................................................ 525 34.5. Register Descriptions for PCA0..................................................................... 527 Rev. 0.3 11 Si102x/3x 35. C2 Interface .......................................................................................................... 533 35.1. C2 Interface Registers................................................................................... 533 35.2. C2 Pin Sharing .............................................................................................. 536 Contact Information .................................................................................................. 538 12 Rev. 0.3 Si102x/3x List of Figures Figure 1.1. Si102x Block Diagram ........................................................................... 28 Figure 1.2. Si103x Block Diagram ........................................................................... 28 Figure 1.3. Si102x/3x RX/TX Direct-tie Application Example .................................. 29 Figure 1.4. Si102x/3x Antenna Diversity Application Example ................................ 29 Figure 1.5. Port I/O Functional Block Diagram ........................................................ 31 Figure 1.6. PCA Block Diagram ............................................................................... 32 Figure 1.7. ADC0 Functional Block Diagram ........................................................... 33 Figure 1.8. ADC0 Multiplexer Block Diagram .......................................................... 34 Figure 1.9. Comparator 0 Functional Block Diagram .............................................. 35 Figure 1.10. Comparator 1 Functional Block Diagram ............................................ 35 Figure 3.1. LGA-85 Pinout Diagram (Top View) ...................................................... 45 Figure 3.2. LGA-85 Package Drawing ..................................................................... 46 Figure 3.3. LGA-85 Land Pattern ............................................................................ 48 Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) ............................ 56 Figure 4.2. Typical VOH Curves, 1.8–3.8 V ............................................................ 58 Figure 4.3. Typical VOL Curves, 1.8–3.8 V ............................................................. 59 Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing  (BURSTEN = 0) ..................................................................................... 81 Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 82 Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 83 Figure 5.5. ADC Window Compare Example: Right-Justified  Single-Ended Data ................................................................................ 94 Figure 5.6. ADC Window Compare Example: Left-Justified  Single-Ended Data ................................................................................ 94 Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95 Figure 5.8. Temperature Sensor Transfer Function ................................................ 97 Figure 5.9. Temperature Sensor Error with 1-Point Calibration  (VREF = 1.68 V) ..................................................................................... 98 Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100 Figure 6.1. Comparator 0 Functional Block Diagram ............................................ 103 Figure 6.2. Comparator 1 Functional Block Diagram ............................................ 104 Figure 6.3. Comparator Hysteresis Plot ................................................................ 105 Figure 7.1. CPn Multiplexer Block Diagram ........................................................... 112 Figure 8.1. CIP-51 Block Diagram ......................................................................... 115 Figure 9.1. Si102x/3x Memory Map ....................................................................... 124 Figure 9.2. Flash Program Memory Map ............................................................... 125 Figure 9.3. Address Memory Map for Instruction Fetches ..................................... 126 Figure 10.1. Multiplexed Configuration Example ................................................... 135 Figure 10.2. Non-Multiplexed Configuration Example ........................................... 136 Figure 10.3. EMIF Operating Modes ..................................................................... 136 Figure 10.4. Non-Multiplexed 16-bit MOVX Timing ............................................... 140 Figure 10.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing ................ 141 Rev. 0.3 13 Si102x/3x Figure 10.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing ..................... 142 Figure 10.7. Multiplexed 16-bit MOVX Timing ....................................................... 143 Figure 10.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 144 Figure 10.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 145 Figure 11.1. DMA0 Block Diagram ........................................................................ 148 Figure 12.1. CRC0 Block Diagram ........................................................................ 161 Figure 12.2. Bit Reverse Register ......................................................................... 168 Figure 13.1. Polynomial Representation ............................................................... 169 Figure 14.1. AES Peripheral Block Diagram ......................................................... 177 Figure 14.2. Key Inversion Data Flow ................................................................... 180 Figure 14.3. AES Block Cipher Data Flow ............................................................. 186 Figure 14.4. Cipher Block Chaining Mode ............................................................. 191 Figure 14.5. CBC Encryption Data Flow ................................................................ 192 Figure 14.6. CBC Decryption Data Flow ............................................................... 196 Figure 14.7. Counter Mode .................................................................................... 199 Figure 14.8. Counter Mode Data Flow .................................................................. 200 Figure 16.1. SFR Page Stack ................................................................................ 218 Figure 16.2. SFR Page Stack While Using SFR Page 0x0  To Access SMB0ADR ....................................................................... 219 Figure 16.3. SFR Page Stack After SPI0 Interrupt Occurs .................................... 220 Figure 16.4. SFR Page Stack Upon PCA Interrupt Occurring  During a SPI0 ISR ............................................................................. 221 Figure 16.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 222 Figure 16.6. SFR Page Stack Upon Return From SPI0 Interrupt .......................... 223 Figure 18.1. Flash Security Example ..................................................................... 253 Figure 19.1. Si102x/3x Power Distribution ............................................................ 265 Figure 19.2. Clock Tree Distribution ...................................................................... 266 Figure 20.1. Step Down DC-DC Buck Converter Block Diagram .......................... 276 Figure 22.1. Reset Sources ................................................................................... 285 Figure 22.2. Power-On Reset Timing Diagram ..................................................... 286 Figure 23.1. Clocking Sources Block Diagram ...................................................... 293 Figure 23.2. 25 MHz External Crystal Example ..................................................... 295 Figure 24.1. SmaRTClock Block Diagram ............................................................. 302 Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 310 Figure 25.1. Pulse Counter Block Diagram ........................................................... 319 Figure 25.2. Mode Examples ................................................................................. 320 Figure 25.3. Reed Switch Configurations .............................................................. 321 Figure 25.4. Debounce Timing .............................................................................. 325 Figure 25.5. Flutter Example ................................................................................. 327 Figure 26.1. LCD Segment Driver Block Diagram ................................................. 341 Figure 26.2. LCD Data Register to LCD Pin Mapping ........................................... 343 Figure 26.3. Contrast Control Mode 1 ................................................................... 345 Figure 26.4. Contrast Control Mode 2 ................................................................... 346 Figure 26.5. Contrast Control Mode 3 ................................................................... 346 Figure 26.6. Contrast Control Mode 4 ................................................................... 347 14 Rev. 0.3 Si102x/3x Figure 27.1. Port I/O Functional Block Diagram .................................................... 358 Figure 27.2. Port I/O Cell Block Diagram .............................................................. 359 Figure 27.3. Crossbar Priority Decoder with No Pins Skipped .............................. 363 Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 364 Figure 28.1. SMBus Block Diagram ...................................................................... 388 Figure 28.2. Typical SMBus Configuration ............................................................ 389 Figure 28.3. SMBus Transaction ........................................................................... 390 Figure 28.4. Typical SMBus SCL Generation ........................................................ 392 Figure 28.5. Typical Master Write Sequence ........................................................ 401 Figure 28.6. Typical Master Read Sequence ........................................................ 402 Figure 28.7. Typical Slave Write Sequence .......................................................... 403 Figure 28.8. Typical Slave Read Sequence .......................................................... 404 Figure 29.1. UART0 Block Diagram ...................................................................... 409 Figure 29.2. UART0 Baud Rate Logic ................................................................... 410 Figure 29.3. UART Interconnect Diagram ............................................................. 411 Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 411 Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 412 Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 413 Figure 30.1. SPI Block Diagram ............................................................................ 418 Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 421 Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode  Connection Diagram .......................................................................... 421 Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode  Connection Diagram .......................................................................... 421 Figure 30.5. Master Mode Data/Clock Timing ....................................................... 423 Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 423 Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 424 Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 428 Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 428 Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 429 Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 429 Figure 31.1. SPI Block Diagram ............................................................................ 431 Figure 31.2. Master Mode Data/Clock Timing ....................................................... 434 Figure 31.3. SPI Master Timing (CKPHA = 0) ....................................................... 441 Figure 32.1. State Machine Diagram ..................................................................... 445 Figure 32.2. TX Timing .......................................................................................... 448 Figure 32.3. RX Timing .......................................................................................... 449 Figure 32.4. Frequency Deviation ......................................................................... 452 Figure 32.5. Sensitivity at 1% PER vs. Carrier Frequency Offset ......................... 454 Figure 32.6. FSK vs. GFSK Spectrums ................................................................. 456 Figure 32.7. Direct Synchronous Mode Example .................................................. 459 Figure 32.8. Direct Asynchronous Mode Example ................................................ 459 Figure 32.9. Microcontroller Connections .............................................................. 460 Figure 32.10. PLL Synthesizer Block Diagram ...................................................... 462 Figure 32.11. FIFO Thresholds ............................................................................. 465 Rev. 0.3 15 Si102x/3x Figure 32.12. Packet Structure .............................................................................. 466 Figure 32.13. Multiple Packets in TX Packet Handler ........................................... 467 Figure 32.14. Required RX Packet Structure with Packet Handler Disabled ........ 467 Figure 32.15. Multiple Packets in RX Packet Handler ........................................... 468 Figure 32.16. Multiple Packets in RX with CRC or Header Error .......................... 468 Figure 32.17. Operation of Data Whitening, Manchester Encoding,  and CRC ......................................................................................... 470 Figure 32.18. Manchester Coding Example .......................................................... 470 Figure 32.19. Header ............................................................................................. 472 Figure 32.20. POR Glitch Parameters ................................................................... 473 Figure 32.21. General Purpose ADC Architecture ................................................ 476 Figure 32.22. Temperature Ranges using ADC8 .................................................. 478 Figure 32.23. WUT Interrupt and WUT Operation ................................................. 481 Figure 32.24. Low Duty Cycle Mode ..................................................................... 482 Figure 32.25. RSSI Value vs. Input Power ............................................................ 484 Figure 32.26. Si1024 Split RF TX/RX Direct-Tie  Reference Design—Schematic ....................................................... 485 Figure 32.27. Si1020 Switch Matching Reference Design—Schematic ................ 486 Figure 33.1. T0 Mode 0 Block Diagram ................................................................. 494 Figure 33.2. T0 Mode 2 Block Diagram ................................................................. 495 Figure 33.3. T0 Mode 3 Block Diagram ................................................................. 496 Figure 33.4. Timer 2 16-Bit Mode Block Diagram ................................................. 501 Figure 33.5. Timer 2 8-Bit Mode Block Diagram ................................................... 502 Figure 33.6. Timer 2 Capture Mode Block Diagram .............................................. 503 Figure 33.7. Timer 3 16-Bit Mode Block Diagram ................................................. 507 Figure 33.8. Timer 3 8-Bit Mode Block Diagram ................................................... 508 Figure 33.9. Timer 3 Capture Mode Block Diagram .............................................. 509 Figure 34.1. PCA Block Diagram ........................................................................... 513 Figure 34.2. PCA Counter/Timer Block Diagram ................................................... 515 Figure 34.3. PCA Interrupt Block Diagram ............................................................ 516 Figure 34.4. PCA Capture Mode Diagram ............................................................. 518 Figure 34.5. PCA Software Timer Mode Diagram ................................................. 519 Figure 34.6. PCA High-Speed Output Mode Diagram ........................................... 520 Figure 34.7. PCA Frequency Output Mode ........................................................... 521 Figure 34.8. PCA 8-Bit PWM Mode Diagram ........................................................ 522 Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 523 Figure 34.10. PCA 16-Bit PWM Mode ................................................................... 524 Figure 34.11. PCA Module 5 with Watchdog Timer Enabled ................................ 525 Figure 35.1. Typical C2 Pin Sharing ...................................................................... 536 16 Rev. 0.3 Si102x/3x List of Tables Table 2.1. Product Selection Guide ......................................................................... 36 Table 3.1. Pin Definitions for the Si102x/3x ............................................................. 37 Table 3.2. LGA-85 Package Dimensions ................................................................ 46 Table 3.3. LGA-85 Land Pattern Dimensions .......................................................... 48 Table 4.1. Absolute Maximum Ratings .................................................................... 50 Table 4.2. Global Electrical Characteristics ............................................................. 51 Table 4.3. Digital Supply Current at VBAT pin with DC-DC  Converter Enabled .................................................................................. 51 Table 4.4. Digital Supply Current with DC-DC Converter Disabled ......................... 52 Table 4.5. Port I/O DC Electrical Characteristics ..................................................... 57 Table 4.6. Reset Electrical Characteristics .............................................................. 60 Table 4.7. Power Management Electrical Specifications ......................................... 61 Table 4.8. Flash Electrical Characteristics .............................................................. 61 Table 4.9. Internal Precision Oscillator Electrical Characteristics ........................... 61 Table 4.10. Internal Low-Power Oscillator Electrical Characteristics ...................... 61 Table 4.11. SmaRTClock Characteristics ................................................................ 62 Table 4.12. ADC0 Electrical Characteristics ............................................................ 62 Table 4.13. Temperature Sensor Electrical Characteristics .................................... 63 Table 4.14. Voltage Reference Electrical Characteristics ....................................... 64 Table 4.15. IREF0 Electrical Characteristics ........................................................... 65 Table 4.16. Comparator Electrical Characteristics .................................................. 66 Table 4.17. VREG0 Electrical Characteristics ......................................................... 67 Table 4.18. LCD0 Electrical Characteristics ............................................................ 68 Table 4.19. PC0 Electrical Characteristics .............................................................. 68 Table 4.20. DC0 (Buck Converter) Electrical Characteristics .................................. 69 Table 4.21. DC Characteristics ................................................................................ 70 Table 4.22. Synthesizer AC Electrical Characteristics ............................................ 71 Table 4.23. Receiver AC Electrical Characteristics ................................................. 72 Table 4.24. Transmitter AC Electrical Characteristics ............................................. 73 Table 4.25. Auxiliary Block Specifications ............................................................... 74 Table 4.26. Digital IO Specifications (nIRQ) ............................................................ 75 Table 4.27. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ........................ 75 Table 4.28. Absolute Maximum Ratings .................................................................. 76 Table 5.1. Representative Conversion Times and Energy Consumption  for the SAR ADC with 1.65 V High-Speed VREF ................................... 85 Table 8.1. CIP-51 Instruction Set Summary .......................................................... 117 Table 10.1. EMIF Pinout ........................................................................................ 132 Table 10.2. AC Parameters for External Memory Interface ................................... 146 Table 12.1. Example 16-bit CRC Outputs ............................................................. 162 Table 12.2. Example 32-bit CRC Outputs ............................................................. 164 Table 14.1. Extended Key Output Byte Order ....................................................... 183 Table 14.2. 192-Bit Key DMA Usage ..................................................................... 184 Table 14.3. 256-bit Key DMA Usage ..................................................................... 184 Rev. 0.3 17 Si102x/3x Table 15.1. Encoder Input and Output Data Sizes ................................................ 208 Table 15.2. Manchester Encoding ......................................................................... 209 Table 15.3. Manchester Decoding ......................................................................... 210 Table 15.4. Three-out-of-Six Encoding Nibble ...................................................... 211 Table 15.5. Three-out-of-Six Decoding ................................................................. 212 Table 16.1. SFR Map (0xC0–0xFF) ...................................................................... 228 Table 16.2. SFR Map (0x80–0xBF) ....................................................................... 229 Table 16.3. Special Function Registers ................................................................. 230 Table 17.1. Interrupt Summary .............................................................................. 240 Table 18.1. Flash Security Summary .................................................................... 254 Table 19.1. Power Modes ...................................................................................... 264 Table 20.1. IPeak Inductor Current Limit Settings ................................................. 277 Table 23.1. Recommended XFCN Settings for Crystal Mode ............................... 295 Table 23.2. Recommended XFCN Settings for RC and C modes ......................... 296 Table 24.1. SmaRTClock Internal Registers ......................................................... 303 Table 24.2. SmaRTClock Load Capacitance Settings .......................................... 309 Table 24.3. SmaRTClock Bias Settings ................................................................ 310 Table 25.1. Pull-Up Resistor Current ..................................................................... 322 Table 25.2. Sample Rate Duty-Cycle Multiplier ..................................................... 322 Table 25.3. Pull-Up Duty-Cycle Multiplier .............................................................. 322 Table 25.4. Average Pull-Up Current (Sample Rate = 250 µs) ............................. 323 Table 25.5. Average Pull-Up Current (Sample Rate = 500 µs) ............................. 323 Table 25.6. Average Pull-Up Current (Sample Rate = 1 ms) ............................... 323 Table 25.7. Average Pull-Up Current (Sample Rate = 2 ms) ................................ 323 Table 26.1. Bit Configurations to select Contrast Control Modes .......................... 345 Table 27.1. Port I/O Assignment for Analog Functions ......................................... 360 Table 27.2. Port I/O Assignment for Digital Functions ........................................... 361 Table 27.3. Port I/O Assignment for External Digital Event  Capture Functions .............................................................................. 361 Table 28.1. SMBus Clock Source Selection .......................................................... 392 Table 28.2. Minimum SDA Setup and Hold Times ................................................ 393 Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 397 Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 398 Table 28.5. SMBus Status Decoding With Hardware ACK Generation  Disabled (EHACK = 0) ........................................................................ 405 Table 28.6. SMBus Status Decoding With Hardware ACK Generation  Enabled (EHACK = 1) ......................................................................... 407 Table 29.1. Timer Settings for Standard Baud Rates  Using The Internal 24.5 MHz Oscillator .............................................. 416 Table 29.2. Timer Settings for Standard Baud Rates  Using an External 22.1184 MHz Oscillator ......................................... 416 Table 30.1. SPI Slave Timing Parameters ............................................................ 430 Table 31.1. SPI Timing Parameters ...................................................................... 441 Table 32.1. EZRadioPRO Operating Modes ......................................................... 444 Table 32.2. EZRadioPRO Operating Modes Response Time ............................... 445 18 Rev. 0.3 Si102x/3x Table 32.3. Frequency Band Selection ................................................................. 450 Table 32.4. Packet Handler Registers ................................................................... 469 Table 32.5. Minimum Receiver Settling Time ........................................................ 471 Table 32.6. POR Parameters ................................................................................ 474 Table 32.7. Temperature Sensor Range ............................................................... 477 Table 32.8. Antenna Diversity Control ................................................................... 483 Table 32.9. EZRadioPRO Internal Register Descriptions ...................................... 488 Table 33.1. Timer 0 Running Modes ..................................................................... 493 Table 34.1. PCA Timebase Input Options ............................................................. 514 Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA  Capture/Compare Modules ................................................................ 516 Table 34.3. Watchdog Timer Timeout Intervals1 ................................................... 526 Rev. 0.3 19 Si102x/3x List of Registers SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 86 SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 87 SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 88 SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 89 SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 90 SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 91 SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 91 SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 92 SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 92 SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 93 SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 93 SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 96 SFR Definition 5.13. TOFFH: Temperature Sensor Offset High Byte ........................... 99 SFR Definition 5.14. TOFFL: Temperature Sensor Offset Low Byte ............................ 99 SFR Definition 5.15. REF0CN: Voltage Reference Control ........................................ 102 SFR Definition 6.1. CPT0CN: Comparator 0 Control .................................................. 106 SFR Definition 6.2. CPT0MD: Comparator 0 Mode Selection .................................... 107 SFR Definition 6.3. CPT1CN: Comparator 1 Control .................................................. 108 SFR Definition 6.4. CPT1MD: Comparator 1 Mode Selection .................................... 109 SFR Definition 7.1. IREF0CN: Current Reference Control ......................................... 110 SFR Definition 7.2. IREF0CF: Current Reference Configuration ................................ 111 SFR Definition 7.3. CPT0MX: Comparator0 Input Channel Select ............................. 113 SFR Definition 7.4. CPT1MX: Comparator1 Input Channel Select ............................. 114 SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 121 SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 121 SFR Definition 8.3. SP: Stack Pointer ......................................................................... 122 SFR Definition 8.4. ACC: Accumulator ....................................................................... 122 SFR Definition 8.5. B: B Register ................................................................................ 122 SFR Definition 8.6. PSW: Program Status Word ........................................................ 123 SFR Definition 9.1. PSBANK: Program Space Bank Select ....................................... 127 SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 133 SFR Definition 10.2. EMI0CF: External Memory Configuration .................................. 134 SFR Definition 10.3. EMI0TC: External Memory Timing Control ................................ 139 SFR Definition 11.1. DMA0EN: DMA0 Channel Enable ............................................. 151 SFR Definition 11.2. DMA0INT: DMA0 Full-Length Interrupt ...................................... 152 SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt ..................................... 153 SFR Definition 11.4. DMA0BUSY: DMA0 Busy .......................................................... 154 SFR Definition 11.5. DMA0SEL: DMA0 Channel Select for Configuration ................. 155 SFR Definition 11.6. DMA0NMD: DMA Channel Mode .............................................. 156 SFR Definition 11.7. DMA0NCF: DMA Channel Configuration ................................... 157 SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte ........................ 158 SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte ......................... 158 SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte .................... 159 20 Rev. 0.3 Si102x/3x SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte ..................... 159 SFR Definition 11.12. DMA0NSZH: Transfer Size High Byte ..................................... 160 SFR Definition 11.13. DMA0NSZL: Memory Transfer Size Low Byte ........................ 160 SFR Definition 12.1. CRC0CN: CRC0 Control ........................................................... 165 SFR Definition 12.2. CRC0IN: CRC0 Data Input ........................................................ 166 SFR Definition 12.3. CRC0DAT: CRC0 Data Output .................................................. 166 SFR Definition 12.4. CRC0AUTO: CRC0 Automatic Control ...................................... 167 SFR Definition 12.5. CRC0CNT: CRC0 Automatic Flash Sector Count ..................... 167 SFR Definition 12.6. CRC0FLIP: CRC0 Bit Flip .......................................................... 168 SFR Definition 13.1. CRC1CN: CRC1 Control ........................................................... 173 SFR Definition 13.2. CRC1IN: CRC1 Data IN ............................................................ 174 SFR Definition 13.3. CRC1POLL: CRC1 Polynomial LSB .......................................... 174 SFR Definition 13.4. CRC1POLH: CRC1 Polynomial MSB ........................................ 174 SFR Definition 13.5. CRC1OUTL: CRC1 Output LSB ................................................ 175 SFR Definition 13.6. CRC1OUTH: CRC1 Output MSB .............................................. 175 SFR Definition 14.1. AES0BCFG: AES Block Configuration ...................................... 203 SFR Definition 14.2. AES0DCFG: AES Data Configuration ....................................... 204 SFR Definition 14.3. AES0BIN: AES Block Input ........................................................ 205 SFR Definition 14.4. AES0XIN: AES XOR Input ......................................................... 206 SFR Definition 14.5. AES0KIN: AES Key Input .......................................................... 206 SFR Definition 14.6. AES0YOUT: AES Y Output ....................................................... 207 SFR Definition 15.1. ENC0CN: Encoder Decoder 0 Control ...................................... 215 SFR Definition 15.2. ENC0L: ENC0 Data Low Byte ................................................... 216 SFR Definition 15.3. ENC0M: ENC0 Data Middle Byte .............................................. 216 SFR Definition 15.4. ENC0H: ENC0 Data High Byte .................................................. 216 SFR Definition 16.1. SFRPGCN: SFR Page Control .................................................. 224 SFR Definition 16.2. SFRPAGE: SFR Page ............................................................... 225 SFR Definition 16.3. SFRNEXT: SFR Next ................................................................ 226 SFR Definition 16.4. SFRLAST: SFR Last .................................................................. 227 SFR Definition 17.1. IE: Interrupt Enable .................................................................... 242 SFR Definition 17.2. IP: Interrupt Priority .................................................................... 243 SFR Definition 17.3. EIE1: Extended Interrupt Enable 1 ............................................ 244 SFR Definition 17.4. EIP1: Extended Interrupt Priority 1 ............................................ 245 SFR Definition 17.5. EIE2: Extended Interrupt Enable 2 ............................................ 246 SFR Definition 17.6. EIP2: Extended Interrupt Priority 2 ............................................ 247 SFR Definition 17.7. IT01CF: INT0/INT1 Configuration .............................................. 249 SFR Definition 18.1. DEVICEID: Device Identification ................................................ 255 SFR Definition 18.2. REVID: Revision Identification ................................................... 256 SFR Definition 18.3. PSCTL: Program Store R/W Control ......................................... 260 SFR Definition 18.4. FLKEY: Flash Lock and Key ...................................................... 261 SFR Definition 18.5. FLSCL: Flash Scale ................................................................... 262 SFR Definition 18.6. FLWR: Flash Write Only ............................................................ 262 SFR Definition 18.7. FRBCN: Flash Read Buffer Control ........................................... 263 SFR Definition 19.1. PCLKACT: Peripheral Active Clock Enable ............................... 267 SFR Definition 19.2. PCLKEN: Peripheral Clock Enable ............................................ 268 Rev. 0.3 21 Si102x/3x SFR Definition 19.3. CLKMODE: Clock Mode ............................................................ 269 SFR Definition 19.4. PMU0CF: Power Management Unit Configuration ..................... 272 SFR Definition 19.5. PMU0FL: Power Management Unit Flag ................................... 273 SFR Definition 19.6. PMU0MD: Power Management Unit Mode ................................ 274 SFR Definition 19.7. PCON: Power Management Control Register ........................... 275 SFR Definition 20.1. DC0CN: DC-DC Converter Control ........................................... 280 SFR Definition 20.2. DC0CF: DC-DC Converter Configuration .................................. 281 SFR Definition 20.3. DC0MD: DC-DC Converter Mode .............................................. 282 SFR Definition 20.4. DC0RDY: DC-DC Converter Ready Indicator ........................... 283 SFR Definition 21.1. REG0CN: Voltage Regulator Control ........................................ 284 SFR Definition 22.1. VDM0CN: VDD Supply Monitor Control .................................... 289 SFR Definition 22.2. RSTSRC: Reset Source ............................................................ 292 SFR Definition 23.1. CLKSEL: Clock Select ............................................................... 298 SFR Definition 23.2. OSCICN: Internal Oscillator Control .......................................... 299 SFR Definition 23.3. OSCICL: Internal Oscillator Calibration ..................................... 300 SFR Definition 23.4. OSCXCN: External Oscillator Control ........................................ 301 SFR Definition 24.1. RTC0KEY: SmaRTClock Lock and Key .................................... 305 SFR Definition 24.2. RTC0ADR: SmaRTClock Address ............................................ 305 SFR Definition 24.3. RTC0DAT: SmaRTClock Data .................................................. 306 Internal Register Definition 24.4. RTC0CN: SmaRTClock Control ............................. 313 Internal Register Definition 24.5. RTC0XCN: SmaRTClock Oscillator Control ........... 314 Internal Register Definition 24.6. RTC0XCF: SmaRTClock  Oscillator Configuration .......................................... 315 Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration .................... 316 Internal Register Definition 24.8. CAPTUREn: SmaRTClock Timer Capture ............. 317 Internal Register Definition 24.9. ALARM0Bn: SmaRTClock Alarm 0  Match Value ............................................................ 317 Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1  Match Value .......................................................... 318 Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2  Match Value ............................................................ 318 SFR Definition 25.1. PC0MD: PC0 Mode Configuration ............................................. 328 SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration .............................. 329 SFR Definition 25.3. PC0TH: PC0 Threshold Configuration ....................................... 330 SFR Definition 25.4. PC0STAT: PC0 Status .............................................................. 331 SFR Definition 25.5. PC0DCH: PC0 Debounce Configuration High ........................... 332 SFR Definition 25.6. PC0DCL: PC0 Debounce Configuration Low ............................ 333 SFR Definition 25.7. PC0CTR0H: PC0 Counter 0 High (MSB) .................................. 334 SFR Definition 25.8. PC0CTR0M: PC0 Counter 0 Middle .......................................... 334 SFR Definition 25.9. PC0CTR0L: PC0 Counter 0 Low (LSB) ..................................... 334 SFR Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB) ................................ 335 SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle ........................................ 335 SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB) ................................... 335 SFR Definition 25.13. PC0CMP0H: PC0 Comparator 0 High (MSB) .......................... 336 SFR Definition 25.14. PC0CMP0M: PC0 Comparator 0 Middle ................................. 336 22 Rev. 0.3 Si102x/3x SFR Definition 25.15. PC0CMP0L: PC0 Comparator 0 Low (LSB) ............................ 336 SFR Definition 25.16. PC0CMP1H: PC0 Comparator 1 High (MSB) .......................... 337 SFR Definition 25.17. PC0CMP1M: PC0 Comparator 1 Middle ................................. 337 SFR Definition 25.18. PC0CMP1L: PC0 Comparator 1 Low (LSB) ............................ 337 SFR Definition 25.19. PC0HIST: PC0 History ............................................................ 338 SFR Definition 25.20. PC0INT0: PC0 Interrupt 0 ........................................................ 339 SFR Definition 25.21. PC0INT1: PC0 Interrupt 1 ........................................................ 340 SFR Definition 26.1. LCD0Dn: LCD0 Data ................................................................. 342 SFR Definition 26.2. LCD0CN: LCD0 Control Register .............................................. 344 SFR Definition 26.3. LCD0CNTRST: LCD0 Contrast Adjustment .............................. 348 SFR Definition 26.4. LCD0MSCN: LCD0 Master Control ........................................... 349 SFR Definition 26.5. LCD0MSCF: LCD0 Master Configuration .................................. 350 SFR Definition 26.6. LCD0PWR: LCD0 Power ........................................................... 350 SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control ............................. 351 SFR Definition 26.8. LCD0CLKDIVH: LCD0 Refresh Rate Prescaler High Byte ........ 352 SFR Definition 26.9. LCD0CLKDIVL: LCD Refresh Rate Prescaler Low Byte ........... 352 SFR Definition 26.10. LCD0BLINK: LCD0 Blink Mask ................................................ 353 SFR Definition 26.11. LCD0TOGR: LCD0 Toggle Rate ............................................. 354 SFR Definition 26.12. LCD0CF: LCD0 Configuration ................................................. 355 SFR Definition 26.13. LCD0CHPCN: LCD0 Charge Pump Control ............................ 355 SFR Definition 26.14. LCD0CHPCF: LCD0 Charge Pump Configuration .................. 356 SFR Definition 26.15. LCD0CHPMD: LCD0 Charge Pump Mode .............................. 356 SFR Definition 26.16. LCD0BUFCN: LCD0 Buffer Control ......................................... 356 SFR Definition 26.17. LCD0BUFCF: LCD0 Buffer Configuration ............................... 357 SFR Definition 26.18. LCD0BUFMD: LCD0 Buffer Mode ........................................... 357 SFR Definition 26.19. LCD0VBMCF: LCD0 VBAT Monitor Configuration .................. 357 SFR Definition 27.1. XBR0: Port I/O Crossbar Register 0 .......................................... 365 SFR Definition 27.2. XBR1: Port I/O Crossbar Register 1 .......................................... 366 SFR Definition 27.3. XBR2: Port I/O Crossbar Register 2 .......................................... 367 SFR Definition 27.4. P0MASK: Port0 Mask Register .................................................. 368 SFR Definition 27.5. P0MAT: Port0 Match Register ................................................... 368 SFR Definition 27.6. P1MASK: Port1 Mask Register .................................................. 369 SFR Definition 27.7. P1MAT: Port1 Match Register ................................................... 369 SFR Definition 27.8. P0: Port0 .................................................................................... 371 SFR Definition 27.9. P0SKIP: Port0 Skip .................................................................... 371 SFR Definition 27.10. P0MDIN: Port0 Input Mode ...................................................... 372 SFR Definition 27.11. P0MDOUT: Port0 Output Mode ............................................... 372 SFR Definition 27.12. P0DRV: Port0 Drive Strength .................................................. 373 SFR Definition 27.13. P1: Port1 .................................................................................. 373 SFR Definition 27.14. P1SKIP: Port1 Skip .................................................................. 374 SFR Definition 27.15. P1MDIN: Port1 Input Mode ...................................................... 374 SFR Definition 27.16. P1MDOUT: Port1 Output Mode ............................................... 375 SFR Definition 27.17. P1DRV: Port1 Drive Strength .................................................. 375 SFR Definition 27.18. P2: Port2 .................................................................................. 376 SFR Definition 27.19. P2SKIP: Port2 Skip .................................................................. 376 Rev. 0.3 23 Si102x/3x SFR Definition 27.20. P2MDIN: Port2 Input Mode ...................................................... 377 SFR Definition 27.21. P2MDOUT: Port2 Output Mode ............................................... 377 SFR Definition 27.22. P2DRV: Port2 Drive Strength .................................................. 378 SFR Definition 27.23. P3: Port3 .................................................................................. 378 SFR Definition 27.24. P3MDIN: Port3 Input Mode ...................................................... 379 SFR Definition 27.25. P3MDOUT: Port3 Output Mode ............................................... 379 SFR Definition 27.26. P3DRV: Port3 Drive Strength .................................................. 380 SFR Definition 27.27. P4: Port4 .................................................................................. 380 SFR Definition 27.28. P4MDIN: Port4 Input Mode ...................................................... 381 SFR Definition 27.29. P4MDOUT: Port4 Output Mode ............................................... 381 SFR Definition 27.30. P4DRV: Port4 Drive Strength .................................................. 382 SFR Definition 27.31. P5: Port5 .................................................................................. 382 SFR Definition 27.32. P5MDIN: Port5 Input Mode ...................................................... 383 SFR Definition 27.33. P5MDOUT: Port5 Output Mode ............................................... 383 SFR Definition 27.34. P5DRV: Port5 Drive Strength .................................................. 384 SFR Definition 27.35. P6: Port6 .................................................................................. 384 SFR Definition 27.36. P6MDIN: Port6 Input Mode ...................................................... 385 SFR Definition 27.37. P6MDOUT: Port6 Output Mode ............................................... 385 SFR Definition 27.38. P6DRV: Port6 Drive Strength .................................................. 386 SFR Definition 27.39. P7: Port7 .................................................................................. 386 SFR Definition 27.40. P7MDOUT: Port7 Output Mode ............................................... 387 SFR Definition 27.41. P7DRV: Port7 Drive Strength .................................................. 387 SFR Definition 28.1. SMB0CF: SMBus Clock/Configuration ...................................... 394 SFR Definition 28.2. SMB0CN: SMBus Control .......................................................... 396 SFR Definition 28.3. SMB0ADR: SMBus Slave Address ............................................ 398 SFR Definition 28.4. SMB0ADM: SMBus Slave Address Mask .................................. 399 SFR Definition 28.5. SMB0DAT: SMBus Data ............................................................ 400 SFR Definition 29.1. SCON0: Serial Port 0 Control .................................................... 414 SFR Definition 29.2. SBUF0: Serial (UART0) Port Data Buffer .................................. 415 SFR Definition 30.1. SPI0CFG: SPI0 Configuration ................................................... 425 SFR Definition 30.2. SPI0CN: SPI0 Control ............................................................... 426 SFR Definition 30.3. SPI0CKR: SPI0 Clock Rate ....................................................... 427 SFR Definition 30.4. SPI0DAT: SPI0 Data ................................................................. 427 SFR Definition 31.1. SPI1CFG: SPI1 Configuration ................................................... 438 SFR Definition 31.2. SPI1CN: SPI1 Control ............................................................... 439 SFR Definition 31.3. SPI1CKR: SPI1 Clock Rate ....................................................... 440 SFR Definition 31.4. SPI1DAT: SPI1 Data ................................................................. 440 SFR Definition 33.1. CKCON: Clock Control .............................................................. 492 SFR Definition 33.2. TCON: Timer Control ................................................................. 497 SFR Definition 33.3. TMOD: Timer Mode ................................................................... 498 SFR Definition 33.4. TL0: Timer 0 Low Byte ............................................................... 499 SFR Definition 33.5. TL1: Timer 1 Low Byte ............................................................... 499 SFR Definition 33.6. TH0: Timer 0 High Byte ............................................................. 500 SFR Definition 33.7. TH1: Timer 1 High Byte ............................................................. 500 SFR Definition 33.8. TMR2CN: Timer 2 Control ......................................................... 504 24 Rev. 0.3 Si102x/3x SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 505 SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 505 SFR Definition 33.11. TMR2L: Timer 2 Low Byte ....................................................... 506 SFR Definition 33.12. TMR2H Timer 2 High Byte ....................................................... 506 SFR Definition 33.13. TMR3CN: Timer 3 Control ....................................................... 510 SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 511 SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 511 SFR Definition 33.16. TMR3L: Timer 3 Low Byte ....................................................... 512 SFR Definition 33.17. TMR3H Timer 3 High Byte ....................................................... 512 SFR Definition 34.1. PCA0CN: PCA Control .............................................................. 527 SFR Definition 34.2. PCA0MD: PCA Mode ................................................................ 528 SFR Definition 34.3. PCA0PWM: PCA PWM Configuration ....................................... 529 SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 530 SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 531 SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte ..................................... 531 SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 532 SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte ........................... 532 C2 Register Definition 35.1. C2ADD: C2 Address ...................................................... 533 C2 Register Definition 35.2. DEVICEID: C2 Device ID ............................................... 534 C2 Register Definition 35.3. REVID: C2 Revision ID .................................................. 534 C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control ........................ 535 C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data ............................ 535 Rev. 0.3 25 Si102x/3x 1. System Overview Si102x/3x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.                  240-960 MHz EZRadioPRO(R) transceiver Power efficient on-chip dc-dc buck converter High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 300 ksps, or 12-bit 75 ksps single-ended ADC with 16 external analog inputs and 4 internal inputs such as various power supply voltages and the temperature sensor 6-bit programmable current reference Precision programmable 24.5 MHz internal oscillator with spread spectrum technology 128 kB, 64 kB, 32 kB, or 16 kB of on-chip flash memory 8448 or 4352 bytes of on-chip RAM 128 segment LCD driver SMBus/I2C, enhanced UART, and two enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable counter/timer array (PCA) with six capture/compare modules and watchdog timer function Hardware AES, DMA, and pulse counter On-chip power-on reset, VDD monitor, and temperature sensor Two on-chip voltage comparators 53-port I/O With on-chip power-on reset, VDD monitor, watchdog timer, and clock oscillator, the Si102x/3x devices are truly stand-alone system-on-a-chip solutions. The flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-wire (C2) development interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 1.8 to 3.8 V operation over the industrial temperature range (–40 to +85 °C). The port I/O and RST pins are tolerant of input signals up to VIO + 2.0 V. The Si102x/3x devices are available in an 85-pin LGA package that is lead-free and RoHS-compliant. See Table 2.1 for ordering information. Block diagrams are included in Figure 1.1 and Figure 1.2. The transceiver's extremely low receive sensitivity (–121 dBm) coupled with industry leading +13 or +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. The advanced radio features including continuous frequency coverage from 240–960 MHz in 156 Hz or 312 Hz steps allow precise tuning control. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption. 26 Rev. 0.3 Si102x/3x The transceivers digital receive architecture features a high-performance ADC and DSP-based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading, ensuring compliance with global regulations including FCC, ETSI, ARIB, and 802.15.4d. Rev. 0.3 27 Si102x/3x Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 128/64/32/16 kByte ISP Flash Program Memory 256 Byte SRAM 8192/4096 Byte XRAM DMA VREG VREG Analog Power Digital Power Port I/O Configuration Digital Peripherals UART Timers 0/1/2/3 PCA/ WDT SMBus SPI 0 Crossbar Control LCD (4x32) Port 0-1 Drivers Port 2 Drivers 16 P0.0...P1.7 4 P2.4...P2.7 32 C2CK/RST Debug / Programming Hardware C2D Priority Crossbar Decoder Port 3-6 Drivers Port 7 Driver P3.0...P6.7 P7.0/C2D VBAT DCOUT+ VBAT VDD CRC Engine AES Engine Encoder RF XCVR (240-960 MHz, +20/+13 dBm) VCO PA TX AGC DCEN DCIN- DC/DC Buck Converter SYSCLK SFR Bus EMIF Pulse Counter EZRadioPro SPI 1 LNA Mixer PGA Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External Oscillator Circuit Enhanced smaRTClock Oscillator RXp RXn CAP LCD Charge Pump XTAL1 XTAL2 Analog Peripherals Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - ADC Digital Modem Delta Sigma Modulator Digital Logic GND XTAL3 XTAL4 12-bit 75ksps ADC System Clock Configuration 30 MHz + - XOUT XIN Comparators Figure 1.1. Si102x Block Diagram Power On Reset/PMU Wake Reset CIP-51 8051 Controller Core 128/64/32/16 kByte ISP Flash Program Memory 256 Byte SRAM 8192/4096 Byte XRAM DMA VREG VREG Analog Power Digital Power Port I/O Configuration Digital Peripherals UART Timers 0/1/2/3 PCA/ WDT SMBus SPI 0 Crossbar Control Port 0-1 Drivers Port 2 Drivers 16 P0.0...P1.7 4 P2.4...P2.7 32 C2CK/RST Debug / Programming Hardware C2D Priority Crossbar Decoder Port 3-6 Drivers Port 7 Driver P3.0...P6.7 P7.0/C2D VBAT DCOUT+ VBAT VDD CRC Engine AES Engine Encoder RF XCVR (240-960 MHz, +20/+13 dBm) VCO PA TX DCEN DCIN- DC/DC “Buck” Converter SYSCLK SFR Bus EMIF AGC Pulse Counter EZRadioPro SPI 1 LNA Mixer PGA Precision 24.5 MHz Oscillator Low Power 20 MHz Oscillator External Oscillator Circuit Enhanced smaRTClock Oscillator RXp RXn CAP LCD Charge Pump XTAL1 XTAL2 Analog Peripherals Internal VREF External VREF A M U X VDD VREF Temp Sensor GND CP0, CP0A CP1, CP1A + - ADC Digital Modem Delta Sigma Modulator Digital Logic GND XTAL3 XTAL4 12-bit 75ksps ADC System Clock Configuration 30 MHz + - XOUT XIN Comparators Figure 1.2. Si103x Block Diagram 28 Rev. 0.3 Si102x/3x 1.1. Typical Connection Diagram The application shown in Figure 1.7 is designed for a system with a TX/RX direct-tie configuration without the use of a TX/RX switch. Most lower power applications will use this configuration. A complete direct-tie reference design is available from Silicon Laboratories applications support. For applications seeking improved performance in the presence of multipath fading, antenna diversity can be used. Antenna diversity support is integrated into the EZRadioPRO transceiver and can improve the system link budget by 8–10 dB in the presence of these fading conditions, resulting in substantial range increases. A complete Antenna Diversity reference design is available from Silicon Laboratories applications support. supply voltage C6 100p C7 100n C8 1u XOUT nIRQ VDD_MCU VDD_DIG Px.x SDN L1 L2 L4 C3 L3 C2 C4 C1 TX RFp RXn XIN X1 30MHz VDD_RF Si1020/1/2/3 Si1030/1/2/3 GPIO0 GPIO1 GPIO2 VR_DIG 0.1 uF 0.1 uF L6 L5 C9 C5 1u Figure 1.3. Si102x/3x RX/TX Direct-tie Application Example Supply Voltage C6 100 p C7 100 n C8 1u X1 30 MHz XOUT L1 TR & ANT-DIV Switch 1 2 3 6 5 4 C4 L3 C3 L2 C2 C1 TX RXp RXn VDD_RF nIRQ VDD_MCU VDD_DIG Px.x SDN XIN Si102x Si103x GPIO0 GPIO1 GPIO2 VR_DIG 0.1 uF 0.1 uF L4 C9 C5 1u Figure 1.4. Si102x/3x Antenna Diversity Application Example Rev. 0.3 29 Si102x/3x 1.2. CIP-51™ Microcontroller Core 1.2.1. Fully 8051 Compatible The Si102x/3x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052. 1.2.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. 1.2.3. Additional Features The Si102x/3x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides multiple interrupt sources into the CIP-51 allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset when power supply voltage drops below safe levels), a Watchdog Timer, a Missing Clock Detector, SmaRTClock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or flash error may be disabled by the user in software. The WDT may be permanently disabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz and is accurate to ±2% over the full temperature and supply range. The internal oscillator period can also be adjusted by user firmware. An additional 20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. 30 Rev. 0.3 Si102x/3x 1.3. Port Input/Output Digital and analog resources are available through 53 I/O pins. Port pins are organized as eight byte-wide ports. Port pins can be defined as digital or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See Section “35. C2 Interface” on page 533 for more details. The designer has complete control over which digital and analog functions are assigned to individual port pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See Section “27. Port Input/Output” on page 358 for more information on the Crossbar. For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIORF, or VBAT supply pin. Port I/Os used for analog functions can operate up to the supply voltage. See Section “27. Port Input/Output” on page 358 for more information on Port I/O operating modes and the electrical specifications chapter for detailed electrical specifications. Port Match P0MASK, P0MAT P1MASK, P1MAT XBR0, XBR1, XBR2, PnSKIP Registers PnMDOUT, PnMDIN Registers External Interrupts EX0 and EX1 Highest Priority U ART SPI0 SPI1 2 4 2 Priority Decoder 8 P0 I/O Cells P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.7 P4.0 P4.7 P5.0 P5.7 P6.0 P6.7 P7.0 8 P1 I/O Cells P2 I/O Cells (Internal Digital Signals) SMBus 8 CP0 CP1 Outputs SYSCLK PCA 7 2 8 4 Digital Crossbar 8 P3 I/O Cells P4 I/O Cells Lowest Priority T0, T1 8 P0 (Port Latches) 8 P5 I/O Cells 8 P6 (P6.0-P6.7) 1 P7 (P7.0) To Analog Peripherals (ADC0, CP0, and CP1 inputs, VREF, IREF0, AGND) 8 P6 I/O Cells 1 P7 To EMIF To LCD Figure 1.5. Port I/O Functional Block Diagram Rev. 0.3 31 Si102x/3x 1.4. Serial Ports The Si102x/3x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and two Enhanced SPI interfaces. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.5. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with six programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. Each capture/compare module can be configured to operate in a variety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK /12 SYSCLK /4 Timer 0 Overflow ECI SYSCLK External Clock /8 PCA CLOCK MUX 16 -Bit Counter/Timer Capture/ Compare Module 0 Capture/ Compare Module 1 Capture/ Compare Module 2 Capture/ Compare Module 3 Capture/ Compare Module 4 Capture/ Compare Module5 / WDT CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 1.6. PCA Block Diagram 32 Rev. 0.3 Si102x/3x 1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power Burst Mode The ADC0 on Si102x/3x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automatically oversample and average the ADC results. See Section “5.4. 12-Bit Mode” on page 84 for more details on using the ADC in 12-bit mode. The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in single-ended mode and may be configured to measure various different signals using the analog multiplexer described in Section “5.7. ADC0 Analog Multiplexer” on page 95. The voltage reference for the ADC is selected as described in Section “5.9. Voltage and Ground Reference Options” on page 100. ADC0CN VDD AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 ADC0TK Burst Mode Logic Start Conversion ADC0PWR AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 3 Overflow CNVSTR Input From AMUX0 AIN+ SYSCLK REF ADC0H ADC ADC0L 10/12-Bit SAR 16-Bit Accumulator AD0WINT Window Compare Logic AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD08BE AD0TM AMP0GN 32 ADC0LTH ADC0LTL ADC0GTH ADC0GTL ADC0CF Figure 1.7. ADC0 Functional Block Diagram Rev. 0.3 33 Si102x/3x ADC0MX AD0MX4 AD0MX3 AD0MX2 AD0MX1 AM0MX0 P0.0 Programmable Attenuator AIN+ P2.6* Temp Sensor AMUX ADC0 VBAT Digital Supply VDD/DC+ Gain = 0. 5 or 1 *P1.7-P2. 6 only available as inputs on 32- pin packages Figure 1.8. ADC0 Multiplexer Block Diagram 1.7. Programmable Current Reference (IREF0) Si102x/3x devices include an on-chip programmable current reference (source or sink) with two output current settings: low power mode and high current mode. The maximum current output in low power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA steps). 1.8. Comparators Si102x/3x devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) which is shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See Section “22. Reset Sources” on page 285 and the Section “19. Power Management” on page 264 for details on reset sources and low power mode wake-up sources, respectively. The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the system clock is not active. This allows the Comparator to operate and generate an output when the device is in some low power modes. The comparator inputs may be connected to Port I/O pins or to other internal signals. 34 Rev. 0.3 Si102x/3x CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 Analog Input Multiplexer CP0MD0 CP0MD1 CP0RIE CP0FIE Px.x CP0 Rising-edge CP0 Falling-edge CPT0CN VDD CP0 Interrupt CPT0MD CP0 + Px.x Interrupt Logic + D SET CP0 Q D SET Q Px.x GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP0 - (ASYNCHRONOUS) CP0A Px.x Reset Decision Tree Figure 1.9. Comparator 0 Functional Block Diagram CP1EN CPT0CN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 VDD CP1 Interrupt CPT0MD CP1MD0 CP1MD1 CP1RIE CP1FIE CP1 Rising-edge CP1 Falling-edge Analog Input Multiplexer Px.x CP1 + Px.x Interrupt Logic + D SET CP1 Q D SET Q Px.x GND CLR Q CLR Q Crossbar (SYNCHRONIZER) CP1 - (ASYNCHRONOUS) CP1A Px.x Reset Decision Tree Figure 1.10. Comparator 1 Functional Block Diagram Rev. 0.3 35 Si102x/3x 2. Ordering Information Table 2.1. Product Selection Guide 10/12-bit 300/75 ksps ADC channels with internal VREF and temp sensor SmaRTClock Real Time Clock AES 128, 192, 256 Encryption LCD Segments (4-MUX) TX Output Power (dBm) Ordering Part Number Analog Comparators Flash Memory (kB) Digital Port I/Os PCA Channels Timers (16-bit) Enhanced SPI MIPS (Peak) RAM (bytes) SMBus/I2C Si1020-A-GM 25 128 8448 20 128 53  Si1021-A-GM 25 Si1022-A-GM 25 Si1023-A-GM 25 64 32 16 8448 20 128 53  8448 20 128 53  4352 20 128 53                  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) LGA-85 (6x8) Si1024-A-GM 25 128 8448 13 128 53  Si1025-A-GM 25 Si1026-A-GM 25 Si1027-A-GM 25 64 32 16 8448 13 128 53  8448 13 128 53  4352 13 128 53  — — — — — — — — 53  53  53  53  53  53  53  53  Si1030-A-GM 25 128 8448 20 Si1031-A-GM 25 Si1032-A-GM 25 Si1033-A-GM 25 64 32 16 8448 20 8448 20 4352 20 Si1034-A-GM 25 128 8448 13 Si1035-A-GM 25 Si1036-A-GM 25 Si1037-A-GM 25 64 32 16 8448 13 8448 13 4352 13 All packages are lead-free (RoHS Compliant). 36 Rev. 0.3 Package UART Si102x/3x 3. Pinout and Package Definitions Table 3.1. Pin Definitions for the Si102x/3x Name VBAT VBATDC VDC Pin Number A43 A44 A46 Type P In P In P In Description Battery Supply Voltage. Must be 1.8 to 3.8 V. DC0 Input Voltage. Must be 1.8 to 3.8 V. Alternate Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage must always be  VBAT. Software may select this supply voltage to power the digital logic. Positive output of the DC-DC converter. A 1 uF to 10 uF ceramic capacitor is required on this pin when using the DC-DC converter. This pin can supply power to external devices when the DC-DC converter is enabled. DC-DC converter return current path. This pin is typically tied to the ground plane. Required Ground. Required Ground. Required Ground. Required Ground. Required Ground. Required Ground. DC-DC Inductor Pin. This pin requires a 560 nH inductor to VDC if the DC-DC converter is used. I/O Power Supply for P0.0–P1.4 and P2.4–P7.0 pins. This supply voltage must always be  VBAT. I/O Power Supply for P1.5–P2.3 pins. This supply voltage must always be  VBAT Device Reset. Open-drain output of internal POR or VDD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1 k to 5 k pullup to VDD is recommended. See Reset Sources Section for a complete description. Clock signal for the C2 Debug Interface. C2CK P7.0/ A48 D I/O D I/O Port 7.0. This pin can only be used as GPIO. The Crossbar cannot route signals to this pin and it cannot be configured as an analog input. See Port I/O Section for a complete description. Bi-directional data signal for the C2 Debug Interface. C2D D I/O P Out GNDDC GND GND GND GND GND GND IND VIO VIORF RST/ A45 D2 D6 B16 B17 A32 B28 B27 B26 B29 A47 P In G G G G G G P In P In P In D I/O Rev. 0.3 37 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name VLCD P0.0 Pin Number A29 A42 Type P I/O Description LCD Power Supply. This pin requires a 10 µF capacitor to stabilize the charge pump. D I/O or A Port 0.0. See Port I/O Section for a complete description. In A In A Out External VREF Input. Internal VREF Output. External VREF decoupling capacitors are recommended. See ADC0 Section for details. VREF P0.1 A41 D I/O or A Port 0.1. See Port I/O Section for a complete description. In G Optional Analog Ground. See ADC0 Section for details. AGND P0.2 A40 D I/O or A Port 0.2. See Port I/O Section for a complete description. In A In External Clock Input. This pin is the external oscillator return for a crystal or resonator. See Oscillator Section. XTAL1 P0.3 A39 D I/O or A Port 0.3. See Port I/O Section for a complete description. In A Out D In A In External Clock Output. This pin is the excitation driver for an external crystal or resonator. External Clock Input. This pin is the external clock input in external CMOS clock mode. External Clock Input. This pin is the external clock input in capacitor or RC oscillator configurations. See Oscillator Section for complete details. XTAL2 P0.4 A38 D I/O or A Port 0.4. See Port I/O Section for a complete description. In D Out UART TX Pin. See Port I/O Section. TX P0.5 A37 D I/O or A Port 0.5. See Port I/O Section for a complete description. In D In UART RX Pin. See Port I/O Section. RX P0.6 A36 D I/O or A Port 0.6. See Port I/O Section for a complete description. In D In External Convert Start Input for ADC0. See ADC0 section for a complete description. CNVSTR 38 Rev. 0.3 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name P0.7 IREF0 P1.0 A34 Pin Number A35 Type Description D I/O or A Port 0.7. See Port I/O Section for a complete description. In A Out IREF0 Output. See IREF Section for complete description. D I/O or A In D I/O Port 1.0. See Port I/O Section for a complete description. May also be used as SCK for SPI0. Pulse Counter 0. Port 1.1. See Port I/O Section for a complete description. May also be used as MISO for SPI0. Pulse Counter 1. Port 1.2. See Port I/O Section for a complete description. May also be used as MOSI for SPI0. SmaRTClock Oscillator Crystal Input. Port 1.3. See Port I/O Section for a complete description. May also be used as NSS for SPI0. SmaRTClock Oscillator Crystal Output. Port 1.4. See Port I/O Section for a complete description. Port 1.5. See Port I/O Section for a complete description. Port 1.6. See Port I/O Section for a complete description. Port 1.7. See Port I/O Section for a complete description. Port 2.4. See Port I/O Section for a complete description. PC0 P1.1 A33 D I/O or A In D I/O PC1 P1.2 A31 D I/O or A In A In XTAL3 P1.3 A30 D I/O or A In A Out XTAL4 P1.4 P1.5 P1.6 P1.7 P2.4 A28 A27 A26 D7 A12 D I/O or A In D I/O or A In D I/O or A In D I/O or A In D I/O or A In AO COM0 P2.5 B10 LCD Common Pin 0 (Backplane Driver) Port 2.5. See Port I/O Section for a complete description. D I/O or A In AO COM1 P2.6 A11 LCD Common Pin 1 (Backplane Driver) Port 2.6. See Port I/O Section for a complete description. D I/O or A In AO COM2 LCD Common Pin 2 (Backplane Driver) Rev. 0.3 39 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name P2.7 Pin Number A10 Type D I/O or A In AO A9 D I/O or A In AO A8 D I/O or A In AO A7 D I/O or A In AO A6 D I/O or A In AO A5 D I/O or A In AO A4 D I/O or A In AO A3 D I/O or A In AO A2 D I/O or A In AO A1 D I/O or A In AO Description Port 2.7. See Port I/O Section for a complete description. COM2 P3.0 LCD Common Pin 3 (Backplane Driver) Port 3.0. See Port I/O Section for a complete description. LCD0 P3.1 LCD Segment Pin 0 Port 3.1. See Port I/O Section for a complete description. LCD1 P3.2 LCD Segment Pin 1 Port 3.2. See Port I/O Section for a complete description. LCD2 P3.3 LCD Segment Pin 2 Port 3.3. See Port I/O Section for a complete description. LCD3 P3.4 LCD Segment Pin 3 Port 3.4. See Port I/O Section for a complete description. LCD4 P3.5 LCD Segment Pin 4 Port 3.5. See Port I/O Section for a complete description. LCD5 P3.6 LCD Segment Pin 5 Port 3.6. See Port I/O Section for a complete description. LCD6 P3.7 LCD Segment Pin 6 Port 3.7. See Port I/O Section for a complete description. LCD7 P4.0 LCD Segment Pin 7 Port 4.0. See Port I/O Section for a complete description. LCD8 LCD Segment Pin 8 40 Rev. 0.3 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name P4.1 Pin Number B25 Type D I/O or A In AO B24 D I/O or A In AO B23 D I/O or A In AO D4/D8 D I/O or A In AO B22 D I/O or A In AO B21 D I/O or A In AO B20 D I/O or A In AO B19 D I/O or A In AO B18 D I/O or A In AO B15 D I/O or A In AO Description Port 4.1. See Port I/O Section for a complete description. LCD9 P4.2 LCD Segment Pin 9 Port 4.2. See Port I/O Section for a complete description. LCD10 P4.3 LCD Segment Pin 10 Port 4.3. See Port I/O Section for a complete description. LCD11 P4.4 LCD Segment Pin 11 Port 4.4. See Port I/O Section for a complete description. LCD12 P4.5 LCD Segment Pin 12 Port 4.5. See Port I/O Section for a complete description. LCD13 P4.6 LCD Segment Pin 13 Port 4.6. See Port I/O Section for a complete description. LCD14 P4.7 LCD Segment Pin 14 Port 4.7. See Port I/O Section for a complete description. LCD15 P5.0 LCD Segment Pin 15 Port 5.0. See Port I/O Section for a complete description. LCD16 P5.1 LCD Segment Pin 16 Port 5.1. See Port I/O Section for a complete description. LCD17 P5.2 LCD Segment Pin 17 Port 5.2. See Port I/O Section for a complete description. LCD18 LCD Segment Pin 18 Rev. 0.3 41 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name P5.3 Pin Number B14 Type D I/O or A In AO B13 D I/O or A In AO B12 D I/O or A In AO B9 D I/O or A In AO B8 D I/O or A In AO B7 D I/O or A In AO B6 D I/O or A In AO B5 D I/O or A In AO B4 D I/O or A In AO B3 D I/O or A In AO Description Port 5.3. See Port I/O Section for a complete description. LCD19 P5.4 LCD Segment Pin 19 Port 5.4. See Port I/O Section for a complete description. LCD20 P5.5 LCD Segment Pin 20 Port 5.5. See Port I/O Section for a complete description. LCD21 P5.6 LCD Segment Pin 21 Port 5.6. See Port I/O Section for a complete description. LCD22 P5.7 LCD Segment Pin 22 Port 5.7. See Port I/O Section for a complete description. LCD23 P6.0 LCD Segment Pin 23 Port 6.0. See Port I/O Section for a complete description. LCD24 P6.1 LCD Segment Pin 24 Port 6.1. See Port I/O Section for a complete description. LCD25 P6.2 LCD Segment Pin 25 Port 6.2. See Port I/O Section for a complete description. LCD26 P6.3 LCD Segment Pin 26 Port 6.3. See Port I/O Section for a complete description. LCD27 P6.4 LCD Segment Pin 27 Port 6.4. See Port I/O Section for a complete description. LCD28 LCD Segment Pin 28 42 Rev. 0.3 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name P6.5 Pin Number B2 Type D I/O or A In AO B1 D I/O or A In AO D1/D5 D I/O or A In AO A17 A18 A19 A20 A16 A21 P In AO AI AI — DO Description Port 6.5. See Port I/O Section for a complete description. LCD29 P6.6 LCD Segment Pin 29 Port 6.6. See Port I/O Section for a complete description. LCD30 P6.7 LCD Segment Pin 30 Port 6.7. See Port I/O Section for a complete description. LCD31 VDD_RF TX RXp RXn NC ANT_A LCD Segment Pin 31 +1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators. The recommended VDD supply voltage is +3.3 V Transmit output pin. The PA output is an open-drain connection so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. Differential RF input pins of the LNA. See application schematic for example matching network. No Connect. Not connected internally to any circuitry. Extra antenna or TR switch control to be used if more GPIO are required. Pin is a hardwired version of GPIO setting 11000, Antenna 2 and can be manually controlled by the antdiv[2:0] bits in register 08h. See register description of 08h. General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, T/R switch, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. Regulated Output Voltage of the Digital 1.7 V regulator. A 1 µF decoupling capacitor is required. +1.8 to +3.6 V supply voltage input to the Digital +1.7 V  regulator. The recommended VDD supply voltage is +3.3 V. General Microcontroller Interrupt Status output. When the EZRadioPRO transceiver exhibits anyone of the Interrupt Events, the nIRQ pin will be set low. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. GPIO_0 GPIO_1 GPIO_2 A22 A23 A24 D I/O D I/O D I/O VR_DIG VDD_DIG nIRQ D3 A25 B11 P Out P In DO Rev. 0.3 43 Si102x/3x Table 3.1. Pin Definitions for the Si102x/3x (Continued) Name XOUT Pin Number A13 Type DI or A I/O Description Crystal Oscillator Output/External Reference Input. Connect to an external 30 MHz crystal or to an external source. If using an external source with no crystal, then DC coupling with a nominal 0.8 VDC level is recommended with a minimum amplitude of 700 mVpp. Crystal Oscillator Input. Connect to an external 30 MHz crystal or leave floating when driving with an external source on XOUT. Shutdown input pin. SDN should be low in all modes except Shutdown mode. When SDN is high, the radio will be completely shut down, and the contents of the registers will be lost. XIN A14 DO or A I/O DI SDN A15 44 Rev. 0.3 Si102x/3x P0.2/XTAL1/ADC2 P0.3/XTAL2/ADC3 P0.1/AGND/ADC1 P0.0/VREF/ADC0 RSTB/C2CK P7.0/C2D VBATDC GNDDC VBAT VDC P4.2/LCD10 P6.7/LCD31 D1 P4.3/LCD11 P4.1/LCD9 VIORF GND IND VIO A48 A47 A46 A45 A44 A43 A42 A41 A40 A39 D4 P4.4/LCD12 P4.0/LCD8 A1 D5 B29 B28 B27 B26 B25 B24 B23 D8 A38 P0.4/TX/ADC4 P3.7/LCD7 P6.6/LCD30 P3.6/LCD6 P6.5/LCD29 P3.5/LCD5 P6.4/LCD28 P3.4/LCD4 P6.3/LCD27 P3.3/LCD3 P6.2/LCD26 P3.2/LCD2 P6.1/LCD25 P3.1/LCD1 P6.0/LCD24 P3.0/LCD0 P5.7/LCD23 P2.7/COM3 P5.6/LCD22 P2.6/COM2 P2.5/COM1 P2.4/COM0 nIRQ XOUT A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 B8 A10 B9 A11 B10 A12 B11 A13 B12 B13 B14 B15 B18 B19 B20 B21 B22 A37 P0.5/RX/ADC5 P4.5/LCD13 A36 P0.6/CNVSTR/ADC6 P4.6/LCD14 A35 P0.7/IREF/ADC7 P4.7/LCD15 A34 P1.0/PC0 P5.0/LCD16 A33 P1.1/PC1 P5.1/LCD17 Si1020-A-GM Top View A32 B17 A31 B16 A30 GND GND P1.2/XTAL3 GND P1.3/XTAL4 P5.2/LCD18 A29 VLCD P5.3/LCD19 P1.4/ADC8 P5.4/LCD20 A28 A27 P1.5/INT01/ADC9 P5.5/LCD21 A26 P1.6/INT01/ADC10 XIN A14 D6 D7 A25 VDD_DIG P1.7/ADC11 GND D2 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 D3 VR_DIG VDD_RF SDN RXN TX GPIO_0 GPIO_1 Figure 3.1. LGA-85 Pinout Diagram (Top View) Rev. 0.3 GPIO_2 RXP ANT_A NC 45 Si102x/3x 3.1. LGA-85 Package Specifications 3.1.1. Package Drawing   D A D3 Pi n A1 ID E E3 E2 E1 (3.385) D1 D2 e 8 5X bxb d dd CAB (bxb) Figure 3.2. LGA-85 Package Drawing Table 3.2. LGA-85 Package Dimensions Dimension A b D D1 D2 D3 e E — — — Min 0.74 0.25 Nom 0.84 0.30 6.00 BSC. 2.40 5.50 3.00 0.50 BSC. 8.00 BSC. — — — Max 0.94 0.35 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 46 Rev. 0.3 Si102x/3x Table 3.2. LGA-85 Package Dimensions (Continued) Dimension E1 E2 E3 L1 aaa bbb ccc ddd Min — — — — — — — — Nom 5.60 5.00 7.50 0.10 — — — — Max — — — — 0.10 0.10 0.08 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 0.3 47 Si102x/3x 3.1.2. Land Pattern   C1 P1 DETAIL "A" C2 P2 (3.385) (f X f) f xf Figure 3.3. LGA-85 Land Pattern Table 3.3. LGA-85 Land Pattern Dimensions Symbol C1 C2 e f P1 P2 Max (mm) 5.50 7.50 0.50 0.35 2.40 5.60 Notes: General 1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05mm is assumed. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. A 2x3 array of 0.72x1.45mm openings on 1.77 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 48 Rev. 0.3 Si102x/3x 3.1.3. Soldering Guidelines 3.1.3.1. Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 3.1.3.2. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x3 array of 0.72x1.45 mm openings on 1.77 mm pitch should be used for the center ground pad. Opening size may be reduced as needed to adjust ratio of solder on center ground pad to solder of signal pins. Excessive solder on center pad may cause opens on signal pins. 3.1.3.3. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components (>245 °C for >20 seconds at peak). Rev. 0.3 49 Si102x/3x 4. Electrical Characteristics Throughout the MCU Electrical Characteristics chapter:  “VDD” refers to the VBAT or VBATDC Supply Voltage.  “VIO” refers to the VIO or VIORF Supply Voltage. 4.1. Absolute Maximum Specifications Table 4.1. Absolute Maximum Ratings Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Port I/O Pin or RST with Respect to GND Voltage on VDD with Respect to GND Maximum Total Current through VDD or GND Maximum Current through RST or any Port Pin Maximum Total Current through all Port Pins Conditions Min –55 –65 –0.3 –0.3 — — — Typ — — — — — — — Max 125 150 VIO + 2 4.0 500 100 200 Units °C °C V V mA mA mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 50 Rev. 0.3 Si102x/3x 4.2. MCU Electrical Characteristics Table 4.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage (VDD) Minimum RAM Data  Retention Voltage1 SYSCLK (System Clock)2 TSYSH (SYSCLK High Time) TSYSL (SYSCLK Low Time) Specified Operating  Temperature Range Conditions not in sleep mode in sleep mode Min 1.8 — — 0 18 18 –40 Typ 1.4 0.3 — — — — Max 3.8 — 0.5 25 — — +85 Units V V MHz ns ns °C Table 4.3. Digital Supply Current at VBAT pin with DC-DC Converter Enabled –40 to +85 °C, VBAT = 3.6V, VDC = 1.9V, 24.5 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max Units Digital Supply Current—CPU Active (Normal Mode, fetching instructions from flash, no external load) IBAT 1,2,3 VBAT= 3.0 V VBAT= 3.3 V VBAT= 3.6 V IBAT1 sourcing 9 mA to external device sourcing 19 mA to external device — — — — — 4.5 4.3 4.2 6.5 13 — — — — — mA mA mA mA mA Digital Supply Current—CPU Inactive (Sleep Mode, sourcing current to external device) Notes: 1. Based on device characterization data; Not production tested. 2. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The supply current will vary slightly based on the physical location of this code in flash. As described in the Flash Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses and power consumption. 3. Includes oscillator and regulator supply current. Rev. 0.3 51 Si102x/3x Table 4.4. Digital Supply Current with DC-DC Converter Disabled –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max Units Digital Supply Current - Active Mode, No Clock Gating (PCLKACT=0x0F) (CPU Active, fetching instructions from flash) IDD 3, 4 VDD = 1.8–3.8 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.8 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.8 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.8 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency  Sensitivity 1, 3 — — — — — — 4.9 3.9 175 190 85 183 6.2 — — — — — mA mA µA µA µA µA/MHz VDD = 1.8–3.8 V, T = 25 °C Digital Supply Current - Active Mode, All Peripharal Clocks Disabled (PCLKACT=0x00) (CPU Active, fetching instructions from flash) IDD 3, 4 VDD = 1.8–3.8 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.8 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.8 V, F = 1 MHz (includes external oscillator/GPIO current) IDD Frequency  Sensitivity 1, 3 — — — — — 3.9 3.1 165 180 TBD -— — — — mA mA µA µA µA/MHz VDD = 1.8–3.8 V, T = 25 °C Digital Supply Current—Idle Mode (CPU Inactive, not fetching instructions from flash) IDD4 VDD = 1.8–3.8 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.8 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.8 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.8 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency Sensitivity1 VDD = 1.8–3.8 V, T = 25 °C — — — — — — 3.5 2.6 340 360 2305 135 — — — — — — mA mA µA µA µA µA/MHz 52 Rev. 0.3 Si102x/3x Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max Units Digital Supply Current— Low Power Idle Mode, All peripheral clocks enabled (PCLKEN = 0x0F) (CPU Inactive, not fetching instructions from flash) IDD4, 6 VDD = 1.8–3.8 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.8 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.8 V, F = 1 MHz (includes external oscillator/GPIO current) VDD = 1.8–3.8 V, F = 32.768 kHz (includes SmaRTClock oscillator current) IDD Frequency Sensitivity1 VDD = 1.8–3.8 V, T = 25 °C — — — — — — 1.5 1.07 270 280 2325 475 1.9 — — — — — mA mA µA µA µA µA/MHz Digital Supply Current— Low Power Idle Mode, All Peripheral Clocks Disabled (PCLKEN = 0x00) (CPU Inactive, not fetching instructions from flash) IDD4, 7 VDD = 1.8–3.8 V, F = 24.5 MHz (includes precision oscillator current) VDD = 1.8–3.8 V, F = 20 MHz (includes low power oscillator current) VDD = 1.8 V, F = 1 MHz VDD = 3.8 V, F = 1 MHz (includes external oscillator/GPIO current) IDD Frequency Sensitivity1 Digital Supply Current  (Suspend Mode) VDD = 1.8–3.8 V, T = 25 °C VDD = 1.8 V VDD = 3.8 V — — — — — 620 340 TBD TBD 115 77 84 TBD — — — — µA µA µA µA µA/MHz Digital Supply Current—Suspend Mode — — — — µA Rev. 0.3 53 Si102x/3x Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current  (Sleep Mode, SmaRTClock running, internal LFO, LCD Contrast Mode 1, charge pump disabled, 60 Hz refresh rate, driving 32 segment pins w/ no load) Conditions 1.8 V, T = 25 °C, static LCD 3.0 V, T = 25 °C, static LCD 3.8 V, T = 25 °C, static LCD 1.8 V, T = 25 °C, 2-Mux LCD 3.0 V, T = 25 °C, 2-Mux LCD 3.8 V, T = 25 °C, 2-Mux LCD 1.8 V, T = 25 °C, 4-Mux LCD 3.0 V, T = 25 °C, 4-Mux LCD 3.8 V, T = 25 °C, 4-Mux LCD 1.8 V, T = 25 °C, static LCD 3.0 V, T = 25 °C, static LCD 3.8 V, T = 25 °C, static LCD 1.8 V, T = 25 °C, 2-Mux LCD 3.0 V, T = 25 °C, 2-Mux LCD 3.8 V, T = 25 °C, 2-Mux LCD 1.8 V, T = 25 °C, 4-Mux LCD 3.0 V, T = 25 °C, 4-Mux LCD 3.8 V, T = 25 °C, 4-Mux LCD 1.8 V, T = 25 °C, static LCD 1.8 V, T = 25 °C, 2-Mux LCD 1.8 V, T = 25 °C, 3-Mux LCD 1.8 V, T = 25 °C, 4-Mux LCD Min — — — — — — — — — — — — — — — — — — — — — — Typ 0.4 0.6 0.8 0.9 1.1 1.3 1.2 1.4 1.6 0.8 1.1 1.4 1.2 1.7 2.0 1.4 1.8 2.1 1.2 1.6 1.8 2.0 Max — — — — — — — — — — — — — — — — — — — — — — Units µA Digital Supply Current—Sleep Mode (LCD Enabled, RTC enabled) µA µA Digital Supply Current  (Sleep Mode, SmaRTClock running, 32.768 kHz Crystal, LCD Contrast Mode 1, charge pump disabled, 60 Hz refresh rate, driving 32 segment pins w/ no load) µA µA µA Digital Supply Current  (Sleep Mode, SmaRTClock running, internal LFO, LCD Contrast Mode 3 (2.7 V), charge pump enabled, 60 Hz refresh rate, driving 32 segment pins w/ no load) Digital Supply Current  (Sleep Mode, SmaRTClock running, 32.768 kHz Crystal, LCD Contrast Mode 3 (2.7 V), charge pump enabled, 60 Hz refresh rate, driving 32 segment pins w/ no load) µA 1.8 V, T = 25 °C, static LCD 1.8 V, T = 25 °C, 2-Mux LCD 1.8 V, T = 25 °C, 3-Mux LCD 1.8 V, T = 25 °C, 4-Mux LCD — — — — 1.3 1.8 1.8 2.0 — — — — µA 54 Rev. 0.3 Si102x/3x Table 4.4. Digital Supply Current with DC-DC Converter Disabled (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current (Sleep Mode, SmaRTClock running, 32.768 kHz crystal) Conditions 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.8 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.8 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.8 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.8 V, T = 85 °C (includes SmaRTClock oscillator and VBAT Supply Monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.8 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.8 V, T = 85 °C (includes POR supply monitor) 1.8 V, T = 25 °C 3.0 V, T = 25 °C 3.8 V, T = 25 °C 1.8 V, T = 85 °C 3.0 V, T = 85 °C 3.8 V, T = 85 °C Min — — — — — — — — — — — — Typ 0.40 0.60 0.70 1.56 2.38 2.79 Max — — — — — — — — — — — — Units µA Digital Supply Current—Sleep Mode (LCD disabled, RTC enabled) Digital Supply Current (Sleep Mode, SmaRTClock running, internal LFO) 0.20 0.30 0.40 1.30 2.06 2.41 µA Digital Supply Current—Sleep Mode (LCD disabled, RTC disabled) Digital Supply Current (Sleep Mode) — — — — — — — — — — — — 0.05 0.07 0.11 1.13 1.83 2.25 0.01 0.02 0.03 TBD TBD TBD — — — — — — — — — — — — µA Digital Supply Current (Sleep Mode, VBAT Supply Monitor Disabled) µA Notes: 1. Based on device characterization data; Not production tested. 2. SYSCLK must be at least 32 kHz to enable debugging. 3. Active Current measure using typical code loop - Digital Supply Current depends upon the particular code being executed. Digital Supply Current depends on the particular code being executed. The values in this table are obtained with the CPU executing a mix of instructions in two loops: djnz R1, $, followed by a loop that accesses an SFR, and moves data around using the CPU (between accumulator and b-register). The supply current will vary slightly based on the physical location of this code in flash. As described in the Flash Memory chapter, it is best to align the jump addresses with a flash word address (byte location /4), to minimize flash accesses and power consumption. 4. Includes oscillator and regulator supply current. 5. Using SmaRTClock osillator with external 32.768 kHz CMOS clock. Does not include crystal bias current. 6. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x0F. 7. Low-Power Idle mode current measured with CLKMODE = 0x04, PCON = 0x01, and PCLKEN = 0x00. Rev. 0.3 55 Si102x/3x 7 6 Active 5 IDD (mA) 4 Idle 3 2 LP Idle (PCLKEN=0x0F) 1 LP Idle (PCLKEN=0x00) 0 0 5 10 15 Frequency (MHz) Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) 20 25 30 56 Rev. 0.3 Si102x/3x Table 4.5. Port I/O DC Electrical Characteristics VIO = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified. Parameters Conditions IOH = –3 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull Low Drive Strength, PnDRV.n = 0 IOH = –1 mA, Port I/O push-pull IOH = –10 µA, Port I/O push-pull IOH = –3 mA, Port I/O push-pull Min VIO– 0.7 VIO – 0.1 Typ Max Units Output High Voltage High Drive Strength, PnDRV.n = 1 — — See Chart V VIO – 0.7 VIO – 0.1 — — — See Chart — — — — — Output Low Voltage High Drive Strength, PnDRV.n = 1 IOL = 8.5 mA IOL = 10 µA IOL = 25 mA Low Drive Strength, PnDRV.n = 0 IOL = 1.4 mA IOL = 10 µA IOL = 4 mA Input High Voltage Input Low Voltage VDD = 2.0 to 3.8 V VDD = 1.8 to 2.0 V VDD = 2.0 to 3.8 V VDD = 1.8 to 2.0 V Input Leakage  Current Weak Pullup Off Weak Pullup On, VIN = 0 V, VDD = 1.8 V Weak Pullup On, Vin = 0 V, VDD = 3.8 V — — — VIO – 0.6 0.7 x VIO — — — — — — — See Chart — — — — — 4 20 0.6 0.1 — — — 0.6 0.3 x VIO ±1 — 35 µA V V V V — — — — — See Chart 0.6 0.1 — V Rev. 0.3 57 Si102x/3x Typical VOH (High Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 5 10 15 20 25 30 35 40 45 50 Load Current (mA) Typical VOH (Low Drive Mode) 3.6 3.3 3 2.7 Voltage 2.4 2.1 1.8 1.5 1.2 0.9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Load Current (mA) VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V VDD = 3.6V VDD = 3.0V VDD = 2.4V VDD = 1.8V Figure 4.2. Typical VOH Curves, 1.8–3.8 V 58 Rev. 0.3 Si102x/3x Typical VOL (High Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -80 -70 -60 -50 -40 -30 -20 -10 0 Load Current (mA) Typical VOL (Low Drive Mode) 1.8 VDD = 3.6V 1.5 VDD = 3.0V 1.2 Voltage VDD = 2.4V VDD = 1.8V 0.9 0.6 0.3 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Load Current (mA) Figure 4.3. Typical VOL Curves, 1.8–3.8 V Rev. 0.3 59 Si102x/3x Table 4.6. Reset Electrical Characteristics VDD = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage Conditions IOL = 1.4 mA, VDD = 2.0 to 3.8 V VDD = 1.8 to 2.0 V Min — VDD – 0.6 0.7 x VDD — — — — 1.8 1.7 — 0.45 — 100 Typ — — — — — 4 20 1.85 1.75 — 0.7 1.75 650 Max 0.6 — — 0.6 0.3 x VDD — 35 1.9 1.8 3 1.0 — 1000 Units V V V V V µA V RST Input Low Voltage VDD = 2.0 to 3.8 V VDD = 1.8 to 2.0 V RST Input Pullup Current VDD Monitor Threshold (VRST) VBAT Ramp Time for Power On POR Monitor Threshold (VPOR) Missing Clock Detector Timeout Minimum System Clock w/ Missing Clock Detector Enabled Reset Time Delay Minimum RST Low Time to Generate a System Reset Digital/Analog Monitor Turn-on Time Digital Monitor Supply  Current Analog Monitor Supply  Current RST = 0.0 V, VDD = 1.8 V RST = 0.0 V, VDD = 3.8 V Early Warning Reset Trigger (all power modes except Sleep) VBAT Ramp from 0–1.8 V Brownout Condition (VDD Falling) Recovery from Brownout (VDD Rising) Time from last system clock rising edge to reset initiation System clock frequency which triggers a missing clock detector timeout Delay between release of any reset source and code execution at location 0x0000 ms V µs — 7 10 kHz — 15 — — — 10 — 300 14 14 — — — — — µs µs ns µA µA 60 Rev. 0.3 Si102x/3x Table 4.7. Power Management Electrical Specifications VDD = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified. Parameter Idle Mode Wake-up Time Suspend Mode Wake-up Time Sleep Mode Wake-up Time Conditions CLKDIV = 0x00 Low Power or Precision Osc. Min 2 — — Typ — 400 2 Max 3 — — Units SYSCLKs ns µs Table 4.8. Flash Electrical Characteristics VDD = 1.8 to 3.8 V, –40 to +85 °C unless otherwise specified., Parameter Flash Size Conditions Si1020/24/30/34 Si1021/25/31/35 Si1022/26/32/36 Si1023/27/33/37 Min 131072 65536 32768 16384 20 k 28 57 Typ — — — — 100k 32 64 Max — — — — — 36 71 Endurance Erase Cycle Time Write Cycle Time Units bytes bytes bytes bytes Erase/Write Cycles ms µs Table 4.9. Internal Precision Oscillator Electrical Characteristics VDD = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.8 V 25 °C; includes bias current of 50 µA typical Min 24 — Typ 24.5 300* Max 25 — Units MHz µA *Note: Does not include clock divider or clock tree supply current. Table 4.10. Internal Low-Power Oscillator Electrical Characteristics VDD = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency Oscillator Supply Current  (from VDD) Conditions –40 to +85 °C, VDD = 1.8–3.8 V 25 °C No separate bias current required Min 18 — Typ 20 100* Max 22 — Units MHz µA *Note: Does not include clock divider or clock tree supply current. Rev. 0.3 61 Si102x/3x Table 4.11. SmaRTClock Characteristics VDD = 1.8 to 3.8 V; TA = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings. Parameter Oscillator Frequency (LFO) Conditions Min 13.1 Typ 16.4 Max 19.7 Units kHz Table 4.12. ADC0 Electrical Characteristics VDD = 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified. Parameter Conditions DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) Offset Error Full Scale Error 12-bit mode 10-bit mode 12-bit mode1 10-bit mode 12-bit mode1 10-bit mode 12-bit mode 10-bit mode 12-bit mode2 10-bit mode 12 10 ±1 ±0.5 ±0.8 ±0.5 ±=0.4+t*0.2V/ms t Figure 32.20. POR Glitch Parameters Rev. 0.3 473 Si102x/3x Table 32.6. POR Parameters Parameter Release Reset Voltage Power-On VDD Slope Low VDD Limit Software Reset Pulse Threshold Voltage Reference Slope VDD Glitch Reset Pulse Symbol VRR SVDD VLD TSWRST VTSD k TP Comment tested VDD slope region VLD 3.2 32.8.6. Wake-Up Timer and 32 kHz Clock Source The EZRadioPRO peripheral contains an integrated wake-up timer independent of the SmaRTClock which can be used to periodically wake the chip from SLEEP mode using the interrupt pin. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14–16h, "Wake Up Timer Period". At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The software will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h– 18h. The formula for calculating the Wake-Up Period is the following: WUT  32  M  2 R ms 32 .768 Description R Value in Formula M Value in Formula WUT Register wtr[4:0] wtm[15:0] Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using the R value. Rev. 0.3 479 Si102x/3x Add R/W Function/Description 14 15 16 17 18 R/W R/W R/W R R Wake-Up Timer Period 1 Wake-Up Timer Period 2 Wake-Up Timer Period 3 Wake-Up Timer Value 1 Wake-Up Timer Value 2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h 00h 00h — — wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] wtm[7] wtv[15] wtv[7] wtm[6] wtv[14] wtv[6] wtm[5] wtv[13] wtv[5] wtm[4] wtv[12] wtv[4] wtm[3] wtv[11] wtv[3] wtm[2] wtv[10] wtv[2] wtm[1] wtm[0] wtv[9] wtv[1] wtv[8] wtv[0] There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in “Register 06h. Interrupt Enable 2.” If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 32.23. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h "Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator. The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is typically less than 10 ppm. 480 Rev. 0.3 Si102x/3x Interrupt Enable enwut =1 ( Reg 06h) WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Sleep Ready 1.5 mA Sleep Ready 1.5 mA Sleep Ready 1.5 mA Sleep Current Consumption 1 uA 1 uA 1 uA Interrupt Enable enwut =0 ( Reg 06h) WUT Period GPIOX =00001 nIRQ SPI Interrupt Read Chip State Sleep Current Consumption 1 uA Figure 32.23. WUT Interrupt and WUT Operation 32.8.7. Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R value (“Register 14h. Wake-up Timer Period 1”) is shared Rev. 0.3 481 Si102x/3x between the WUT and the TLDC. The ldc[7:0] bits are located in “Register 19h. Low Duty Cycle Mode Duration.” The time of the TLDC is determined by the formula below: TLDC  ldc [ 7 : 0 ]  42R ms 32 . 768 Figure 32.24. Low Duty Cycle Mode 32.8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current consumption. Add R/W 0B 0C 0D 0E R/W R/W R/W R/W Function/ Description GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration D7 D6 D5 D4 D3 D2 D1 D0 POR Def. gpio0drv[1] gpio0drv[0] gpio1drv[1] gpio1drv[0] gpio2drv[1] gpio2drv[0] extitst[2] pup0 pup1 pup2 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] itsdo dio2 dio1 dio0 00h 00h 00h 00h extitst[1] extitst[0] The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO GPIO0 GPIO1 GPIO2 00000—Default Setting POR POR Inverted Output Clock For a complete list of the available GPIOs see “AN440: EZRadioPRO Detailed Register Descriptions”. The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be 482 Rev. 0.3 Si102x/3x taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. Pin 6, ANT may be used as an alternate to control a TR switch. Pin 6 is a hardwired version of GPIO setting 11000, Antenna 2 Switch used for antenna diversity. It can be manually controlled by the antdiv[2:0] bits in register 08h if antenna diversity is not used. See AN440, register 08h for more details. 32.8.9. Antenna Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an external SPDT RF switch (such as PIN diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits are found in register 08h “Operating & Function Control 2.” The GPIO pins are capable of sourcing up to 5 mA of current, so it may be used directly to forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes. A special antenna diversity algorithm (antdiv[2:0] = 110 or 111) is included that allows for shorter preamble lengths for beacon mode in TDMA-like systems where the arrival of the packet is synchronous to the receiver enable. The recommended preamble length to obtain optimal antenna selection for synchronous mode is 4 bytes. Add R/W Function/Description 08 R/W Operating & Function Control 2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h Table 32.8. Antenna Diversity Control antdiv[2:0] 000 001 010 011 100 101 110 111 RX/TX State GPIO Ant1 GPIO Ant2 0 1 1 0 0 1 1 0 Antenna Diversity Algorithm Antenna Diversity Algorithm Antenna Diversity Algorithm in Beacon Mode Antenna Diversity Algorithm in Beacon Mode Non RX/TX State GPIO Ant1 GPIO Ant2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 32.8.10. RSSI and Clear Channel Assessment Received signal strength indicator (RSSI) is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 32.25 demonstrates the relationship between input power level and RSSI value. The absolute value of the RSSI will change slightly depending on the modem settings. The RSSI may be read at anytime, but Rev. 0.3 483 Si102x/3x an incorrect error may rarely occur. The RSSI value may be incorrect if read during the update period. The update period is approximately 10 ns every 4 Tb. For 10 kbps, this would result in a 1 in 40,000 probability that the RSSI may be read incorrectly. This probability is extremely low, but to avoid this, one of the following options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA). Add R/W 26 27 R R/W Function/Description Received Signal Strength Indicator RSSI Threshold for Clear Channel Indicator D7 rssi[7] rssith[7] D6 rssi[6] rssith[6] D5 rssi[5] rssith[5] D4 rssi[4] rssith[4] D3 rssi[3] rssith[3] D2 rssi[2] rssith[2] D1 rssi[1] rssith[1] D0 rssi[0] rssith[0] POR Def. — 00h For CCA, threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel Indicator." After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this channel is above or below the threshold. If the signal strength is above the programmed threshold then the RSSI status bit, irssi, in "Register 04h. Interrupt/Status 2" will be set to 1. The RSSI status can also be routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110. RSSI vs Input Power 250 200 150 RSSI 100 50 0 -120 -100 -80 -60 -40 -20 0 20 In Pow [dBm] Figure 32.25. RSSI Value vs. Input Power 32.9. Reference Design Reference designs are available at www.silabs.com for many common applications which include recommended schematics, BOM, and layout. TX matching component values for the different frequency bands can be found in the application notes “AN435: Si4032/4432 PA Matching” and “AN436: Si4030/4031/4430/4431 PA Matching.” RX matching component values for different frequency bands can be found in “AN427: EZRadioPRO Si433x and Si443x RX LNA Matching.” 484 Rev. 0.3 GND P1.7 P1.6 P5.5/LCD21 P1.5/CTS P5.4/LCD20 P1.4 P5.3/LCD19 P5.2/LCD18 U1 SI1024-A1-GM NO POP P1.3 R6 NO POP P1.2 R5 P5.1/LCD17 P1.1/PC1 P5.0/LCD16 P1.0/PC0 P4.7/LCD15 P0.7/IREF0 P4.6/LCD14 P0.6/CNVSTR P4.5/LCD13 P0.5/RX P0.4/TX P4.4/LCD12 Rev. 0.3 GND TRX1 SMA VBAT VDC VRF CC1 SJ7 SJ6 SJ5 Si102x/3x 485 CR1 GND 1.0UF Matched to 50 ohm source / load. CM3 LM2 CM2 LM CM L0 C0 1 R13 0.0 L2 NO POP 2 GND C15 2.2UF 0.1UF 100pF 33PF VDD_RF C16 C17 C18 L2 IS AN OPTIONAL PLACEMENT PLACE INSTEAD OF R0 IF FILTERING IS NECESSARY LR2 LR GPIO_2 GPIO_1 CR2 LC RDC ANT_A SDN GPIO_0 P1.7 SJ3 C9 A21 A20 A19 A16 A24 A23 A22 A18 A17 A15 GND GND 100pF 0.1UF C8 X5R 10UF GND TX NC RXP Q2 30MHz RXN SDN ANT_A TZ1430A GPIO_2 GPIO_1 GPIO_0 VDD_RF C10 VDD_RF GND_EPAD E0 4 1 3 2 C11 X1 32.768KHZ-7-T GND SJ4 GND GND IRQ P1.6 D3 D7 A25 A26 B12 A27 B13 A28 B14 A29 B15 A30 B16 A31 B17 A32 B18 A33 B19 A34 B20 A35 B21 A36 B22 A37 A38 D8 D4 VR_DIG P1.7/ADC11 VDD_DIG P1.6/INT01/ADC10 P5.5/LCD21 P1.5/INT01/ADC9 P5.4/LCD20 P1.4/ADC8 P5.3/LCD19 VLCD P5.2/LCD18 P1.3/XTAL4 GND P1.2/XTAL3 GND GND P5.1/LCD17 P1.1/PC1 P5.0/LCD16 P1.0/PC0 P4.7/LCD15 P0.7/IREF/ADC7 P4.6/LCD14 P0.6/CNVSTR/ADC6 P4.5/LCD13 P0.5/RX/ADC5 P0.4/TX/ADC4 P4.4/LCD12 P4.4/LCD12 GND GND XIN XOUT NIRQ P2.4/COM0 P2.5/COM1 P2.6/COM2 P5.6/LCD22 P2.7/COM3 P5.7/LCD23 P3.0/LCD0 P6.0/LCD24 P3.1/LCD1 P6.1/LCD25 P3.2/LCD2 P6.2/LCD26 P3.3/LCD3 P6.3/LCD27 P3.4/LCD4 P6.4/LCD28 P3.5/LCD5 P6.5/LCD29 P3.6/LCD6 P6.6/LCD30 P3.7/LCD7 P4.0/LCD8 P6.7/LCD31 P6.7/LCD31 D2 D6 A14 A13 B11 A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7 B5 A6 B4 A5 B3 A4 B2 A3 B1 A2 A1 D5 D1 P2.4/COM0 P2.5/COM1 P2.6/COM2 P5.6/LCD22 P2.7/COM3 P5.7/LCD23 P3.0/LCD0 P6.0/LCD24 P3.1/LCD1 P6.1/LCD25 P3.2/LCD2 P6.2/LCD26 P3.3/LCD3 P6.3/LCD27 P3.4/LCD4 P6.4/LCD28 P3.5/LCD5 P6.5/LCD29 P3.6/LCD6 P6.6/LCD30 P3.7/LCD7 P4.0/LCD8 P6.7/LCD31 P7.0/C2D RSTB/C2CK VIORF VDC GND GNDDC IND VBATDC VIO VBAT P4.1/LCD P0.0/VREF/ADC0 P4.2/LCD10 P0.1/AGND/ADC1 P4.3/LCD11 P0.2/XTAL1/ADC2 P0.3/XTAL2/ADC3 A48 A47 B29 A46 B28 A45 B27 A44 B26 A43 B25 A42 B24 A41 B23 A40 A39 VBAT R1 1K GND P7.0/C2D RST/C2CK VDD_RF Figure 32.26. Si1024 Split RF TX/RX Direct-Tie Reference Design—Schematic P4.1/LCD9 P0.0/VREF P4.2/LCD10 P0.1/AGND P4.3/LCD11 P0.2/XTAL1 P0.3/XTAL2 C3 X7R 0.01UF VDC GND 0.01UF X7R C6 0.1UF X7R C5 2.2UF X5R C4 0.1UF X7R C13 1 C C2 X7R 0.1UF C1 X5R 2.2UF 1 2 GND 0.56uH Z1 2 L1 A NO-POP VIO VBAT GND Matched to 50 ohm source / load. C19 GPIO1 / VC1 GPIO2 / VC2 LC ANT_A GPIO_0 GPIO_1 GPIO_2 SDN P1.7 SJ3 C9 1.0UF RXN SDN ANT_A GPIO_2 GPIO_1 GPIO_0 VDD_RF C10 100pF GND_EPAD E0 4 1 3 2 GND P1.7 P1.6 P5.5/LCD21 C11 0.1UF P1.5/CTS P5.4/LCD20 P1.4 P5.3/LCD19 P5.2/LCD18 SJ4 GNDGND U1 R6 P1.3 NO POP R5 P1.2 X1 NO POP P5.1/LCD17 P1.1/PC1 P5.0/LCD16 P1.0/PC0 P4.7/LCD15 P0.7/IREF0 P4.6/LCD14 P0.6/CNVSTR P4.5/LCD13 P0.5/RX P0.4/TX P4.4/LCD12 D3 D7 A25 A26 B12 A27 B13 A28 B14 A29 B15 A30 B16 A31 B17 A32 B18 A33 B19 A34 B20 A35 B21 A36 B22 A37 A38 D8 D4 VR_DIG P1.7/ADC11 VDD_DIG P1.6/INT01/ADC10 P5.5/LCD21 P1.5/INT01/ADC9 P5.4/LCD20 P1.4/ADC8 P5.3/LCD19 VLCD P5.2/LCD18 P1.3/XTAL4 GND P1.2/XTAL3 GND GND P5.1/LCD17 P1.1/PC1 P5.0/LCD16 P1.0/PC0 P4.7/LCD15 P0.7/IREF/ADC7 P4.6/LCD14 P0.6/CNVSTR/ADC6 P4.5/LCD13 P0.5/RX/ADC5 P0.4/TX/ADC4 P4.4/LCD12 P4.4/LCD12 GND GND XIN XOUT NIRQ P2.4/COM0 P2.5/COM1 P2.6/COM2 P5.6/LCD22 P2.7/COM3 P5.7/LCD23 P3.0/LCD0 P6.0/LCD24 P3.1/LCD1 P6.1/LCD25 P3.2/LCD2 P6.2/LCD26 P3.3/LCD3 P6.3/LCD27 P3.4/LCD4 P6.4/LCD28 P3.5/LCD5 P6.5/LCD29 P3.6/LCD6 P6.6/LCD30 P3.7/LCD7 P4.0/LCD8 P6.7/LCD31 P6.7/LCD31 D2 D6 A14 A13 B11 A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7 B5 A6 B4 A5 B3 A4 B2 A3 B1 A2 A1 D5 D1 P2.4/COM0 P2.5/COM1 P2.6/COM2 P5.6/LCD22 P2.7/COM3 P5.7/LCD23 P3.0/LCD0 P6.0/LCD24 P3.1/LCD1 P6.1/LCD25 P3.2/LCD2 P6.2/LCD26 P3.3/LCD3 P6.3/LCD27 P3.4/LCD4 P6.4/LCD28 P3.5/LCD5 P6.5/LCD29 P3.6/LCD6 P6.6/LCD30 P3.7/LCD7 P4.0/LCD8 P6.7/LCD31 A 2 C 1 1 2 486 VBAT VDC VRF SJ7 SJ6 SJ5 Si102x/3x Rev. 0.3 GND TRX SMA CM3 LM2 CM2 CC2 100pF C20 GND TX 1 0 RX 0 1 100pF UPG2214TB 4 3 VC2 OUT2 5 2 RF_IN GND 6 1 VC1 OUT1 SJ2 SJ1 U3 R13 0.0 L2 NO POP Switch controls are active low. CC1 GND CR2 LR 2.2UF X5R C15 LM GND GND CM L0 VDD_RF C16 0.1UF L2 IS AN OPTIONAL PLACEMENT PLACE INSTEAD OF R0 IF FILTERING IS NECESSARY GND CR1 GND C17 100pF CH RH 49.9 A24 A23 A22 C18 33PF C0 LH RDC GND XTL-SMT_TZ1430A_30MHZ A21 A20 A19 A18 A17 A16 A15 GND GND Q2 TX NC RXP GND C8 VDD_RF X5R 10UF IRQ P1.6 SI1020-A1-GM 32.768KHZ-7-T P7.0/C2D RSTB/C2CK VIORF VDC GND GNDDC IND VBATDC VIO VBAT P4.1/LCD P0.0/VREF/ADC0 P4.2/LCD10 P0.1/AGND/ADC1 P4.3/LCD11 P0.2/XTAL1/ADC2 P0.3/XTAL2/ADC3 A48 A47 B29 A46 B28 A45 B27 A44 B26 A43 B25 A42 B24 A41 B23 A40 A39 Figure 32.27. Si1020 Switch Matching Reference Design—Schematic GND R1 VBAT 1K C3 X7R 0.01UF P7.0/C2D RST/C2CK VDD_RF P4.1/LCD9 P0.0/VREF P4.2/LCD10 P0.1/AGND P4.3/LCD11 P0.2/XTAL1 P0.3/XTAL2 0.01UF X7R 0.1UF X7R 2.2UF X5R 0.1UF X7R VDC C6 C5 C4 C13 C2 C1 X7R 0.1UF X5R 2.2UF GND GND GND VIO Z1 L1 NO POP 0.56uH VBAT Si102x/3x 32.10. Application Notes and Reference Designs A comprehensive set of application notes and reference designs are available to assist with the development of a radio system. A partial list of applications notes is given below. For the complete list of application notes, latest reference designs and demos visit the Silicon Labs website.                        AN361: Wireless MBUS Implementation using EZRadioPRO Devices AN379: Antenna Diversity with EZRadioPRO AN414: EZRadioPRO Layout Design Guide AN415: EZRadioPRO Programming Guide AN417: Si4x3x Family Crystal Oscillators AN419: ARIB STD-T67 Narrow-Band 426/429 MHz Measured on the Si4431-A0 AN427: EZRadioPRO Si433x and Si443x RX LNA Matching AN429: Using the DC-DC Converter on the F9xx Series MCU for Single Battery Operation with the EZRadioPRO RF Devices AN432: RX BER Measurement on EZRadioPRO with a Looped PN Sequence AN435: Si4032/4432 PA Matching AN436: Si4030/4031/4430/4431 PA Matching AN437: 915 MHz Measurement Results and FCC Compliance AN439: EZRadioPRO Quick Start Guide AN440: Si4430/31/32 Register Descriptions AN445: Si4431 RF Performance and ETSI Compliance Test Results AN451: Wireless M-BUS Software Implementation AN459: 950 MHz Measurement Results and ARIB Compliance AN460: 470 MHz Measurement Results for China AN463: Support for Non-Standard Packet Structures and RAW Mode AN466: Si4030/31/32 Register Descriptions AN467: Si4330 Register Descriptions AN514: Using the EZLink Reference Design to Create a Two-Channel PWM Motor Control Circuit AN539: EZMacPRO Overview 32.11. Customer Support Technical support for the complete family of Silicon Labs wireless products is available by accessing the wireless section of the Silicon Labs' website at www.silabs.com/wireless. For MCU support, please visit www.silabs.com/mcu.  For answers to common questions please visit the wireless and mcu knowledge base at www.silabs.com/support/knowledgebase. Rev. 0.3 487 Si102x/3x 32.12. Register Table and Descriptions Table 32.9. EZRadioPRO Internal Register Descriptions Add R/W Function/Desc 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Device Type Device Version Device Status Interrupt Status 1 Interrupt Status 2 Interrupt Enable 1 Interrupt Enable 2 Operating & Function Control 1 Operating & Function Control 2 Crystal Oscillator Load Capacitance Microcontroller Output Clock GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration ADC Configuration D7 0 0 ffovfl ifferr iswdet enfferr enswdet swres D6 0 0 ffunfl itxffafull ipreaval entxffafull enpreaval enlbd D5 0 0 rxffem itxffaem ipreainval entxffaem enpreainval enwt Data D4 dt[4] vc[4] headerr irxffafull irssi enrxffafull enrssi x32ksel D3 dt[3] vc[3] reserved iext iwut enext enwut txon D2 dt[2] vc[2] reserved ipksent ilbd enpksent enlbd rxon D1 dt[1] vc[1] cps[1] ipkvalid ichiprdy enpkvalid enchiprdy pllon D0 dt[0] vc[0] cps[0] icrcerror ipor encrcerror enpor xton POR Default 00111 06h — — — 00h 03h 01h antdiv[2] xtalshft Reserved gpio0drv[1] gpio1drv[1] gpio2drv[1] Reserved adcstart/adcdone Reserved adc[7] tsrange[1] tvoffs[7] Reserved wtm[15] wtm[7] wtv[15] wtv[7] ldc[7] Reserved 0 dwn3_bypass afcbd swait_timer[1] Reserved rxosr[7] rxosr[10] ncoff[15] ncoff[7] Reserved crgain[7] rssi[7] rssith[7] antdiv[1] xlc[6] Reserved gpio0drv[0] gpio1drv[0] gpio2drv[0] extitst[2] adcsel[2] Reserved adc[6] tsrange[0] tvoffs[6] Reserved wtm[14] wtm[6] wtv[14] wtv[6] ldc[6] Reserved 0 ndec[2] enafc swait_timer[0] Reserved rxosr[6] rxosr[9] ncoff[14] ncoff[6] Reserved crgain[6] rssi[6] rssith[6] antdiv[0] xlc[5] clkt[1] pup0 pup1 pup2 extitst[1] adcsel[1] Reserved adc[5] entsoffs tvoffs[5] Reserved wtm[13] wtm[5] wtv[13] wtv[5] ldc[5] Reserved 0 ndec[1] afcgearh[2] shwait[2] crfast[2] rxosr[5] rxosr[8] ncoff[13] ncoff[5] Reserved crgain[5] rssi[5] rssith[5] rxmpk xlc[4] clkt[0] gpio0[4] gpio1[4] gpio2[4] extitst[0] adcsel[0] Reserved adc[4] entstrim tvoffs[4] wtr[4] wtm[12] wtm[4] wtv[12] wtv[4] ldc[4] lbdt[4] vbat[4] ndec[0] afcgearh[1] shwait[1] crfast[1] rxosr[4] stallctrl ncoff[12] ncoff[4] rxncocomp crgain[4] rssi[4] rssith[4] autotx xlc[3] enlfc gpio0[3] gpio1[3] gpio2[3] itsdo adcref[1] adcoffs[3] adc[3] tstrim[3] tvoffs[3] wtr[3] wtm[11] wtm[3] wtv[11] wtv[3] ldc[3] lbdt[3] vbat[3] filset[3] afcgearh[0] shwait[0] crfast[0] rxosr[3] ncoff[19] ncoff[11] ncoff[3] crgain2x crgain[3] rssi[3] rssith[3] enldm xlc[2] mclk[2] gpio0[2] gpio1[2] gpio2[2] dio2 adcref[0] adcoffs[2] adc[2] tstrim[2] tvoffs[2] wtr[2] wtm[10] wtm[2] wtv[10] wtv[2] ldc[2] lbdt[2] vbat[2] filset[2] 1p5 bypass anwait[2] crslow[2] rxosr[2] ncoff[18] ncoff[10] ncoff[2] crgain[10] crgain[2] rssi[2] rssith[2] ffclrrx xlc[1] mclk[1] gpio0[1] gpio1[1] gpio2[1] dio1 adcgain[1] adcoffs[1] adc[1] tstrim[1] tvoffs[1] wtr[1] wtm[9] wtm[1] wtv[9] wtv[1] ldc[1] lbdt[1] vbat[1] filset[1] matap anwait[1] crslow[1] rxosr[1] ncoff[17] ncoff[9] ncoff[1] crgain[9] crgain[1] rssi[1] rssith[1] ffclrtx xlc[0] mclk[0] gpio0[0] gpio1[0] gpio2[0] dio0 adcgain[0] adcoffs[0] adc[0] tstrim[0] tvoffs[0] wtr[0] wtm[8] wtm[0] wtv[8] wtv[0] ldc[0] lbdt[0] vbat[0] filset[0] ph0size anwait[0] crslow[0] rxosr[0] ncoff[16] ncoff[8] ncoff[0] crgain[8] crgain[0] rssi[0] rssith[0] 00h 7Fh 06h 00h 00h 00h 00h 00h 00h — 20h 00h 03h 00h 01h — — 00h 14h — 01h 40h 0Ah 03h 64h 01h 47h AEh 02h 8Fh — 1Eh 28 29 2A 2B 2C 2D 2E 2F R/W ADC Sensor Amplifier Offset R ADC Value R/W Temperature Sensor Control R/W Temperature Value Offset R/W Wake-Up Timer Period 1 R/W Wake-Up Timer Period 2 R/W Wake-Up Timer Period 3 R Wake-Up Timer Value 1 R Wake-Up Timer Value 2 R/W Low-Duty Cycle Mode Duration R/W Low Battery Detector Threshold R Battery Voltage Level R/W IF Filter Bandwidth R/W AFC Loop Gearshift Override R/W AFC Timing Control R/W Clock Recovery Gearshift Override R/W Clock Recovery Oversampling Ratio R/W Clock Recovery Offset 2 R/W Clock Recovery Offset 1 R/W Clock Recovery Offset 0 R/W Clock Recovery Timing Loop Gain 1 R/W Clock Recovery Timing Loop Gain 0 R Received Signal Strength Indicator R/W RSSI Threshold for Clear Channel Indicator R Antenna Diversity Register 1 R Antenna Diversity Register 2 R/W AFC Limiter R AFC Correction Read R/W OOK Counter Value 1 R/W OOK Counter Value 2 R/W Slicer Peak Hold adrssi1[7] adrssib[7] Afclim[7] afc_corr[9] afc_corr[9] ookcnt[7] Reserved adrssia[6] adrssib[6] Afclim[6] afc_corr[8] afc_corr[9] ookcnt[6] attack[2] adrssia[5] adrssia[4] adrssib[5] adrssib[4] Afclim[5] Afclim[4] afc_corr[7] afc_corr[6] ookfrzen peakdeten ookcnt[5] ookcnt[4] attack[1] attack[0] Reserved adrssia[3] adrssib[3] Afclim[3] afc_corr[5] madeten ookcnt[3] decay[3] adrssia[2] adrssib[2] Afclim[2] afc_corr[4] ookcnt[10] ookcnt[2] decay[2] adrssia[1] adrssib[1] Afclim[1] afc_corr[3] ookcnt[9] ookcnt[1] decay[1] adrssia[0] adrssib[0] Afclim[0] afc_corr[2] ookcnt[8] ookcnt[0] decay[0] — — 00h 00h 18h BCh 26h 488 Rev. 0.3 Si102x/3x Table 32.9. EZRadioPRO Internal Register Descriptions (Continued) Add R/W Function/Desc D7 enpacrx 0 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C-4E 4F 50-5F 60 61 62 63-6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F R/W Data Access Control R EzMAC status R/W Header Control 1 R/W Header Control 2 R/W Preamble Length R/W Preamble Detection Control R/W Sync Word 3 R/W Sync Word 2 R/W Sync Word 1 R/W Sync Word 0 R/W Transmit Header 3 R/W Transmit Header 2 R/W Transmit Header 1 R/W Transmit Header 0 R/W Transmit Packet Length R/W Check Header 3 R/W Check Header 2 R/W Check Header 1 R/W Check Header 0 R/W Header Enable 3 R/W Header Enable 2 R/W Header Enable 1 R/W Header Enable 0 R Received Header 3 R Received Header 2 R Received Header 1 R Received Header 0 R Received Packet Length R/W R/W ADC8 Control Channel Filter Coefficient Address Crystal Oscillator/ Control Test TX Power TX Data Rate 1 TX Data Rate 0 Modulation Mode Control 1 Modulation Mode Control 2 Frequency Deviation Frequency Offset 1 Frequency Offset 2 Frequency Band Select Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 Frequency Hopping Channel Select Frequency Hopping Step Size TX FIFO Control 1 TX FIFO Control 2 RX FIFO Control FIFO Access skipsyn prealen[7] preath[4] sync[31] sync[23] sync[15] sync[7] txhd[31] txhd[23] txhd[15] txhd[7] pklen[7] chhd[31] chhd[23] chhd[15] chhd[7] hden[31] hden[23] hden[15] hden[7] rxhd[31] rxhd[23] rxhd[15] rxhd[7] rxplen[7] Reserved Inv_pre_th[3] Data D6 D5 D4 lsbfrst crcdonly skip2ph rxcrc1 pksrch pkrx bcen[3:0] hdlen[2] hdlen[1] hdlen[0] prealen[6] prealen[5] prealen[4] preath[3] preath[2] preath[1] sync[30] sync[29] sync[28] sync[22] sync[21] sync[20] sync[14] sync[13] sync[12] sync[6] sync[5] sync[4] txhd[30] txhd[29] txhd[28] txhd[22] txhd[21] txhd[20] txhd[14] txhd[13] txhd[12] txhd[6] txhd[5] txhd[4] pklen[6] pklen[5] pklen[4] chhd[30] chhd[29] chhd[28] chhd[22] chhd[21] chhd[20] chhd[14] chhd[13] chhd[12] chhd[6] chhd[5] chhd[4] hden[30] hden[29] hden[28] hden[22] hden[21] hden[20] hden[14] hden[13] hden[12] hden[6] hden[5] hden[4] rxhd[30] rxhd[29] rxhd[28] rxhd[22] rxhd[21] rxhd[20] rxhd[14] rxhd[13] rxhd[12] rxhd[6] rxhd[5] rxhd[4] rxplen[6] rxplen[5] rxplen[4] Reserved Reserved adc8[5] adc8[4] Reserved Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0] D3 enpactx pkvalid fixpklen prealen[3] preath[0] sync[27] sync[19] sync[11] sync[3] txhd[27] txhd[19] txhd[11] txhd[3] pklen[3] chhd[27] chhd[19] chhd[11] chhd[3] hden[27] hden[19] hden[11] hden[3] rxhd[27] rxhd[19] rxhd[11] rxhd[3] rxplen[3] adc8[3] chfiladd[3] D2 D1 encrc crc[1] crcerror pktx hdch[3:0] synclen[1] synclen[0] prealen[2] prealen[1] rssi_off[2] rssi_off[1] sync[26] sync[25] sync[18] sync[17] sync[10] sync[9] sync[2] sync[1] txhd[26] txhd[25] txhd[18] txhd[17] txhd[10] txhd[9] txhd[2] txhd[1] pklen[2] pklen[1] chhd[26] chhd[25] chhd[18] chhd[17] chhd[10] chhd[9] chhd[2] chhd[1] hden[26] hden[25] hden[18] hden[17] hden[10] hden[9] hden[2] hden[1] rxhd[26] rxhd[25] rxhd[18] rxhd[17] rxhd[10] rxhd[9] rxhd[2] rxhd[1] rxplen[2] rxplen[1] D0 crc[0] pksent prealen[8] prealen[0] rssi_off[0] sync[24] sync[16] sync[8] sync[0] txhd[24] txhd[16] txhd[8] txhd[0] pklen[0] chhd[24] chhd[16] chhd[8] chhd[0] hden[24] hden[16] hden[8] hden[0] rxhd[24] rxhd[16] rxhd[8] rxhd[0] rxplen[0] adc8[0] chfiladd[0] POR Default 8Dh — 0Ch 22h 08h 2Ah 2Dh D4h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh — — — — — adc8[2] chfiladd[2] adc8[1] chfiladd[1] 10h 00h R/W pwst[2] pwst[1] Reserved pwst[0] clkhyst Reserved Reserved Reserved txdr[13] txdr[12] txdr[5] txdr[4] txdtrtscale enphpwdn dtmod[1] dtmod[0] fd[5] fd[4] fo[5] fo[4] Reserved Reserved hbsel fb[4] fc[13] fc[12] fc[5] fc[4] enbias2x enamp2x bufovr enbuf 24h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved txdr[15] txdr[7] Reserved trclk[1] fd[7] fo[7] Reserved Reserved fc[15] fc[7] Reserved txdr[14] txdr[6] Reserved trclk[0] fd[6] fo[6] Reserved sbsel fc[14] fc[6] Ina_sw txdr[11] txdr[3] manppol eninv fd[3] fo[3] Reserved fb[3] fc[11] fc[3] txpow[2] txdr[10] txdr[2] enmaninv fd[8] fd[2] fo[2] Reserved fb[2] fc[10] fc[2] txpow[1] txdr[9] txdr[1] enmanch modtyp[1] fd[1] fo[1] fo[9] fb[1] fc[9] fc[1] txpow[0] txdr[8] txdr[0] enwhite modtyp[0] fd[0] fo[0] fo[8] fb[0] fc[8] fc[0] 18h 0Ah 3Dh 0Ch 00h 20h 00h 00h 75h BBh 80h R/W R/W fhch[7] fhs[7] fhch[6] fhs[6] Reserved fhch[5] fhch[4] fhs[5] fhs[4] fhch[3] fhs[3] fhch[2] fhs[2] fhch[1] fhs[1] fhch[0] fhs[0] 00h 00h R/W R/W R/W R/W Reserved Reserved Reserved fifod[7] Reserved Reserved Reserved fifod[6] Reserved txafthr[5] txafthr[4] txaethr[5] txaethr[4] rxafthr[5] rxafthr[4] fifod[5] fifod[4] txafthr[3] txaethr[3] rxafthr[3] fifod[3] txafthr[2] txaethr[2] rxafthr[2] fifod[2] txafthr[1] txaethr[1] rxafthr[1] fifod[1] txafthr[0] txaethr[0] rxafthr[0] fifod[0] 37h 04h 37h — Note: Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions. Rev. 0.3 489 Si102x/3x 32.13. Required Changes to Default Register Values The following register writes should be performed during device initialization. 1. The value 0x40 should be written to Register 59h. 2. If the device will be operated in the 240–320 MHz or 480–640 MHz bands at a temperature above 60 °C, then Register 59h should be written to 0x43 and Register 5Ah should be written to 0x02. 490 Rev. 0.3 Si102x/3x 33. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and Timer 3 have a Capture Mode that can be used to measure the SmaRTClock, Comparator, or external clock period with respect to another oscillator. The ability to measure the Comparator period with respect to another oscillator is particularly useful when interfacing to capacitive sensors. Timer 0 and Timer 1 Modes: 13-bit counter/timer 16-bit counter/timer 8-bit counter/timer with autoreload Two 8-bit counter/timers (Timer 0 only) Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Timer 3 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M– T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which Timer 0 and/or Timer 1 may be clocked (See SFR Definition 33.1 for pre-scaled clock selection). Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked by the external oscillator clock source divided by 8 or the Comparator1 output. Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a frequency of up to one-fourth the system clock frequency can be counted. The input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. Rev. 0.3 491 Si102x/3x SFR Definition 33.1. CKCON: Clock Control Bit Name Type Reset 7 T3MH R/W 0 6 T3ML R/W 0 5 T2MH R/W 0 4 T2ML R/W 0 3 T1M R/W 0 2 T0M R/W 0 1 SCA[1:0] R/W 0 0 0 SFR Page = 0x0; SFR Address = 0x8E Bit Name 7 T3MH Function Timer 3 High Byte Clock Select. Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only). 0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 high byte uses the system clock. 6 T3ML Timer 3 Low Byte Clock Select. Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN. 1: Timer 3 low byte uses the system clock. 5 T2MH Timer 2 High Byte Clock Select. Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only). 0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 high byte uses the system clock. 4 T2ML Timer 2 Low Byte Clock Select. Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN. 1: Timer 2 low byte uses the system clock. 3 T1M Timer 1 Clock Select. Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1. 0: Timer 1 uses the clock defined by the prescale bits SCA[1:0]. 1: Timer 1 uses the system clock. 2 T0M Timer 0 Clock Select. Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1. 0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0]. 1: Counter/Timer 0 uses the system clock. 1:0 SCA[1:0] Timer 0/1 Prescale Bits. These bits control the Timer 0/1 Clock Prescaler: 00: System clock divided by 12 01: System clock divided by 4 10: System clock divided by 48 11: External clock divided by 8 (synchronized with the system clock) 492 Rev. 0.3 Si102x/3x 33.1. Timer 0 and Timer 1 Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (Section “17.5. Interrupt Register Descriptions” on page 241); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register (Section “17.5. Interrupt Register Descriptions” on page 241). Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits T1M1–T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating mode is described below. 33.1.1. Mode 0: 13-bit Counter/Timer Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as described for Timer 0. The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section “27.3. Priority Crossbar Decoder” on page 362 for information on selecting and configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see SFR Definition 33.1). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 17.7). Setting GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see Section “17.5. Interrupt Register Descriptions” on page 241), facilitating pulse width measurements Table 33.1. Timer 0 Running Modes TR0 0 1 1 1 Note: X = Don't Care GATE0 X 0 1 1 INT0 X X 0 1 Counter/Timer Disabled Enabled Disabled Enabled Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see SFR Definition 17.7). Rev. 0.3 493 Si102x/3x CKCON T 3 M H T 3 M L T 2 M H TTTSS 2 1 0CC MMMA A L 10 G A T E 1 C / T 1 TM OD T 1 M 1 T 1 M 0 G A T E 0 C / T 0 T 0 M 1 T 0 M 0 I N 1 P L I N 1 S L 2 IT 0 1 C F I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 P re -s ca le d C lo c k 0 0 SYSCLK 1 1 T0 TR0 G ATE0 C ro ss b a r TCLK IN T 0 IN 0 P L XOR Figure 33.1. T0 Mode 0 Block Diagram 33.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. 33.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0 is active as defined by bit IN0PL in register IT01CF (see Section “17.6. External Interrupts INT0 and INT1” on page 248 for details on the external input signals INT0 and INT1). 494 Rev. 0.3 TCON TL0 (5 b its ) TH0 (8 b its) TF1 TR1 TF0 TR0 IE 1 IT 1 IE 0 IT 0 Inte rru pt Si102x/3x CKCON TTTTTTS 332210C MMMMMMA HLHL 1 S C A 0 G A T E 1 C / T 1 TMOD T 1 M 1 T 1 M 0 G A T E 0 C / T 0 T 0 M 1 T 0 M 0 I N 1 P L I N 1 S L 2 IT01CF I N 1 S L 1 I N 1 S L 0 I N 0 P L I N 0 S L 2 I N 0 S L 1 I N 0 S L 0 Pre-scaled Clock 0 0 SYSCLK 1 1 T0 TCLK TL0 (8 bits) TCON TR0 Crossbar GATE0 TH0 (8 bits) INT0 IN0PL XOR TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt Reload Figure 33.2. T0 Mode 2 Block Diagram 33.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt. Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3. Rev. 0.3 495 Si102x/3x CKCO N TTTTTT 332210 MMMMMM HLHL S C A 1 S C A 0 G A T E 1 C / T 1 TM O D T 1 M 1 T 1 M 0 G A T E 0 C / T 0 T 0 M 1 T 0 M 0 Pre-scaled Clock 0 TR1 TH0 (8 bits) TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt Interrupt SYSCLK 1 0 1 T0 TL0 (8 bits) TR0 Crossbar G ATE0 INT0 IN0PL XOR Figure 33.3. T0 Mode 3 Block Diagram 496 Rev. 0.3 Si102x/3x SFR Definition 33.2. TCON: Timer Control Bit Name Type Reset 7 TF1 R/W 0 6 TR1 R/W 0 5 TF0 R/W 0 4 TR0 R/W 0 3 IE1 R/W 0 2 IT1 R/W 0 1 IE0 R/W 0 0 IT0 R/W 0 SFR Page = All Pages; SFR Address = 0x88; Bit-Addressable Bit Name Function 7 TF1 Timer 1 Overflow Flag. Set to 1 by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 6 5 TR1 TF0 Timer 1 Run Control. Timer 1 is enabled by setting this bit to 1. Timer 0 Overflow Flag. Set to 1 by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 4 3 TR0 IE1 Timer 0 Run Control. Timer 0 is enabled by setting this bit to 1. External Interrupt 1. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine in edge-triggered mode. 2 IT1 Interrupt 1 Type Select. This bit selects whether the configured INT1 interrupt will be edge or level sensitive. INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition 17.7). 0: INT1 is level triggered. 1: INT1 is edge triggered. 1 IE0 External Interrupt 0. This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine in edge-triggered mode. 0 IT0 Interrupt 0 Type Select. This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 17.7). 0: INT0 is level triggered. 1: INT0 is edge triggered. Rev. 0.3 497 Si102x/3x SFR Definition 33.3. TMOD: Timer Mode Bit Name Type Reset 7 GATE1 R/W 0 6 C/T1 R/W 0 5 T1M[1:0] R/W 0 4 3 GATE0 R/W 2 C/T0 R/W 0 1 T0M[1:0] R/W 0 0 0 0 0 SFR Page = 0x0; SFR Address = 0x89 Bit Name 7 GATE1 Function Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in register IT01CF (see SFR Definition 17.7). 6 C/T1 Counter/Timer 1 Select. 0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON. 1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1). 5:4 T1M[1:0] Timer 1 Mode Select. These bits select the Timer 1 operation mode. 00: Mode 0, 13-bit Counter/Timer 01: Mode 1, 16-bit Counter/Timer 10: Mode 2, 8-bit Counter/Timer with Auto-Reload 11: Mode 3, Timer 1 Inactive 3 GATE0 Timer 0 Gate Control. 0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level. 1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 17.7). 2 C/T0 Counter/Timer 0 Select. 0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON. 1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0). 1:0 T0M[1:0] Timer 0 Mode Select. These bits select the Timer 0 operation mode. 00: Mode 0, 13-bit Counter/Timer 01: Mode 1, 16-bit Counter/Timer 10: Mode 2, 8-bit Counter/Timer with Auto-Reload 11: Mode 3, Two 8-bit Counter/Timers 498 Rev. 0.3 Si102x/3x SFR Definition 33.4. TL0: Timer 0 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TL0[7:0] R/W 3 2 1 0 0 0 0 0 SFR Page = 0x0; SFR Address = 0x8A Bit Name 7:0 TL0[7:0] Function Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 33.5. TL1: Timer 1 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TL1[7:0] R/W 3 2 1 0 0 0 0 0 SFR Page = 0x0; SFR Address = 0x8B Bit Name 7:0 TL1[7:0] Function Timer 1 Low Byte. The TL1 register is the low byte of the 16-bit Timer 1. Rev. 0.3 499 Si102x/3x SFR Definition 33.6. TH0: Timer 0 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TH0[7:0] R/W 3 2 1 0 0 0 0 0 SFR Page = 0x0; SFR Address = 0x8C Bit Name 7:0 TH0[7:0] Function Timer 0 High Byte. The TH0 register is the high byte of the 16-bit Timer 0. SFR Definition 33.7. TH1: Timer 1 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 TH1[7:0] R/W 3 2 1 0 0 0 0 0 SFR Page = 0x0; SFR Address = 0x8D Bit Name 7:0 TH1[7:0] Function Timer 1 High Byte. The TH1 register is the high byte of the 16-bit Timer 1. 500 Rev. 0.3 Si102x/3x 33.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period with respect to the system clock is makes using Touch Sense Switches very easy. Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized with the system clock. 33.2.1. 16-bit Timer with Auto-Reload When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2 reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 33.4, and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L) overflow from 0xFF to 0x00. CKCON T2XCLK[1:0] TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 To SMBus To ADC, SMBus SYSCLK / 12 00 TL2 Overflow TR2 TCLK SmaRTClock / 8 Comparator 0 01 11 0 TMR2L TMR2H TMR2CN 1 SYSCLK TMR2RLL TMR2RLH Reload TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Interrupt Figure 33.4. Timer 2 16-Bit Mode Block Diagram Rev. 0.3 501 Si102x/3x 33.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers operate in auto-reload mode as shown in Figure 33.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode. Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows: T2MH 0 0 0 0 1 T2XCLK[1:0] 00 01 10 11 X TMR2H Clock Source SYSCLK / 12 SmaRTClock / 8 Reserved Comparator 0 SYSCLK T2ML 0 0 0 0 1 T2XCLK[1:0] 00 01 10 11 X TMR2L Clock Source SYSCLK / 12 SmaRTClock / 8 Reserved Comparator 0 SYSCLK The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags are not cleared by hardware and must be manually cleared by software. CKCON T2XCLK[1:0] TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 TMR2RLH Reload To SMBus SYSCLK / 12 00 0 SmaRTClock / 8 Comparator 0 01 TR2 11 1 TCLK TMR2H TMR2CN TMR2RLL SYSCLK Reload TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK Interrupt 1 TCLK 0 TMR2L To ADC, SMBus Figure 33.5. Timer 2 8-Bit Mode Block Diagram 33.2.3. Comparator 0/SmaRTClock Capture Mode The Capture Mode in Timer 2 allows either Comparator 0 or the SmaRTClock period to be measured against the system clock or the system clock divided by 12. Comparator 0 and the SmaRTClock period can also be compared against each other. Timer 2 Capture Mode is enabled by setting TF2CEN to 1. Timer 2 should be in 16-bit auto-reload mode when using Capture Mode. 502 Rev. 0.3 Si102x/3x When Capture Mode is enabled, a capture event will be generated either every Comparator 0 rising edge or every 8 SmaRTClock clock cycles, depending on the T2XCLK1 setting. When the capture event occurs, the contents of Timer 2 (TMR2H:TMR2L) are loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set (triggering an interrupt if Timer 2 interrupts are enabled). By recording the difference between two successive timer capture values, the Comparator 0 or SmaRTClock period can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the capture clock to achieve an accurate reading. For example, if T2ML = 1b, T2XCLK1 = 0b, and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every SmaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two successive captures is 5984, then the SmaRTClock clock is as follows: 24.5 MHz/(5984/8) = 0.032754 MHz or 32.754 kHz. This mode allows software to determine the exact SmaRTClock frequency in self-oscillate mode and the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the capacitance of a Touch Sense Switch. T2XCLK[1:0] CKCON TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 SYSCLK / 12 X0 Comparator 0 SmaRTClock / 8 01 11 0 TR2 TCLK TMR2L TMR2H SYSCLK 1 Capture T2XCLK1 TF2CEN TMR2RLL TMR2RLH TMR2CN SmaRTClock / 8 0 TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK1 T2XCLK0 Interrupt Comparator 0 1 Figure 33.6. Timer 2 Capture Mode Block Diagram Rev. 0.3 503 Si102x/3x SFR Definition 33.8. TMR2CN: Timer 2 Control Bit Name Type Reset 7 TF2H R/W 0 6 TF2L R/W 0 5 TF2LEN R/W 0 4 TF2CEN R/W 0 3 T2SPLIT R/W 0 2 TR2 R/W 0 1 0 T2XCLK[1:0] R/W 0 0 SFR Page = All Pages; SFR Address = 0xC8; Bit-Addressable Bit Name Function 7 TF2H Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt service routine. This bit is not automatically cleared by hardware. 6 TF2L Timer 2 Low Byte Overflow Flag. Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will be set when the low byte overflows regardless of the Timer 2 mode. This bit is not automatically cleared by hardware. 5 TF2LEN Timer 2 Low Byte Interrupt Enable. When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are also enabled, an interrupt will be generated when the low byte of Timer 2 overflows. 4 3 TF2CEN T2SPLIT Timer 2 Capture Enable. When set to 1, this bit enables Timer 2 Capture Mode. Timer 2 Split Mode Enable. When set to 1, Timer 2 operates as two 8-bit timers with auto-reload. Otherwise, Timer 2 operates in 16-bit auto-reload mode. 2 TR2 Timer 2 Run Control. Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables TMR2H only; TMR2L is always enabled in split mode. 1:0 T2XCLK[1:0] Timer 2 External Clock Select. This bit selects the “external” and “capture trigger” clock sources for Timer 2. If Timer 2 is in 8-bit mode, this bit selects the “external” clock source for both timer bytes. Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to select between the “external” clock and the system clock for either timer. Note: External clock sources are synchronized with the system clock. 00: External Clock is SYSCLK/12. Capture trigger is SmaRTClock/8. 01: External Clock is Comparator 0. Capture trigger is SmaRTClock/8. 10: External Clock is SYSCLK/12. Capture trigger is Comparator 0. 11: External Clock is SmaRTClock/8. Capture trigger is Comparator 0. 504 Rev. 0.3 Si102x/3x SFR Definition 33.9. TMR2RLL: Timer 2 Reload Register Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2RLL[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0xCA Bit Name 7:0 Function TMR2RLL[7:0] Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 33.10. TMR2RLH: Timer 2 Reload Register High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2RLH[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0xCB Bit Name Function 7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte. TMR2RLH holds the high byte of the reload value for Timer 2. Rev. 0.3 505 Si102x/3x SFR Definition 33.11. TMR2L: Timer 2 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2L[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0xCC Bit Name 7:0 TMR2L[7:0] Timer 2 Low Byte. Function In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8bit mode, TMR2L contains the 8-bit low byte timer value. SFR Definition 33.12. TMR2H Timer 2 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR2H[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0xCD Bit Name 7:0 TMR2H[7:0] Timer 2 Low Byte. Function In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8bit mode, TMR2H contains the 8-bit high byte timer value. 506 Rev. 0.3 Si102x/3x 33.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator source or the SmaRTClock oscillator period with respect to another oscillator. Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source divided by 8, or the SmaRTClock oscillator. The external oscillator source divided by 8 and SmaRTClock oscillator is synchronized with the system clock. 33.3.1. 16-bit Timer with Auto-Reload When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or SmaRTClock oscillator. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 33.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00. CKCON T3XCLK[1:0] TTTTTTSS 3 3 2 2 1 0CC MMMMMM A A HLHL 10 SYSCLK / 12 External Clock / 8 SmaRTClock 00 To ADC 01 11 0 TR3 TCLK TMR3L TMR3H TMR3CN 1 SYSCLK TMR3RLL TMR3RLH Reload TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 Interrupt Figure 33.7. Timer 3 16-Bit Mode Block Diagram Rev. 0.3 507 Si102x/3x 33.3.2. 8-Bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers operate in auto-reload mode as shown in Figure 33.8. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode. Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock source divided by 8, or the SmaRTClock. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN), as follows: T3MH 0 0 0 0 1 T3XCLK[1:0] 00 01 10 11 X TMR3H Clock Source SYSCLK / 12 SmaRTClock Reserved External Clock / 8 SYSCLK T3ML 0 0 0 0 1 T3XCLK[1:0] 00 01 10 11 X TMR3L Clock Source SYSCLK / 12 SmaRTClock Reserved External Clock / 8 SYSCLK The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared by hardware and must be manually cleared by software. CKCON T3XCLK[1:0] TTTTTTSS 3 3 2 2 1 0 CC MMMMMM A A HLHL 10 TMR3RLH Reload SYSCLK / 12 SmaRTClock External Clock / 8 00 0 01 TR3 11 1 Reload TMR3CN TCLK TMR3H TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK1 T3XCLK0 Interrupt TMR3RLL SYSCLK 1 TCLK 0 TMR3L To ADC Figure 33.8. Timer 3 8-Bit Mode Block Diagram 33.3.3. SmaRTClock/External Oscillator Capture Mode The Capture Mode in Timer 3 allows either SmaRTClock or the external oscillator period to be measured against the system clock or the system clock divided by 12. SmaRTClock and the external oscillator period can also be compared against each other. 508 Rev. 0.3 Si102x/3x Setting TF3CEN to 1 enables the SmaRTClock/External Oscillator Capture Mode for Timer 3. In this mode, T3SPLIT should be set to 0, as the full 16-bit timer is used. When Capture Mode is enabled, a capture event will be generated either every SmaRTClock rising edge or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the difference between two successive timer capture values, the SmaRTClock or external clock period can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture clock to achieve an accurate reading. For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and capture every SmaRTClock rising edge. If SYSCLK is 24.5 MHz and the difference between two successive captures is 350 counts, then the SmaRTClock period is as follows: 350 x (1 / 24.5 MHz) = 14.2 µs. This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or the time between consecutive SmaRTClock rising edges, which is useful for determining the SmaRTClock frequency. T 3X C L K [1:0] CKCON T 3 M H T 3 M L T 2 M H TTTSS 2 1 0CC MMMA A 10 L S Y S C LK /12 E xtern al C lock/8 X0 01 11 0 TR 3 TCLK S m a R T C lo ck T M R 3L TM R3H S Y S C LK 1 C ap ture T 3X C L K 1 TF3CEN T M R 3R LL T M R 3 R LH TMR3CN S m aR T C loc k 0 T F 3H TF3L TF3LEN TF3CEN T 3 S P LIT TR3 T 3X C L K 1 T 3X C L K 0 Interrupt E xte rna l C lock/8 1 Figure 33.9. Timer 3 Capture Mode Block Diagram Rev. 0.3 509 Si102x/3x SFR Definition 33.13. TMR3CN: Timer 3 Control Bit Name Type Reset 7 TF3H R/W 0 6 TF3L R/W 0 5 TF3LEN R/W 0 4 TF3CEN R/W 0 3 T3SPLIT R/W 0 2 TR3 R/W 0 1 0 T3XCLK[1:0] R/W 0 0 SFR Page = 0x0; SFR Address = 0x91 Bit Name 7 TF3H Function Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 interrupt service routine. This bit is not automatically cleared by hardware. 6 TF3L Timer 3 Low Byte Overflow Flag. Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will be set when the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hardware. 5 TF3LEN Timer 3 Low Byte Interrupt Enable. When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are also enabled, an interrupt will be generated when the low byte of Timer 3 overflows. 4 3 TF3CEN T3SPLIT Timer 3 SmaRTClock/External Oscillator Capture Enable. When set to 1, this bit enables Timer 3 Capture Mode. Timer 3 Split Mode Enable. When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload. 0: Timer 3 operates in 16-bit auto-reload mode. 1: Timer 3 operates as two 8-bit auto-reload timers. 2 TR3 Timer 3 Run Control. Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables TMR3H only; TMR3L is always enabled in split mode. 1:0 T3XCLK[1:0] Timer 3 External Clock Select. This bit selects the “external” and “capture trigger” clock sources for Timer 3. If Timer 3 is in 8-bit mode, this bit selects the “external” clock source for both timer bytes. Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to select between the “external” clock and the system clock for either timer. Note: External clock sources are synchronized with the system clock. 00: External Clock is SYSCLK /12. Capture trigger is SmaRTClock. 01: External Clock is External Oscillator/8. Capture trigger is SmaRTClock. 10: External Clock is SYSCLK/12. Capture trigger is External Oscillator/8. 11: External Clock is SmaRTClock. Capture trigger is External Oscillator/8. 510 Rev. 0.3 Si102x/3x SFR Definition 33.14. TMR3RLL: Timer 3 Reload Register Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3RLL[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0x92 Bit Name 7:0 Function TMR3RLL[7:0] Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. SFR Definition 33.15. TMR3RLH: Timer 3 Reload Register High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3RLH[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0x93 Bit Name Function 7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte. TMR3RLH holds the high byte of the reload value for Timer 3. Rev. 0.3 511 Si102x/3x SFR Definition 33.16. TMR3L: Timer 3 Low Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3L[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0x94 Bit Name 7:0 TMR3L[7:0] Function Timer 3 Low Byte. In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-bit mode, TMR3L contains the 8-bit low byte timer value. SFR Definition 33.17. TMR3H Timer 3 High Byte Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 TMR3H[7:0] R/W 0 0 0 0 SFR Page = 0x0; SFR Address = 0x95 Bit Name 7:0 TMR3H[7:0] Function Timer 3 High Byte. In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer 3. In 8-bit mode, TMR3H contains the 8-bit high byte timer value. 512 Rev. 0.3 Si102x/3x 34. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a programmable timebase that can select between seven sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, SmaRTClock divided by 8, Timer 0 overflows, or an external clock signal on the ECI input pin. Each capture/compare module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section “34.3. Capture/Compare Modules” on page 516). The external oscillator clock option is ideal for realtime clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the internal oscillator drives the system clock. The PCA is configured and controlled through the system controller's Special Function Registers. The PCA block diagram is shown in Figure 34.1 Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled. See Section 34.4 for details. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 SmaRTClock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 Capture/Compare Module 5 / WDT CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 34.1. PCA Block Diagram Rev. 0.3 513 Si102x/3x 34.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2–CPS0 bits in the PCA0MD register select the timebase for the counter/timer as shown in Table 34.1. When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode. Table 34.1. PCA Timebase Input Options CPS2 0 0 0 0 1 1 1 1 CPS1 0 0 1 1 0 0 1 1 CPS0 0 1 0 1 0 1 0 1 System clock divided by 4 Timer 0 overflow Timebase System clock divided by 12 High-to-low transitions on ECI (max rate = system clock divided by 4) System clock External oscillator source divided by 81 SmaRTClock oscillator source divided by 82 Reserved Notes: 1. External oscillator source divided by 8 is synchronized with the system clock. 2. SmaRTClock oscillator source divided by 8 is synchronized with the system clock. 514 Rev. 0.3 Si102x/3x IDLE PCA0MD CWW I DD DT L LEC K CCCE PPPC SSSF 210 PCA0CN CCCCCCCC FRCCCCCC FFFFFF 543210 PCA0L read To SFR Bus Snapshot Register SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 SmaRTClock/8 000 001 010 011 100 101 110 To PCA Modules 0 1 PCA0H PCA0L Overflow CF To PCA Interrupt System Figure 34.2. PCA Counter/Timer Block Diagram 34.2. PCA0 Interrupt Sources Figure 34.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of that module. These event flags are always set when the trigger condition occurs. Each of these flags can be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by setting the EA bit and the EPCA0 bit to logic 1. Rev. 0.3 515 Si102x/3x (for n = 0 to 5) PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n PCA Counter/Timer 8, 9, 10 or 11-bit Overflow PCA Counter/Timer 16bit Overflow PCA0CN CCCCCCCC FRCCCCCC FFFFFF 543210 PCA0MD C WW I DD DT L LEC K CCCE PPPC SSSF 210 PCA0PWM A CE ROC S VO EFV L C L S E L 1 C L S E L 0 Set 8, 9, 10, or 11 bit Operation 0 1 0 1 ECCF0 EPCA0 0 1 EA 0 1 PCA Module 0 (CCF0) ECCF1 0 1 Interrupt Priority Decoder PCA Module 1 (CCF1) ECCF2 0 1 PCA Module 2 (CCF2) ECCF3 0 1 PCA Module 3 (CCF3) ECCF4 0 1 PCA Module 4 (CCF4) ECCF5 0 1 PCA Module 5 (CCF5) 0 1 Figure 34.3. PCA Interrupt Block Diagram 34.3. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation. Table 34.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM registers used to select the PCA capture/compare module’s operating mode. Note that all modules set to use 8, 9, 10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a PCA0CPMn register enables the module's CCFn interrupt. Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules Operational Mode PCA0CPMn PCA0PWM 4–2 1–0 XX XX XX Bit Number 7 6 5 4 3 2 1 0 7 6 5 Capture triggered by positive edge on CEXn Capture triggered by negative edge on CEXn Capture triggered by any transition on CEXn X X 1 0 0 0 0 A 0 X B XXX X X 0 1 0 0 0 A 0 X B XXX X X 1 1 0 0 0 A 0 X B XXX 516 Rev. 0.3 Si102x/3x Table 34.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules Operational Mode Software Timer High Speed Output Frequency Output 8-Bit Pulse Width Modulator (Note 7) 9-Bit Pulse Width Modulator (Note 7) 10-Bit Pulse Width Modulator (Note 7) 11-Bit Pulse Width Modulator (Note 7) 16-Bit Pulse Width Modulator PCA0CPMn PCA0PWM XX XX XX 00 01 10 11 XX X C 0 0 1 0 0 A 0 X B XXX X C 0 0 1 1 0 A 0 X B XXX X C 0 0 0 1 1 A 0 X B XXX 0 C 0 0 E 0 1 A 0 X B XXX 0 C 0 0 E 0 1 A D X B XXX 0 C 0 0 E 0 1 A D X B XXX 0 C 0 0 E 0 1 A D X B XXX 1 C 0 0 E 0 1 A 0 X B XXX Notes: 1. X = Don’t Care (no functional difference for individual module if 1 or 0). 2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1). 3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]). 4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0). 5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated channel is accessed via addresses PCA0CPHn and PCA0CPLn. 6. E = When set, a match event will cause the CCFn flag for the associated channel to be set. 7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting. 34.3.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused the capture. Rev. 0.3 517 Si102x/3x PCA Interrupt PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n xx 000x PCA0CN CC FR CCC CCC FFF 210 (to CCFn) PCA0CPLn PCA0CPHn 0 Port I/O Crossbar CEXn 1 0 1 PCA Timebase Capture PCA0L PCA0H Figure 34.4. PCA Capture Mode Diagram Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware. 34.3.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1. 518 Rev. 0.3 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB PCA Interrupt 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n x 00 00x Enable Match 0 1 PCA0CN PCA0CPLn PCA0CPHn CC FR CCC CCC FFF 210 16-bit Comparator PCA Timebase PCA0L PCA0H Figure 34.5. PCA Software Timer Mode Diagram 34.3.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the HighSpeed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next match event. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1. Rev. 0.3 519 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 P ECCMT P E WC A A AOWC MOPP TGMC 1 MPN n n n F 6nnn n n x 00 0x PCA Interrupt PCA0CN PCA0CPLn PCA0CPHn CC FR CCC CCC FFF 210 Enable 16-bit Comparator Match 0 1 TOGn Toggle 0 CEXn 1 Crossbar Port I/O PCA Timebase PCA0L PCA0H Figure 34.6. PCA High-Speed Output Mode Diagram 34.3.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 34.1. F PCA F CEXn = ---------------------------------------2  PCA 0 CPHn Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation. Equation 34.1. Square Wave Frequency Output Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register, PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register. The MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for the channel are equal. 520 Rev. 0.3 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPMn ENB 1 P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n x 000 x Enable PCA0CPLn 8-bit Adder Adder Enable PCA0CPHn TOGn Toggle 8-bit Comparator match 0 CEXn 1 Crossbar Port I/O PCA Timebase PCA0L Figure 34.7. PCA Frequency Output Mode 34.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes Each module can be used independently to generate a pulse width modulated (PWM) output on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Output, Software Timer, Frequency Output, or 16-bit PWM mode independently. 34.3.5.1. 8-Bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the CEXn output will be reset (see Figure 34.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in Equation 34.2. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.  256 – PCA 0 CPHn  Duty Cycle = -------------------------------------------------256 Equation 34.2. 8-Bit PWM Duty Cycle Using Equation 34.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0. Rev. 0.3 521 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB PCA0CPHn ENB 1 COVF PCA0PWM A R S E L EC CO OV VF C L S E L 1 C L S E L 0 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n 0 00x0 x Enable PCA0CPLn 0x 00 8-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0L Overflow Figure 34.8. PCA 8-Bit PWM Mode Diagram 34.3.5.2. 9/10/11-bit Pulse Width Modulator Mode The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “AutoReload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data written to define the duty cycle should be right-justified in the registers. The auto-reload registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers are accessed when ARSEL is set to 0. When the least-significant N bits of the PCA0 counter match the value in the associated module’s capture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from the Nth bit, CEXn is asserted low (see Figure 34.9). Upon an overflow from the Nth bit, the COVF flag is set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register. The value of N is determined by the CLSEL bits in register PCA0PWM. The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM Mode is given in Equation 34.3, where N is the number of bits in the PWM cycle. Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.  2 N – PCA 0 CPn  Duty Cycle = ------------------------------------------N 2 Equation 34.3. 9, 10, and 11-Bit PWM Duty Cycle A 0% duty cycle may be generated by clearing the ECOMn bit to 0. 522 Rev. 0.3 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB R/W when ARSEL = 1 (Auto-Reload) PCA0CPH:Ln (right-justified) PCA0PWM A R S E L EC CO OV VF C L S E L 1 C L S E L 0 Set “N” bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits ENB 1 PCA0CPMn P ECCMT P E WC A A AOWC MOPP TGMC 1 MP N n n n F 6nnn n n 0 00x0 x Enable R/W when ARSEL = 0 x (Capture/Compare) PCA0CPH:Ln (right-justified) N-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0H:L Overflow of Nth Bit Figure 34.9. PCA 9, 10 and 11-Bit PWM Mode Diagram 34.3.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other (8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 34.4. Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.  65536 – PCA 0 CPn  Duty Cycle = ---------------------------------------------------65536 Equation 34.4. 16-Bit PWM Duty Cycle Using Equation 34.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0. Rev. 0.3 523 Si102x/3x Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB 1 PCA0CPMn PEC WCA MOP 1 MP 6nn n 1 C A P N n MT P AOW TGM nnn E C C F n x Enable PCA0CPHn PCA0CPLn 00x0 16-bit Comparator match S SET Q CEXn Crossbar Port I/O R PCA Timebase CLR Q PCA0H PCA0L Overflow Figure 34.10. PCA 16-Bit PWM Mode 34.4. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 5. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit. The WDT can be configured and enabled/disabled as needed by software. With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Module 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and optionally re-configured and re-enabled if it is used in the system). 34.4.1. Watchdog Timer Operation While the WDT is enabled:       PCA counter is forced on. Writes to PCA0L and PCA0H are not allowed. PCA clock source bits (CPS2–CPS0) are frozen. PCA Idle control bit (CIDL) is frozen. Module 5 is forced into software timer mode. Writes to the Module 5 mode register (PCA0CPM5) are disabled. While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write of any value to PCA0CPH5. Upon a PCA0CPH5 write, PCA0H plus the offset held in PCA0CPL5 is loaded into PCA0CPH5. (See Figure 34.11.) 524 Rev. 0.3 Si102x/3x PC A0M D C I D L W D T E W D L C K C P S 2 C P S 1 CE PC SF 0 PC A0C PH 5 Enable 8-bit C om parator M atch R eset PCA0CPL5 8-bit Adder Adder Enable PC A 0H P CA0L O verflow W rite to PCA 0C PH 2 Figure 34.11. PCA Module 5 with Watchdog Timer Enabled Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given (in PCA clocks) by Equation 34.5, where PCA0L is the value of the PCA0L register at the time of the update. Offset =  256  PCA 0 CPL 5  +  256 – PCA 0 L  Equation 34.5. Watchdog Timer Offset in PCA Clocks The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is enabled. 34.4.2. Watchdog Timer Usage To configure the WDT, perform the following tasks:       Disable the WDT by writing a 0 to the WDTE bit. Select the desired PCA clock source (with the CPS2–CPS0 bits). Load PCA0CPL5 with the desired WDT update offset value. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle mode). Enable the WDT by setting the WDTE bit to 1. Reset the WDT timer by writing to PCA0CPH5. The PCA clock source and idle mode select cannot be changed while the WDT is enabled. The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit. The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 34.5, this results in a WDT timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 34.3 lists some example timeout intervals for typical system clocks. Rev. 0.3 525 Si102x/3x Table 34.3. Watchdog Timer Timeout Intervals1 System Clock (Hz) 24,500,000 24,500,000 24,500,000 3,062,5002 3,062,5002 3,062,5002 32,000 32,000 32,000 PCA0CPL5 255 128 32 255 128 32 255 128 32 Timeout Interval (ms) 32.1 16.2 4.1 257 129.5 33.1 24576 12384 3168 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. 2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8. 526 Rev. 0.3 Si102x/3x 34.5. Register Descriptions for PCA0 Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 34.1. PCA0CN: PCA Control Bit Name Type Reset 7 CF R/W 0 6 CR R/W 0 5 CCF5 R/W 0 4 CCF4 R/W 0 3 CCF3 R/W 0 2 CCF2 R/W 0 1 CCF1 R/W 0 0 CCF0 R/W 0 SFR Page = All Pages; SFR Address = 0xD8; Bit-Addressable Bit Name Function 7 CF PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. 6 CR PCA Counter/Timer Run Control. This bit enables/disables the PCA Counter/Timer. 0: PCA Counter/Timer disabled. 1: PCA Counter/Timer enabled. 5:0 CCF[5:0] PCA Module n Capture/Compare Flag. These bits are set by hardware when a match or capture occurs in the associated PCA Module n. When the CCFn interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. Rev. 0.3 527 Si102x/3x SFR Definition 34.2. PCA0MD: PCA Mode Bit Name Type Reset 7 CIDL R/W 0 6 WDTE R/W 1 5 WDLCK R/W 0 4 3 CPS2 2 CPS1 R/W 0 1 CPS0 R/W 0 0 ECF R/W 0 R 0 R/W 0 SFR Page = 0x0; SFR Address = 0xD9 Bit Name 7 CIDL Function PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. 6 WDTE Watchdog Timer Enable. If this bit is set, PCA Module 5 is used as the watchdog timer. 0: Watchdog Timer disabled. 1: PCA Module 5 enabled as Watchdog Timer. 5 WDLCK Watchdog Timer Lock. This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog Timer may not be disabled until the next system reset. 0: Watchdog Timer Enable unlocked. 1: Watchdog Timer Enable locked. 4 3:1 Unused Read = 0b, Write = don't care. These bits select the timebase source for the PCA counter 000: System clock divided by 12 001: System clock divided by 4 010: Timer 0 overflow 011: High-to-low transitions on ECI (max rate = system clock divided by 4) 100: System clock 101: External clock divided by 8 (synchronized with the system clock) 110: SmaRTClock divided by 8 (synchronized with the system clock) 111: Reserved CPS[2:0] PCA Counter/Timer Pulse Select. 0 ECF PCA Counter/Timer Overflow Interrupt Enable. This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt. 0: Disable the CF interrupt. 1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set. Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the contents of the PCA0MD register, the Watchdog Timer must first be disabled. 528 Rev. 0.3 Si102x/3x SFR Definition 34.3. PCA0PWM: PCA PWM Configuration Bit Name Type Reset 7 ARSEL R/W 0 6 ECOV R/W 0 5 COVF R/W 0 4 3 2 1 0 CLSEL[1:0] R 0 R 0 R 0 0 R/W 0 SFR Page = 0x0; SFR Address = 0xDF Bit Name 7 ARSEL Function Auto-Reload Register Select. This bit selects whether to read and write the normal PCA capture/compare registers (PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function is used to define the reload value for 9, 10, and 11-bit PWM modes. In all other modes, the Auto-Reload registers have no function. 0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn. 1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn. 6 ECOV Cycle Overflow Interrupt Enable. This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt. 0: COVF will not generate PCA interrupts. 1: A PCA interrupt will be generated when COVF is set. Cycle Overflow Flag. This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA counter (PCA0). The specific bit used for this flag depends on the setting of the Cycle Length Select bits. The bit can be set by hardware or software, but must be cleared by software. 0: No overflow has occurred since the last time this bit was cleared. 1: An overflow has occurred since the last time this bit was cleared. 5 COVF 4:2 Unused Read = 000b; Write = don’t care. When 16-bit PWM mode is not selected, these bits select the length of the PWM cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which are not using 16-bit PWM mode. These bits are ignored for individual channels configured to16-bit PWM mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits. 1:0 CLSEL[1:0] Cycle Length Select. Rev. 0.3 529 Si102x/3x SFR Definition 34.4. PCA0CPMn: PCA Capture/Compare Mode Bit Name Type Reset 7 PWM16n R/W 0 6 ECOMn R/W 0 5 CAPPn R/W 0 4 CAPNn R/W 0 3 MATn R/W 0 2 TOGn R/W 0 1 PWMn R/W 0 0 ECCFn R/W 0 SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0 PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0 Bit Name Function 7 PWM16n 16-bit Pulse Width Modulation Enable. This bit enables 16-bit mode when Pulse Width Modulation mode is enabled. 0: 8 to 11-bit PWM selected. 1: 16-bit PWM selected. 6 5 4 3 ECOMn CAPPn CAPNn MATn Comparator Function Enable. This bit enables the comparator function for PCA module n when set to 1. Capture Positive Function Enable. This bit enables the positive edge capture for PCA module n when set to 1. Capture Negative Function Enable. This bit enables the negative edge capture for PCA module n when set to 1. Match Function Enable. This bit enables the match function for PCA module n when set to 1. When enabled, matches of the PCA counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to be set to logic 1. 2 TOGn Toggle Function Enable. This bit enables the toggle function for PCA module n when set to 1. When enabled, matches of the PCA counter with a module's capture/compare register cause the logic level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode. 1 PWMn Pulse Width Modulation Mode Enable. This bit enables the PWM function for PCA module n when set to 1. When enabled, a pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode. 0 ECCFn Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt. 0: Disable CCFn interrupts. 1: Enable a Capture/Compare Flag interrupt request when CCFn is set. Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog Timer must be disabled. 530 Rev. 0.3 Si102x/3x SFR Definition 34.5. PCA0L: PCA Counter/Timer Low Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 PCA0[7:0] R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Page = 0x0; SFR Address = 0xF9 Bit Name 7:0 PCA0[7:0] PCA Counter/Timer Low Byte. Function The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of the PCA0L register, the Watchdog Timer must first be disabled. SFR Definition 34.6. PCA0H: PCA Counter/Timer High Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0[15:8] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Page = 0x0; SFR Address = 0xFA Bit Name 7:0 PCA0[15:8] PCA Counter/Timer High Byte. Function The PCA0H register holds the high byte (MSB) of the 16-bit PCA Counter/Timer. Reads of this register will read the contents of a “snapshot” register, whose contents are updated only when the contents of PCA0L are read (see Section 34.1). Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of the PCA0H register, the Watchdog Timer must first be disabled. Rev. 0.3 531 Si102x/3x SFR Definition 34.7. PCA0CPLn: PCA Capture Module Low Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0CPn[7:0] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB, PCA0CPL3 = 0xED, PCA0CPL4 = 0xFD, PCA0CPL5 = 0xD2 SFR Pages: PCA0CPL0 = 0x0, PCA0CPL1 = 0x0, PCA0CPL2 = 0x0, PCA0CPL3 = 0x0, PCA0CPL4 = 0x0, PCA0CPL5 = 0x0 Name Function The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n. This register address also allows access to the low byte of the corresponding PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in register PCA0PWM controls which register is accessed. Note: A write to this register will clear the module’s ECOMn bit to a 0. Bit 7:0 PCA0CPn[7:0] PCA Capture Module Low Byte. SFR Definition 34.8. PCA0CPHn: PCA Capture Module High Byte Bit Name Type Reset R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 PCA0CPn[15:8] R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC, PCA0CPH3 = 0xEE, PCA0CPH4 = 0xFE, PCA0CPH5 = 0xD3 SFR Pages: PCA0CPH0 = 0x0, PCA0CPH1 = 0x0, PCA0CPH2 = 0x0, PCA0CPH3 = 0x0, PCA0CPH4 = 0x0, PCA0CPH5 = 0x0 Name Function The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n. This register address also allows access to the high byte of the corresponding PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in register PCA0PWM controls which register is accessed. Note: A write to this register will set the module’s ECOMn bit to a 1. Bit 7:0 PCA0CPn[15:8] PCA Capture Module High Byte. 532 Rev. 0.3 Si102x/3x 35. C2 Interface Si102x/3x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2 protocol. 35.1. C2 Interface Registers The following describes the C2 registers necessary to perform Flash programming through the C2 interface. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification. C2 Register Definition 35.1. C2ADD: C2 Address Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 C2ADD[7:0] R/W 0 0 0 0 Bit Name Function The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands. 7:0 C2ADD[7:0] C2 Address. Address 0x00 0x01 0x02 0xB4 Description Selects the Device ID register for Data Read instructions Selects the Revision ID register for Data Read instructions Selects the C2 Flash Programming Control register for Data Read/Write instructions Selects the C2 Flash Programming Data register for Data Read/Write instructions Rev. 0.3 533 Si102x/3x C2 Register Definition 35.2. DEVICEID: C2 Device ID Bit Name Type Reset 0 0 0 1 7 6 5 4 3 2 1 0 DEVICEID[7:0] R/W 0 1 0 0 C2 Address: 0x00 Bit Name 7:0 DEVICEID[7:0] Device ID. Function This read-only register returns the 8-bit device ID: 0x2A (Si102x/3x). C2 Register Definition 35.3. REVID: C2 Revision ID Bit Name Type Reset Varies Varies Varies Varies 7 6 5 4 3 2 1 0 REVID[7:0] R/W Varies Varies Varies Varies C2 Address: 0x01 Bit Name 7:0 REVID[7:0] Revision ID. Function This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A. 534 Rev. 0.3 Si102x/3x C2 Register Definition 35.4. FPCTL: C2 Flash Programming Control Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 FPCTL[7:0] R/W 0 0 0 0 C2 Address: 0x02 Bit Name 7:0 Function This register is used to enable Flash programming via the C2 interface. To enable C2 Flash programming, the following codes must be written in order: 0x02, 0x01. Note that once C2 Flash programming is enabled, a system reset must be issued to resume normal operation. FPCTL[7:0] Flash Programming Control Register. C2 Register Definition 35.5. FPDAT: C2 Flash Programming Data Bit Name Type Reset 0 0 0 0 7 6 5 4 3 2 1 0 FPDAT[7:0] R/W 0 0 0 0 C2 Address: 0xB4 Bit Name 7:0 Function This register is used to pass Flash commands, addresses, and data during C2 Flash accesses. Valid commands are listed below. FPDAT[7:0] C2 Flash Programming Data Register. Code 0x06 0x07 0x08 0x03 Command Flash Block Read Flash Block Write Flash Page Erase Device Erase Rev. 0.3 535 Si102x/3x 35.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely “borrow” the C2CK (RST) and C2D pins. In most applications, external resistors are required to isolate C2 interface traffic from the user application. A typical isolation configuration is shown in Figure 35.1. C8051Fxxx RST (a) Input (b) Output (c) C2CK C2D C2 Interface Master Figure 35.1. Typical C2 Pin Sharing The configuration in Figure 35.1 assumes the following: 1. The user input (b) cannot change state while the target device is halted. 2. The RST pin on the target device is used as an input only. Additional resistors may be necessary depending on the specific application. 536 Rev. 0.3 Si102x/3x NOTES: Rev. 0.3 537 Si102x/3x CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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