SI3201-X-FS

Si3233 P R O SLIC ® P R O G R A M M A B L E C MOS SLIC W I T H R I N G I N G / B A T T E R Y VO L TA G E G E N E R A T I O N Features Software Programmable SLIC with codec interface Software programmable internal balanced ringing up to 90 VPK (5 REN up to 4 kft, 3 REN up to 8 kft) Integrated battery supply with dynamic voltage output On-chip dc-dc converter continuously minimizes power in all operating modes Entire solution can be powered from a single 3.3 V or 5 V supply 3.3 V to 35 V dc input range Dynamic 0 V to –94.5 V output Software programmable signal generation and audio processing: Phase-continuous FSK (caller ID) generation Dual audio tone generators Smooth and abrupt polarity reversal Extensive test and diagnostic features Realtime dc linefeed measurement GR-909 line test capabilities Ordering Information See page 95. Software programmable linefeed parameters: Ringing frequency, amplitude, cadence, and waveshape 2-wire ac impedance constant current feed (20 to 41 mA) Loop closure and ring trip thresholds and filtering SPI control interface Extensive programmable interrupts 100% software configurable global solution Lead-Free and RoHS-compliant Pin Assignments QFN Package TEST2 PCLK INT CS SCLK SDI SDO Applications Interface to Broadcom devices BCM11xx residential gateway BCM3341 VOIP processor BCM33xx cable modem Voice over IP Terminal adapters Fixed cellular terminal Description The Si3233 ProSLIC® is a low-voltage CMOS device that provides a multi-functional subscriber line interface ideal for customer premise equipment (CPE) applications. The ProSLIC integrates subscriber line interface circuit (SLIC) and battery generation functionality into a single CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3233M only) or 5 V supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry. Si3233 features include software-configurable 5 REN internal ringing up to 90 VPK, DTMF generation, and a comprehensive set of telephony signaling capabilities for operation with only one hardware solution. The ProSLIC is packaged in a 38-pin QFN and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC. NC FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC 1 38 37 36 35 34 33 32 31 30 2 3 4 5 6 7 8 9 10 11 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP Patents pending U.S. Patent #6,567,521 U.S. Patent #6,812,744 Other patents pending Functional Block Diagram INT RESET SPI Control Interface CS SCLK SDO SDI Si3233 Ringing Generator Loop Closure Detect Ring Trip Detect Line Diagnostics SLIC Linefeed Control Linefeed Monitor Linefeed Interface Tip Ring Tone Generators FSK Caller ID Impedance Synth PCLK PLL FSYNC DC–DC Converter Controller Battery Preliminary Rev. 0.5 4/06 Copyright © 2006 by Silicon Laboratories STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA Si3233 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i3233 2 Preliminary Rev. 0.5 S i3233 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. Si3230 to Si3233 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8. PLL Free-run Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.4. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 5. Pin Descriptions: Si3233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Preliminary Rev. 0.5 3 S i3233 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage Operating Temperature Range2 Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical Continuous Power Dissipation2 Si3201 DC Supply Voltage Battery Supply Voltage Input Voltage: TIP, RING, SRINGE, STIPE pins Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins Operating Temperature Range2 Storage Temperature Range SOIC-16 Thermal Resistance, Typical3 Continuous Power Dissipation 2 Symbol Si3233 VDDD, VDDA1, VDDA2 IIN VIND TA TSTG θJA θJA PD VDD VBAT VINHV VIN TA TSTG θJA PD Value –0.5 to 6.0 ±10 –0.3 to (VDDD + 0.3) –40 to 100 –40 to 150 70 35 0.7 –0.5 to 6.0 –104 (VBAT – 0.3) to (VDD + 0.3) –0.3 to (VDD + 0.3) –40 to 100 –40 to 150 55 1.0 Unit V mA V ºC ºC ºC/W ºC/W W V V V V ºC ºC ºC/W W Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Operation above 125 oC junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. 4 Preliminary Rev. 0.5 S i3233 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3233 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage Symbol TA TA VDDD,VDDA1 ,VDDA2 VDD VBAT VBATH = VBAT Test Condition F-grade G-grade Min* 0 –40 3.13 3.13 –96 Typ 25 25 3.3/5.0 3.3/5.0 — Max* 70 85 5.25 5.25 –10 Unit oC o C V V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used. Table 3. AC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade) Parameter Overload Level Audio Tone Generator Signal-to-Distortion Ratio1 Intermodulation Distortion 2-Wire Return Loss Idle Channel Noise 2 Test Condition TX/RX Performance THD = 1.5% 0 dBm0, Active off-hook, and OHT, any Zac 200 Hz to 3.4 kHz Noise Performance C-Message Weighted Psophometric Weighted 3 kHz flat Min 2.5 45 — 30 — — — 40 40 40 56 43 53 53 40 Typ — — — 35 — — — — — — 60 60 60 60 — Max — — –45 — 15 –75 18 — — — — — — — — Unit VPK dB dB dB dBrnC dBmP dBrn dB dB dB dB dB dB dB dB PSRR from VDDA PSRR from VDDD PSRR from VBAT Longitudinal to Metallic Balance RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz Longitudinal Performance 200 Hz to 3.4 kHz, βQ1,Q2 ≥ 150, 1% mismatch βQ1,Q2 = 60 to 2403 βQ1,Q2 = 300 to 800 Using Si3201 3 Metallic to Longitudinal Balance 200 Hz to 3.4 kHz Notes: 1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 2. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 3. Assumes normal distribution of betas. Preliminary Rev. 0.5 5 S i3233 Table 3. AC Characteristics (Continued) (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade) Parameter Longitudinal Impedance Test Condition 200 Hz to 3.4 kHz at TIP or RING Register selectable ETBO/ETBA Min Typ Max Unit 00 01 10 Longitudinal Current per Pin Active off-hook 200 Hz to 3.4 kHz Register selectable ETBO/ETBA — — — 33 17 17 — — — Ω Ω Ω 00 01 10 — — — 4 8 8 — — — mA mA mA Notes: 1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 2. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 3. Assumes normal distribution of betas. 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 1 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) Figure 1. Overload Compression Performance 6 Preliminary Rev. 0.5 S i3233 Table 4. Linefeed Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade) Parameter Loop Resistance Range DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC Open Circuit Voltage— Ground Start DC Output Resistance— Ground Start DC Output Resistance— Ground Start Loop Closure/Ring Ground Detect Threshold Accuracy Ring Trip Threshold Accuracy Ring Trip Response Time Ring Amplitude Ring DC Offset Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy Symbol RLOOP Test Condition See note.* ILIM = 29 mA, ETBA = 4 mA Active Mode; VOC = 48 V, VTIP – VRING Min 0 –10 –4 — –4 — 150 –20 –10 — 44 0 –.05 1.35 Typ — — — 160 — 160 — — — — — — — — — — — — Max 160 10 4 — 4 — — 20 10 — — — .05 1.45 1 50 600 25 Unit Ω % V Ω V Ω kΩ % % RDO VOCTO RROTO RTOTO ILOOP < ILIM IRING VRING; audio signal paths powered on. TIP tri-stated, RING active; used for ground start. Ringing waveform applied to TIP and RING. VRING > VTIP. VRING > VTIP; audio signal paths powered on. RING tri-stated, TIP active. Note: The Linefeed register (LF) is located in direct Register 64. Table 21. Measured Realtime Linefeed Interface Characteristics Parameter Loop Voltage Sense (VTIP – VRING) Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 (VBAT) Battery Voltage Sense 2 (VBAT) Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense Measurement Range –94.5 to +94.5 V –78.75 to +78.5 mA 0 to –95.88 V 0 to –95.88 V 0 to –95.88 V 0 to –95.88 V 0 to 81.35 mA 0 to 81.35 mA 0 to 9.59 mA 0 to 9.59 mA 0 to 80.58 mA 0 to 80.58 mA Resolution 1.5 V 1.25 mA 0.376 V 0.376 V 0.376 V 0.376 V 0.319 mA 0.319 mA 37.6 µA 37.6 µA 0.316 mA 0.316 mA Register Bits LVSP, LVS[6:0] LCSP, LCS[5:0] VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] Location* Direct Register 78 Direct Register 79 Direct Register 80 Direct Register 81 Direct Register 82 Direct Register 83 Direct Register 84 Direct Register 85 Direct Register 86 Direct Register 87 Direct Register 88 Direct Register 89 *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. 20 Preliminary Rev. 0.5 S i3233 2.2.5. Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each linefeed transistor. Realtime output power of any one of the six linefeed transistors can be read by setting the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power Output Monitor (direct Register 77). The realtime power measurements are low-pass filtered and compared to a maximum power threshold. Maximum power thresholds and filter time constants are software programmable and should be set for each transistor pair based on the characteristics of the transistors used. Table 22 describes the registers associated with this function. If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of the type of fault condition present on the line. The value of each thermal low-pass filter pole is set according to the equation: 4096 Thermal LPF Pole [12:0] = -----------------800 × τ where τ is the thermal time constant of the transistor package, 4096 is the full range of the 12-bit register, and 800 is the sample rate in hertz. Generally τ = 3 seconds for SOT223 packages and τ = 0.16 seconds for SOT23, but check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows: P MAX 1.28 PT56[7:0] = ------------------------------ = ----------------- = 42 = 2Ah 0.0304 Resolution Thus, indirect Register 21 2Ah x 27 = 1500h. should be set to Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6. Table 22. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Description/ Range 0 to 5 points to Q1 to Q6, respectively 0 to 7.8 W for Q1, Q2, Q5, Q6 0 to 0.9 W for Q3, Q4 0 to 7.8 W 0 to 0.9 W 0 to 7.8 W Resolution N/A Register Bits PWRMP[2:0] Location* Direct Register 76 Line Power Monitor Output 30.4 mW 3.62 mW PWROM[7:0] Direct Register 77 Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & Q2 Thermal LPF Pole, Q3 & Q4 Thermal LPF Pole, Q5 & Q6 Power Alarm Interrupt Pending 30.4 mW 3.62 mW 30.4 mW PPT12[7:0] PPT34[7:0] PPT56[7:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] QnAP[n+1], where n = 1 to 6 Indirect Register 19 Indirect Register 20 Indirect Register 21 Indirect Register 24 Indirect Register 25 Indirect Register 26 Direct Register 19 see equation above see equation above see equation above Bits 2 to 7 correspond to Q1 to Q6, respectively N/A Preliminary Rev. 0.5 21 S i3233 Table 22. Associated Power Monitoring and Power Fault Registers (Continued) Power Alarm Interrupt Enable Bits 2 to 7 correspond to Q1 to Q6, respectively 0 = manual mode 1 = enter open state upon power alarm N/A QnAE[n+1], where n = 1 to 6 AOPN Direct Register 22 Power Alarm Automatic/Manual Detect N/A Direct Register 67 *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). LCS LVS Input Signal Processor ISP_OUT Digital LPF + Debounce Filter – NCLR LFS LCVE HYSTEN Loop Closure Threshold LCDI LCIE LCR LCIP Interrupt Logic LCRT LCRTL Figure 9. Loop Closure Detection 2.2.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or onhook active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement loop closure detection are shown in Figure 9. The primary input to the system is the Loop Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input Signal Processor when the ProSLIC is in the on-hook transmission or on-hook active linefeed state, as indicated by the Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect register 15). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit will be set to indicate that a valid loop closure has occurred. A loop closure interrupt is generated if enabled by the LCIE bit (direct Register 22). Table 23 lists the registers that must be written or monitored to correctly detect a loop closure condition. 2.2.7. Loop Closure Threshold Hysteresis Programmable hysteresis to the loop closure threshold can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect Register 15) and LCRTL (indirect Register 66), which set the upper and lower bounds, respectively. 22 Preliminary Rev. 0.5 S i3233 2.2.8. Voltage-Based Loop Closure Detection An optional voltage-based loop closure detection mode is enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current threshold. If hysteresis is also enabled, LCRT represents the upper voltage boundary, and LCRTL represents the lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default current-based loop closure detection is recommended. RING or TIP must not be connected to ground during the calibration. 2.3. Battery Voltage Generation and Switching The Si3233 integrates a dc-dc converter controller that dynamically regulates a single output voltage. This eliminates the need to supply large external battery voltages. Instead, it converts a single positive input voltage into the real-time battery voltage needed for any given state according to programmed linefeed parameters. 2.3.1. DC-DC Converter General Description The dc-dc converter dynamically generates the large negative voltages required to operate the linefeed interface. The Si3233 acts as the controller for a buckParameter Register Location Loop Closure LCIP Direct Reg. 19 boost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. In Interrupt Pending addition to eliminating external power supplies, this Loop Closure LCIE Direct Reg. 22 allows the Si3233 to dynamically control the battery Interrupt Enable voltage to the minimum required for any given mode of Loop Closure Threshold LCRT[5:0] Indirect Reg. 15 operation. Loop Closure LCRTL[5:0] Indirect Reg. 66 Extensive design guidance can be obtained from Threshold—Lower Application Note 45 (AN45) and from an interactive dcLoop Closure Filter NCLR[12:0] Indirect Reg. 22 dc converter design spreadsheet. Both of these Coefficient documents are available on the Silicon Laboratories Loop Closure Detect LCR Direct Reg. 68 website (www.silabs.com). Status (monitor only) 2.3.2. BJT/Inductor Circuit Using Si3233 LCDI[6:0] Direct Reg. 69 Loop Closure Detect The BJT/Inductor circuit, as defined in Figure 4, offers a Debounce Interval flexible, low-cost solution. Depending on selected L1 Hysteresis Enable HYSTEN Direct Reg. 108 inductance value and the switching frequency, the input Voltage-Based Loop LCVE Direct Reg. 108 voltage (V ) can range from 5 V to 30 V. By nature of a DC Closure dc-dc converter’s operation, peak and average input 2.2.9. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3233 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (tsettle) the calibration can be initiated. Additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. During calibration, VBAT, VTIP, and VRING voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. Calibration should be performed in the on-hook state. currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply. In this circuit, a PNP power BJT (Q7) switches the current flow through low ESR inductor L1. The Si3233 uses the DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3233 (not Si3233M) must be used. 2.3.3. MOSFET/Transformer Circuit Option Using Si3233M The MOSFET/transformer circuit option, as defined in Figure 5, offers higher power efficiencies across a larger input voltage range. Depending on the transformer’s primary inductor value and the switching frequency, the input voltage (VDC) can range from 3.3 V to 35 V. Therefore, it is possible to power the entire ProSLIC Table 23. Register Set for Loop Closure Detection Preliminary Rev. 0.5 23 S i3233 solution from a single 3.3 V or 5 V power supply. By nature of a dc-dc converter’s operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply (number of REN supported). In this circuit, an n-channel power MOSFET (M1) switches the current flow through a power transformer T1. T1 is specified in Application Note 45 (AN45), and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3233M version of the Si3233 must be used for the application circuit depicted in Figure 5 because the DCFF pin is used to drive M1 directly and therefore must be the same polarity as DCDRV. DCDRV is not used in this circuit option; connecting DCFF and DCDRV together is not recommended. 2.3.4. DC-DC Converter Architecture The control logic for a pulse width modulated (PWM) dcdc converter is incorporated in the Si3233. Output pins, DCDRV and DCFF, are used to switch a bipolar transistor or MOSFET. The polarity of DCFF is opposite to that of DCDRV. The dc-dc converter circuit is powered on when the DCOF bit in the Power Down Register (direct Register 14, bit 4) is cleared to 0. The switching regulator circuit within the Si3233 is a high performance, pulse-width modulation controller. The control pins are driven by the PWM controller logic in the Si3233. The regulated output voltage (VBAT) is sensed by the SVBAT pin and is used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. The dc monitor pins SDCH and SDCL monitor input current and voltage to the dc-dc converter external circuitry. If an overload condition is detected, the PWM controller will turn off the switching transistor for the remainder of a PWM period to prevent damage to external components. It is important that the proper value of R18 be selected to ensure safe operation. Guidance is given in Application Note 45 (AN45). The PWM controller operates at a frequency set by the dc-dc Converter PWM register (direct Register 92). During a PWM period the outputs of the control pins DCDRV and DCFF are asserted for a time given by the read-only PWM Pulse Width register (direct Register 94). The dc-dc converter must be off for some time in each cycle to allow the inductor or transformer to transfer its stored energy to the output capacitor, C9. This minimum off time can be set through the dc-dc Converter Switching Delay register, (direct Register 93). The number of 16.384 MHz clock cycles that the controller is off is equal to DCTOF (bits 0 through 4) plus 4. If the dc Monitor pins detect an overload condition, the dc-dc converter interrupts its conversion cycles regardless of the register settings to prevent component damage. These inputs should be calibrated by writing the DCCAL bit (bit 7) of the dc-dc Converter Switching Delay register, direct Register 93, after the dc-dc converter has been turned on. The most negative terminal (VRING or VTIP) is offset from the battery voltage (VBAT) by a programmable overlead voltage (VOV) to allow sufficient headroom for audio signals. The dc-dc converter can be made to adjust more quickly to voltage changes by setting DCSU = 1 (Direct Register 108, bit 5). Audio band noise can optionally be reduced using an audio band filter by setting DCFIL = 1 (Direct Register 108, bit 1). 2.3.5. DC-DC Converter During Forward Active The Si3233 dynamically adjusts VBAT to match the requirements of the loop and line state. The behavior of the tracking dc-dc converter in the active state is shown in Figure 10. In the active state, the TIP-to-RING open circuit voltage is kept at VOC in the constant voltage region while the regulator output voltage, VBAT = VCM + VOC + VOV. When the loop current attempts to exceed ILIM, the dc line driver circuit enters constant current mode allowing the TIP to RING voltage to track RLOOP. As the TIP terminal is kept at a constant voltage, it is the RING terminal voltage that tracks RLOOP and, as a result, the |VBAT| voltage will also track RLOOP. In this state, |VBAT| = ILIM x RLOOP + VCM +VOV. As RLOOP decreases below the VOC/ILIM mark, the regulator output voltage can continue to track RLOOP (TRACK = 1), or the RLOOP tracking mechanism is stopped when |VBAT| = |VBATL| (TRACK = 0). The former case is the more common application and provides the maximum power dissipation savings. In principle, the regulator output voltage can go as low as |VBAT| = VCM+ VOV, offering significant power savings. When TRACK = 0, |VBAT| will not decrease below VBATL. The RING terminal voltage, however, continues to decrease with decreasing RLOOP. The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment which, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line. TRACK = 0 mode 24 Preliminary Rev. 0.5 S i3233 is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and would cause the terminal equipment to incorrectly sense another off-hook terminal. VOC Constant I Region ILIM VCM Constant V Region RLOOP VTIP TR AC VBATL K= 1 |VTIP - VRING| VOV VOC TRACK=0 VOV VRING VBAT V Figure 10. VTIP, VRING, and VBAT in the Forward Active State Table 24. Associated Relevant DC-DC Converter Registers Parameter DC-DC Converter Power-off Control DC-DC Converter Calibration Enable/Status DC-DC Converter PWM Period DC-DC Converter Min. Off Time High Battery Voltage—VBATH Low Battery Voltage—VBATL VOV Range n/a n/a 0 to 15.564 us (0 to 1.892 us) + 4 clock cycles 0 to –94.5 V 0 to –94.5 V 0 to –9 V or 0 to –13.5 V Resolution n/a n/a 61.035 ns 61.035 ns 1.5 V 1.5 V 1.5 V Register Bit DCOF DCCAL DCN[7:0] DCTOF[4:0] VBATH[5:0] VBATL[5:0] VMIND[3:0] VOV Location Direct Register 14 Direct Register 93 Direct Register 92 Direct Register 93 Direct Register 74 Direct Register 75 Indirect Register 64 Direct Register 66 Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). Preliminary Rev. 0.5 25 S i3233 2.3.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and –94.5 V in 1.5 V steps. To avoid clipping the ringing signal, VBATH must be set larger than the ringing amplitude. At the end of each ringing burst the dc-dc converter switches back to active state regulation as described above. spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. 2.4.1. Tone Generator Architecture A simplified diagram of the tone generator architecture is shown in Figure 11. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. These registers are described in more detail in Table 25. 2.4. Tone Generation Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single or dual tone frequency and amplitude combinations and 8 kHz Clock OnE OZn Zero Cross Zero Cross Logic OSSn Enable 16 kHz Clock 16-Bit Modulo Counter OAT Expire OIT Expire Load Logic Register Load Two-Pole Resonance Oscillator Signal Routing to RX Path OATn OATnE OITn OITnE INT Logic INT Logic OnIP REL* OSCn OnSO OnIE OnAP OSCnY OSCnX OnAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 11. Simplified Tone Generator Diagram 26 Preliminary Rev. 0.5 S i3233 2.4.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonant oscillator circuit with a programmable frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 16 kHz. The equations are as follows: coeffn = cos(2π fn/16 kHz), where fn is the frequency to be generated; OSCn = coeffn x (215); Desired V rms 15 1 1 – coeff OSCnX = -- × ----------------------- × ( 2 – 1 ) × -----------------------------------1.11 V rms 4 1 + coeff 2.4.3. Tone Generator Cadence Programming Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 µs steps. The active period time interval is set using OAT1 (direct registers 36 and 37) for tone generator 1 and OAT2 (direct registers 40 and 41) for tone generator 2. To enable automatic cadence for tone generator 1, define the OAT1 and OIT1 registers and then set the O1TAE bit (direct Register 32, bit 4) and O1TIE bit (direct Register 32, bit 3). This enables each of the timers to control the state of the Oscillator Enable bit, O1E (direct Register 32, bit 2). The 16-bit counter will begin counting until the active timer expires, at which time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 12 is an example of an output cadence using the zero crossing feature. One-shot oscillation can be achieved by enabling O1E and O1TAE. Direct control over the cadence can be achieved by controlling the O1E bit (direct Register 32, bit 2) directly if O1TAE and O1TIE are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers. Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator due to resource sharing within the hardware. where desired Vrms is the amplitude to be generated; OSCnY = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, in order to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated: 2 π 852 coeff 1 = cos ⎛ ---------------- ⎞ = 0.94455 ⎝ 16000 ⎠ OSC1 = 0.94455 ( 2 ) = 30951 = 78E6h 15 1 0.05545OSC1X = -- × ---------------------- × ( 2 – 1 ) × 0.5 = 692 = 2B3h 4 1094455 15 OSC1Y = 0 2 π 1336 coeff2 = cos ⎛ ------------------- ⎞ = 0.86550 ⎝ 16000 ⎠ OSC2 = 0.86550 (215) = 28361 = 3EC8h 1 15 OSC2X = -- × 0.13450 × ( 2 – 1 ) × 0.5 = 1098 = 44Bh -------------------4 1.86550 OSC2Y = 0 The computed values above would be written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. Continuous phase frequency-shift keying (FSK) waveforms may be created using tone generator 1 (not available on tone generator 2) by setting the REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1). Preliminary Rev. 0.5 27 S i3233 Table 25. Associated Tone Generator Registers Tone Generator 1 Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Description / Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers Tone Generator 2 Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control Description/Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 seconds 0 to 8 seconds Status and control registers Register OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] OAT2[15:0] OIT2[15:0] OSS2, OZ2, O2TAE, O2TIE, O2E, O2SO[1:0] Location Indirect Register 3 Indirect Register 4 Indirect Register 5 Direct Registers 40 & 41 Direct Register 42 & 43 Direct Register 33 Register Bits OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OAT1[15:0] OIT1[15:0] OSS1, REL, OZ1, O1TAE, O1TIE, O1E, O1SO[1:0] Location Indirect Register 0 Indirect Register 1 Indirect Register 2 Direct Registers 36 & 37 Direct Register 38 & 39 Direct Register 32 O1E 0,1 . .. ... , OAT1 0,1 . .. ... , O IT1 0,1 . .. ... , OAT1 0,1 . .. ... ... OSS1 Tone G en. 1 Signal O utput Figure 12. Tone Generator Timing Diagram 28 Preliminary Rev. 0.5 S i3233 2.4.4. Enhanced FSK Waveform Generation Enhanced FSK generation can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 69–74. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. By writing to FSKDAT (direct Register 52), this mode applies a 24 kHz sample rate to tone generator 1 to give additional resolution to timers and frequency generation. “AN32: Si321x Frequency Shift Keying (FSK) Modulation” gives detailed instructions on how to implement FSK in this mode. Additionally, sample source code is available from Silicon Laboratories upon request. 2.4.5. Tone Generator Interrupts Both the active and inactive timers can generate their own interrupt to signal “on/off” transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the O1AE and O1IE bits (direct Register 21, bits 0 and 1, respectively). Timer interrupts for tone generator two are O2AE and O2IE (direct Register 21, bits 2 and 3, respectively). A pending interrupt for each of the timers is determined by reading the O1AP, O1IP, O2AP, and O2IP bits in the Interrupt Status 1 register (direct Register 18, bits 0 through 3, respectively). 2.5. Ringing Generation The ProSLIC provides fully programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. All parameters associated with ringing are software programmable: ringing frequency, waveform, amplitude, dc offset, and ringing cadence. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals of up to 88 V peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 Ω + 40 µF) ringer load across loop lengths of 2000 feet (160 Ω) or more. 2.5.1. Ringing Architecture The ringing generator architecture is nearly identical to that of the tone generator. The sinusoid ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. However, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate instead of 16 kHz. The ringing generator has two timers that function the same as for the tone generator timers. They allow on/off cadence settings up to 8 seconds on/ 8 seconds off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. Table 26 summarizes the list of registers used for ringing generation. Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware. Table 26. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset Ringing frequency Range/ Description Sine/Trapezoid Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled 0 to 8 seconds 0 to 8 seconds Ringing State = 100b 0 to –94.5 V 0 to 94.5 V 15 to 100 Hz Preliminary Rev. 0.5 Register Bits TSWS RVO RTAE RTIE ROE RAT[15:0] RIT[15:0] LF[2:0] VBATH[5:0] ROFF[15:0] RCO[15:0] Location Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Registers 48 and 49 Direct Registers 50 and 51 Direct Register 64 Direct Register 74 Indirect Register 6 Indirect Register 7 29 S i3233 Table 26. Registers for Ringing Generation (Continued) Ringing amplitude Ringing initial phase 0 to 94.5 V Sets initial phase for sinewave and period for trapezoid 0 to 22.5 V RNGX[15:0] RNGY[15:0] Indirect Register 8 Indirect Register 9 Common Mode Bias Adjust During Ringing VCMR[3:0] Indirect Register 27 Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). When the ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC will go into the ringing state and start the first ring. At the expiration of RAT, the ProSLIC will turn off the ringing waveform and will go to the on-hook transmission state. At the expiration of RIT, ringing will again be initiated. This process will continue as long as the two timers are enabled and the Linefeed Control register is set to the ringing state. 2.5.2. Sinusoidal Ringing To configure the ProSLIC for sinusoidal ringing, the frequency and amplitude are initialized by writing to the following indirect registers: RCO, RNGX, and RNGY. The equations for RCO, RNGX, RNGY are as follows: RCO = coeff × ( 2 ) 15 waveform by writing TSWS = 0 (direct Register 34, bit 0). 2.5.3. Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ringing. Figure 13 illustrates a trapezoidal ringing waveform with offset VROFF. VTIP-RING VROFF T=1/freq tRISE where 2πf coeff = cos ⎛ ---------------------- ⎞ ⎝ 1000 Hz⎠ time and f = desired ringing frequency in hertz. 1 15 Desired V PK ( 0 to 94.5 V ) 1 – coeff RNGX = -- × ----------------------- × 2 × ----------------------------------------------------------------------4 96 V 1 + coeff RNGY = 0 Figure 13. Trapezoidal Ringing Waveform To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations: 1 R NGY = -- × Period × 8000 2 Desired V PK 15 RNGX = ----------------------------------- × ( 2 ) 96 V 2 × RNGX RCO = -------------------------------t RISE × 8000 In selecting a ringing amplitude, the peak TIP-to-RING ringing voltage must be greater than the selected onhook line voltage setting (VOC, direct Register 72). For example, to generate a 70 VPK 20 Hz ringing signal, the equations are as follows: 2 π × 20coeff = cos ⎛ ---------------------- ⎞ = 0.99211 ⎝ 1000 Hz⎠ RCO = 0.99211 × ( 2 ) = 32509 = 7EFDh 15 70 1 RNGX = -- × 0.00789 × 2 × ----- = 376 = 0177h -------------------96 4 1.99211 15 RNGY = 0 In addition, the user must select the sinusoidal ringing RCO is a value which is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. 30 Preliminary Rev. 0.5 S i3233 3 1t RISE = -- T ⎛ 1 – ----------⎞ 2⎠ 4⎝ CF V AC , PK N REN I LOAD , PK = ------------------ + I OS = V AC , PK × ----------------- + I OS R LOAD 6.9 k Ω where T = ringing period, and CF = desired crest factor. For example, to generate a 71 VPK, 20 Hz ringing signal, the equations are as follows: 1 1RNGY ( 20 Hz ) = -- × --------------- × 8000 = 200 = C8h 2 20 Hz 71 15 RNGX ( 71 V PK ) = ----- × 2 = 24235 = 5EABh 96 where: NREN is the ringing REN load (max value = 5), IOS is the offset current flowing in the line driver circuit (max value = 2 mA), and VAC,PK = amplitude of the ac ringing waveform. It is good practice to provide a buffer of a few more milliamperes for ILOAD,PK to account for possible line leakages, etc. The total ILOAD,PK current should be smaller than 80 mA. β+1 V OVR = I LOAD , PK × ------------ × ( 80.6 Ω + 1 V ) β For a crest factor of 1.3 and a period of 0.05 seconds (20 Hz), the rise time requirement is 0.0153 seconds. RCO ( 20 Hz , 1.3 crest factor ) 2 × 24235 = ------------------------------------- = 396 = 018Ch 0.0153 × 8000 where β is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by the following: VBATH = V AC , PK + V ROFF + V OVR In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. 2.5.4. Ringing DC voltage Offset A dc offset can be added to the ac ringing waveform by defining the offset voltage in ROFF (indirect Register 6). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows: V ROFF 15 ROFF = ----------------- × 2 96 The ProSLIC is designed to create a fully balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following: VBATH – VCMR VCM _ RING = --------------------------------------------2 2.5.5. Linefeed Considerations During Ringing Care must be taken to keep the generated ringing signal within the ringing voltage rails (GNDA and VBAT) to maintains proper biasing of the external bipolar transistors. If the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors will result. To prevent this invalid operation, set the VBATH value (direct Register 74) to a value higher than the maximum peak ringing voltage. The discussion below outlines the considerations and equations that govern the selection of the VBATH setting for a particular desired peak ringing voltage. First, the required amount of ringing overhead voltage, VOVR, is calculated based on the maximum value of current through the load, ILOAD,PK, the minimum current gain of Q5 and Q6, and a reasonable voltage required to keep Q5 and Q6 out of saturation. For ringing signals up to VPK = 87 V, VOVR = 7.5 V is a safe value. However, to determine VOVR for a specific case, use the equations below. VCMR is an indirect register which provides the headroom by the ringing waveform with respect to the VBATH rail. The value is set as a 4-bit setting in indirect Register 27 with an LSB voltage of 1.5 V/LSB. Register 27 should be set with the calculated VOVR to provide voltage headroom during ringing. Silicon revisions C and higher support the option to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from ringing to a dc linefeed state. This mode is enabled by setting ILIMEN = 1 (direct Register 108, bit 7). 2.5.6. Ring Trip Detection A ring trip event signals that the terminal equipment has gone off-hook during the ringing state. The ProSLIC performs ring trip detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement ring trip detection is shown in Figure 14. The primary input to the system is the Loop Current Sense (LCS) value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Preliminary Rev. 0.5 31 S i3233 Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter is compared to a programmable threshold, RPTP (indirect Register 16). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval, RTDI[6:0] (direct Register 70). If the debounce interval Input Signal Processor has been satisfied, the RTP bit of direct Register 68 will be set to indicate that a valid ring trip has occurred. A ring trip interrupt is generated if enabled by the RTIE bit (direct Register 22). Table 27 lists the registers that must be written or monitored to correctly detect a ring trip condition. The recommended values for RPTP, NRTP, and RTDI vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 28. LCS ISP_OUT Digital LPF + DBIRAW Debounce Filter RTP Interrupt Logic RTIP – NRTP LFS Ring Trip Threshold RTDI RTIE RPTP Figure 14. Ring Trip Detector Table 27. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Register RTIP RTIE RTDI[6:0] RPTP[5:0] NRTP[12:0] RTP Location Direct Register 19 Direct Register 22 Direct Register 70 Indirect Register 16 Indirect Register 23 Direct Register 68 Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). 32 Preliminary Rev. 0.5 S i3233 Table 28. Recommended Ring Trip Values for Ringing Ringing Frequency Hz 16.667 20 30 40 50 60 decimal 64 100 112 128 213 256 NRTP hex 0200 0320 0380 0400 06A8 0800 decimal 34 mA 34 mA 34 mA 34 mA 34 mA 34 mA RPTP hex 3600 3600 3600 3600 3600 3600 decimal 15.4 ms 12.3 ms 8.96 ms 7.5 ms 5 ms 4.8 ms RTDI hex 0F 0B 09 07 05 05 Preliminary Rev. 0.5 33 S i3233 2.6. Two-Wire Impedance Matching The ProSLIC provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the TISS[2:0] bits of the Two-Wire Impedance Synthesis Control register (direct Register 10). If direct Register 10 is not explicitly set, the default setting of 600 Ω will be loaded into the TISS register. The ProSLIC also provides a means to compensate for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range. The default setting of CLC[2:0] assumes no line capacitance. To support 600 Ω + 1 µF and 900 Ω + 2.16 µF applications, an external resistor, RZREF, must be inserted into the application circuit as shown in Figure 15. to TIP C3 R8 STIPAC RZREF Si3233 SRINGAC C4 For 600 + 1 µF, RZREF = 12 kΩ and C3, C4 = 100 nF. For 900 + 2.16 µF, RZREF = 18 kΩ and C3, C4 = 220 nF. to RING R9 PCLK frequency and it can be approximately predicted by the following equation: 64 T SETTLE = ---------------F PCLK 2.8. PLL Free-run Operation The Si3233 is capable of operating in the absence of a valid PCLK signal. This feature can be enabled at any time after initialization by setting the PFR bit (register 14, bit 3). When enabled, the Si3233 internally gates off the buffered PCLK signal and applies a reference voltage input to the PLL. This allows the DC/DC converter to operate correctly and enables a nominal battery voltage to remain on the line. The PCLK pin must be held either high or low during PLL Free-run operation. To exit the PLL Free-run mode, valid PCLK and FSYNC signals must be reestablished and the Si3233 RESET pin must be asserted. The direct and indirect registers must then be reloaded with the desired initialization settings. Capturing and storing the calibration results (direct registers 98–107) before entering the PLL free-run mode is recommended since the results can then be manually reloaded after exiting the PLL free-run mode without executing a calibration routine. Note that audio signal generation will not be accurate during this mode of operation and therefore it is not recommended. 2.9. Interrupt Logic The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Power alarm Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain 1 bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three interrupt enable registers also contain 1 bit for each interrupt function. In the case of the interrupt enable registers, the bits are active high. Refer to the appropriate functional description section for operational details of the interrupt functions. When a resource reaches an interrupt condition, it will Figure 15. RZREF External Resistor Placement 2.7. Clock Generation The ProSLIC will generate the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 768 kHz, 1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined via a counter clocked by PCLK. The three-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a reset of the ProSLIC. The PLL_MULT is used to control the internal PLL which multiplies PCLK as needed to generate 16.384 MHz rate needed to run the internal filters and other circuitry. The PLL clock synthesizer settles very quickly following power up. However, the settling time depends on the 34 Preliminary Rev. 0.5 S i3233 signal an interrupt to the interrupt control block. The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the INT pin will remain asserted. impedence on either the falling edge of SCLK following the LSB, or the rising of CS as specified by the SPIM bit (direct Register 0, bit 6). SDI is a “don’t care” during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress. There are a number of variations of usage on this fourwire interface: Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-‘bit transfer (command/address or data). SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. Daisy chain mode. This mode allows communication with banks of up to eight ProSLIC devices using one chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in Figure 18, a single device may select from the bank of devices by setting the appropriate chip select bit to 1. Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. 2.10. Serial Peripheral Interface The control interface to the ProSLIC is a 4-wire interface modeled after commonly available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte transfers. Figures 16 and 17 illustrate read and write operation in the SPI bus. The first byte of the pair is the command/address byte. The MSB of this byte indicates register read when 1 and a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides resynchronization of the SPI state machine in the event of a framing error, it is recommended (but not required) that CS be taken high between byte transfers as shown in Figures 16 and 17. During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first. The SDO will be high Preliminary Rev. 0.5 35 S i3233 Don't Care SCLK CS SDI 0 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 SDO High Impedance Figure 16. Serial Write 8-Bit Mode SCLK Don't Care CS SDI 1 a6 a5 a4 a3 a2 a1 a0 Don't Care SDO High Impedance d7 d6 d5 d4 d3 d2 d1 d0 Figure 17. Serial Read 8-Bit Mode 36 Preliminary Rev. 0.5 S i3233 SDO C PU CS SDI CS SDO SDI SDI0 SDITHRU CS SDO SDI SDI1 SDITHRU CS SDO SDI SDI2 SDITHRU CS SDO SDI SDI3 SDITHRU Chip Select Byte SCLK Address Byte Data Byte SDI0 C7 C6 C5 C4 C3 C2 C1 C0 R/W A 6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI1 – C7 C6 C5 C4 C3 C2 C1 R/W A 6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI2 – – C7 C6 C5 C4 C3 C2 R/W A 6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI3 – – – C7 C6 C5 C4 C3 R/W A 6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. Figure 18. SPI Daisy Chain Mode Preliminary Rev. 0.5 37 S i3233 3. Control Registers Indirect registers are accessed through direct registers 28 through 31. Instructions on how to access them is described in “4. Indirect Registers” beginning on page 85. Note: Any register not listed here is reserved and must not be written. Table 29. Direct Register Summary Register Name 0 9 10 11 14 15 18 19 20 21 22 23 28 29 30 31 32 33 34 36 37 SPI Mode Select Audio Gain Control Two-Wire Impedance Synthesis Control Reserved Powerdown Power Down Control 1 Power Down Control 2 Interrupts Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3 Indirect Register Access Indirect Data Access— Low Byte Indirect Data Access— High Byte Indirect Address Indirect Address Status Oscillators Oscillator 1 Control Oscillator 2 Control Ringing Oscillator Control Oscillator 1 Active Timer—Low Byte Oscillator 1 Active Timer—High Byte OSS1 OSS2 RSS REL OZ1 OZ2 RDAC O1TAE O2TAE RTAE O1TIE O2TIE RTIE O1E O2E ROE O1SO[1:0] O2SO[1:0] RVO TSWS IDA[7:0] IDA[15:8] IAA[7:0] IAS PMIE Q6AE PMAE Q5AE RGIE Q4AE RGAE Q3AE O2IE Q2AE PMIP Q6AP PMAP Q5AP RGIP Q4AP RGAP Q3AP O2IP Q2AP O2AP Q1AP CMCP O2AE Q1AE CMCE O1IP LCIP INDP O1IE LCIE INDE O1AP RTIP DTMFP O1AE RTIE DTMFE DCOF PFR DACM DACON BIASOF SLICOF GMM GMON CLC[1:0] TISE Bit 7 SPIDC Bit 6 SPIM Bit 5 Setup PNI[1:0] Audio ARX[1:0] TISS[2:0] RNI[3:0] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OATI[7:0] OAT1[15:8] 38 Preliminary Rev. 0.5 S i3233 Table 29. Direct Register Summary (Continued) Register Name 38 39 40 41 42 43 48 49 50 51 52 63 Oscillator 1 Inactive Timer—Low Byte Oscillator 1 Inactive Timer—High Byte Oscillator 2 Active Timer—Low Byte Oscillator 2 Active Timer—High Byte Oscillator 2 Inactive Timer—Low Byte Oscillator 2 Inactive Timer—High Byte Ringing Oscillator Active Timer—Low Byte Ringing Oscillator Active Timer—High Byte Ringing Oscillator Inactive Timer—Low Byte Ringing Oscillator Inactive Timer—High Byte FSK Data SLIC Loop Closure Debounce Interval for Automatic Ringing Linefeed Control External Bipolar Transistor Control Battery Feed Control Automatic/Manual Control Loop Closure/Ring Trip Detect Status Loop Closure Debounce Interval Ring Trip Detect Debounce Interval Loop Current Limit On-Hook Line Voltage Common Mode Voltage High Battery Voltage VSGN VOC[5:0] VCM[5:0] VBATH[5:0] MNCM MNDIF SQH LFS[2:0] CBY ETBE VOV SPDS ETBO[1:0] FVBAT AORD DBIRAW LCDI[6:0] RTDI[6:0] ILIM[2:0] AOLD RTP LCD[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] FSKDAT 64 65 66 67 68 69 70 71 72 73 74 LF[2:0] ETBA[1:0] TRACK AOPN LCR Preliminary Rev. 0.5 39 S i3233 Table 29. Direct Register Summary (Continued) Register Name 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 92 93 94 95 96 97 98 99 100 Low Battery Voltage Power Monitor Pointer Line Power Output Monitor Loop Voltage Sense Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 Battery Voltage Sense 2 Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense DC-DC Converter PWM Period DC-DC Converter Switching Delay PWM Pulse Width Reserved Calibration Control/ Status Register 1 Calibration Control/ Status Register 2 RING Gain Mismatch Calibration Result TIP Gain Mismatch Calibration Result Differential Loop Current Gain Calibration Result CAL CALSP CALR CALM1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PWRMP[2:0] Bit 0 VBATL[5:0] PWROM[7:0] LVSP LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] DCN[7:0] DCCAL DCPOL DCPW[7:0] CALT CALM2 LVS[5:0] LCS[5:0] DCTOF[4:0] CALD CALDAC CALC CALADC CALIL CALCM CALGMR[R4:0] CALGMT[4:0] CALGD[4:0] 40 Preliminary Rev. 0.5 S i3233 Table 29. Direct Register Summary (Continued) Register Name 101 Common Mode Loop Current Gain Calibration Result Current Limit Calibration Result Monitor ADC Offset Calibration Result Analog DAC/ADC Offset DAC Offset Calibration Result Common Mode Balance Calibration Result DC Peak Voltage Calibration Result Enhancement Enable ILIMEN FSKEN DCSU CALMG1[3:0] DACP DACOF[7:0] CMBAL[5:0] CMDCPK[3:0] LCVE DCFIL HYSTEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CALGC[4:0] Bit 1 Bit 0 102 103 104 105 106 107 108 CALGIL[3:0] CALMG2[3:0] DACN ADCP ADCN Preliminary Rev. 0.5 41 S i3233 Register 0. SPI Mode Select Bit Name Type D7 SPIDC R/W D6 SPIM R/W D5 PNI[1:0] R D4 D3 D2 RNI[3:0] R D1 D0 Reset settings = 00xx_xxxx Bit 7 Name SPIDC SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Part Number Identification. 00 = Si3233 01 = Reserved 10 = Reserved 11 = Si3233M Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. Function 6 SPIM 5:4 PNI[1:0] 3:0 RNI[3:0] 42 Preliminary Rev. 0.5 S i3233 Register 9. Audio Gain Control Bit Name Type Reset settings = 0000_0000 Bit 7:2 1:0 Name Reserved ARX[1:0] Read returns zero. Analog Receive Path Gain. 00 = 0 dB 01 = –3.5 dB 10 = 3.5 dB 11 = Mute Note: ARX affects internally generated audio signals only. Audio received on IGMN/IGMP pins is not impacted. D7 D6 D5 D4 D3 D2 D1 D0 ARX[1:0] R/W Function Preliminary Rev. 0.5 43 S i3233 Register 10. Two-Wire Impedance Synthesis Control Bit Name Type Reset settings = 0000_1000 Bit 7:6 5:4 Name Reserved CLC[1:0] Read returns zero. Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. Two-Wire Impedance Synthesis Selection. 000 = 600 Ω 001 = 900 Ω 010 = Japan (600 Ω + 1 µF); requires RZREF = 12 kΩ and C3, C4 = 100 nF 011 = 900 Ω + 2.16 µF; requires RZREF = 18 kΩ and C3, C4 = 220 nF 100 = CTR21 270 Ω + (750 Ω || 150 nF) 101 = Australia/New Zealand 220 Ω + (820 Ω || 120 nF) 110 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF) 111 = China 200 Ω + (680 Ω || 100 nF) Function D7 D6 D5 D4 D3 TISE R/W D2 D1 TISS[2:0] R/W D0 CLC[1:0] R/W 3 TISE 2:0 TISS[2:0] 44 Preliminary Rev. 0.5 S i3233 Register 14. Power Down Control 1 Si3233 Bit Name Type Reset settings = 0001_0000 Bit 7:5 4 Name Reserved DCOF Read returns zero. DC-DC Converter Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc-dc circuitry off. PLL Free-Run Control. 0 = Normal operation. 1 = PLL free-run mode enabled. Read returns zero. DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc bias circuitry off. SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off. Function D7 D6 D5 D4 DCOF R/W D3 MOF R/W D2 D1 BIASOF R/W D0 SLICOF R/W 3 PFR 2 1 Reserved BIASOF 0 SLICOF Preliminary Rev. 0.5 45 S i3233 Register 15. Power Down Control 2 Bit Name Type Reset settings = 0000_0000 Bit 7:4 3 Name Reserved DACM Read returns zero. Digital to Analog Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; DACON controls on/off state. Digital to Analog Converter On/Off Power Control. When DACM = 1: 0 = Digital to analog converter powered off. 1 = Digital to analog converter powered on. DACON has no effect when DACM = 0. Transconductance Amplifier Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; GMON controls on/off state. Transconductance Amplifier On/Off Power Control. When GMM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. GMON has no effect when GMM = 0. Function D7 D6 D5 D4 D3 DACM R/W D2 DACON R/W D1 GMM R/W D0 GMON R/W 2 DACON 1 GMM 0 GMON 46 Preliminary Rev. 0.5 S i3233 Register 18. Interrupt Status 1 Bit Name Type Reset settings = 0000_0000 Bit 7:6 5 Name Reserved RGIP Read returns zero. Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Function D7 D6 D5 RGIP R/W D4 RGAP R/W D3 O2IP R/W D2 O2AP R/W D1 O1IP R/W D0 O1AP R/W 4 RGAP 3 O2IP 2 O2AP 1 O1IP 0 O1AP Preliminary Rev. 0.5 47 S i3233 Register 19. Interrupt Status 2 Bit Name Type D7 Q6AP R/W D6 Q5AP R/W D5 Q4AP R/W D4 Q3AP R/W D3 Q2AP R/W D2 Q1AP R/W D1 LCIP R/W D0 RTIP R/W Reset settings = 0000_0000 Bit 7 Name Q6AP Function Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Transition Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 6 Q5AP 5 Q4AP 4 Q3AP 3 Q2AP 2 Q1AP 1 LCIP 0 RTIP 48 Preliminary Rev. 0.5 S i3233 Register 20. Interrupt Status 3 Bit Name Type Reset settings = 0000_0000 Bit 7:2 1 Name Reserved INDP Read returns zero. Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Read returns zero. Function D7 D6 D5 D4 D3 D2 D1 INDP R/W D0 0 Reserved Preliminary Rev. 0.5 49 S i3233 Register 21. Interrupt Enable 1 Bit Name Type Reset settings = 0000_0000 Bit 7:6 5 Name Reserved RGIE Read returns zero. Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Function D7 D6 D5 RGIE R/W D4 RGAE R/W D3 O2IE R/W D2 O2AE R/W D1 O1IE R/W D0 O1AE R/W 4 RGAE 3 O2IE 2 O2AE 1 O1IE 0 O1AE 50 Preliminary Rev. 0.5 S i3233 Register 22. Interrupt Enable 2 Bit Name Type D7 Q6AE R/W D6 Q5AE R/W D5 Q4AE R/W D4 Q3AE R/W D3 Q2AE R/W D2 Q1AE R/W D1 LCIE R/W D0 RTIE R/W Reset settings = 0000_0000 Bit 7 Name Q6AE Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Transition Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Function 6 Q5AE 5 Q4AE 4 Q3AE 3 Q2AE 2 Q1AE 1 LCIE 0 RTIE Preliminary Rev. 0.5 51 S i3233 Register 23. Interrupt Enable 3 Bit Name Type Reset settings = 0000_0000 Bit 7:2 1 Name Reserved INDE Read returns zero. Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Read returns zero. Function D7 D6 D5 D4 D3 D2 D1 INDE R/W D0 0 Reserved 52 Preliminary Rev. 0.5 S i3233 Register 28. Indirect Data Access—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[7:0] Function Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IDA[7:0] R/W D3 D2 D1 D0 Register 29. Indirect Data Access—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[15:8] Function Indirect Data Access—High Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 D3 D2 D1 D0 IDA[15:8] R/W Preliminary Rev. 0.5 53 S i3233 Register 30. Indirect Address Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IAA[7:0] Function Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IAA[7:0] R/W D3 D2 D1 D0 Register 31. Indirect Address Status Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved IAS Read returns zero. Indirect Access Status. 0 = No indirect memory access pending. 1 = Indirect memory access pending. Function D7 D6 D5 D4 D3 D2 D1 D0 IAS R 54 Preliminary Rev. 0.5 S i3233 Register 32. Oscillator 1 Control Bit Name Type D7 OSS1 R D6 REL R/W D5 OZ1 R/W D4 O1TAE R/W D3 O1TIE R/W D2 O1E R/W D1 D0 O1SO[1:0] R/W Reset settings = 0000_0000 Bit 7 Name OSS1 Oscillator 1 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. Oscillator 1 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing after active timer expires. Oscillator 1 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 1 Signal Output Routing. 00 = Unassigned path (output not connected). 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function 6 REL 5 OZ1 4 O1TAE 3 O1TIE 2 O1E 1:0 O1SO[1:0] Preliminary Rev. 0.5 55 S i3233 Register 33. Oscillator 2 Control Bit Name Type D7 OSS2 R D6 D5 OZ2 R/W D4 O2TAE R/W D3 O2TIE R/W D2 O2E R/W D1 D0 O2SO[1:0] R/W Reset settings = 0000_0000 Bit 7 Name OSS2 Oscillator 2 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Oscillator 2 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing. Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 2 Signal Output Routing. 00 = Unassigned path (output not connected) 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function 6 5 Reserved OZ2 4 O2TAE 3 O2TIE 2 O2E 1:0 O2SO[1:0] 56 Preliminary Rev. 0.5 S i3233 Register 34. Ringing Oscillator Control Bit Name Type D7 RSS R D6 D5 RDAC R D4 RTAE R/W D3 RTIE R/W D2 ROE R D1 RVO R/W D0 TSWS R/W Reset settings = 0000_0000 Bit 7 Name RSS Function Ringing Signal Status. 0 = Ringing oscillator output signal inactive. 1 = Ringing oscillator output signal active. Read returns zero. Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING. 1 = Ringing signal present at TIP and RING. Ringing Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Oscillator Enable. 0 = Ringing oscillator disabled. 1 = Ringing oscillator enabled. Ringing Voltage Offset. 0 = No dc offset added to ringing signal. 1 = DC offset added to ringing signal. Trapezoid/Sinusoid Waveshape Select. 0 = Sinusoid 1 = Trapezoid 6 5 Reserved RDAC 4 RTAE 3 RTIE 2 ROE 1 RVO 0 TSWS Preliminary Rev. 0.5 57 S i3233 Register 36. Oscillator 1 Active Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Function D7 D6 D5 D4 D3 D2 D1 D0 OAT1[7:0] R/W Register 37. Oscillator 1 Active Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[15:8] Oscillator 1 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 OAT1[15:8] R/W Register 38. Oscillator 1 Inactive Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[7:0] Oscillator 1 Inactive Timer. LSB = 125 µs Function D7 D6 D5 D4 D3 D2 D1 D0 OIT1[7:0] R/W 58 Preliminary Rev. 0.5 S i3233 Register 39. Oscillator 1 Inactive Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[15:8] Oscillator 1 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 OIT1[15:8] R/W Register 40. Oscillator 2 Active Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Function D7 D6 D5 D4 D3 D2 D1 D0 OAT2[7:0] R/W Register 41. Oscillator 2 Active Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[15:8] Oscillator 2 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 OAT2[15:8] R/W Preliminary Rev. 0.5 59 S i3233 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Function D7 D6 D5 D4 D3 D2 D1 D0 OIT2[7:0] R/W Register 43. Oscillator 2 Inactive Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[15:8] Oscillator 2 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 OIT2[15:8] R/W Register 48. Ringing Oscillator Active Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[7:0] Ringing Active Timer. LSB = 125 µs Function D7 D6 D5 D4 RAT[7:0] R/W D3 D2 D1 D0 60 Preliminary Rev. 0.5 S i3233 Register 49. Ringing Oscillator Active Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[15:8] Ringing Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 RAT[15:8] R/W Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[7:0] Ringing Inactive Timer. LSB = 125 µs Function D7 D6 D5 D4 RIT[7:0] R/W D3 D2 D1 D0 Register 51. Ringing Oscillator Inactive Timer—High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[15:8] Ringing Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0 RIT[15:8] R/W Preliminary Rev. 0.5 61 S i3233 Register 52. FSK Data Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved FSKDAT Read returns zero. FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. Function D7 D6 D5 D4 D3 D2 D1 D0 FSKDAT R/W Register 63. Loop Closure Debounce Interval Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 LCD[7:0] R/W Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions) Bit 7:0 Name LCD[7:0] Function Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps. 62 Preliminary Rev. 0.5 S i3233 Register 64. Linefeed Control Bit Name Type Reset settings = 0000_0000 Bit 7 6:4 Name Reserved LFS[2:0] Read returns zero. Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst). 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Read returns zero. Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function D7 D6 D5 LFS[2:0] R D4 D3 D2 D1 LF[2:0] R/W D0 3 2:0 Reserved LF[2:0] Preliminary Rev. 0.5 63 S i3233 Register 65. External Bipolar Transistor Control Bit Name Type D7 D6 SQH R/W D5 CBY R/W D4 ETBE R/W D3 D2 D1 D0 ETBO[1:0] R/W ETBA[1:0] R/W Reset settings = 0110_0001 Bit 7 6 Name Reserved SQH Read returns zero. Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled. External Transistor Bias Levels—On-Hook Transmission State. DC bias current which flows through external BJTs in the on-hook transmission state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved External Transistor Bias Levels—Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved Function 5 CBY 4 ETBE 3:2 ETBO[1:0] 1:0 ETBA[1:0] 64 Preliminary Rev. 0.5 S i3233 Register 66. Battery Feed Control Bit Name Type Reset settings = 0000_0011 Bit 7:5 4 Name Reserved VOV Read returns zero. Overhead Voltage Range Increase. This bit selects the programmable range for VOV, which is defined in indirect Register 41. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V VBAT Manual Setting. 0 = Normal operation 1 = VBAT tracks VBATH register. 2:1 0 Reserved TRACK Read returns zero. DC-DC Converter Tracking Mode. 0 = |VBAT| will not decrease below VBATL. 1 = VBAT tracks VRING. Function D7 D6 D5 D4 VOV R/W D3 FVBAT R/W D2 D1 D0 TRACK R/W 3 FVBAT Preliminary Rev. 0.5 65 S i3233 Register 67. Automatic/Manual Control Bit Name Type D7 D6 MNCM R/W D5 MNDIF R/W D4 SPDS R/W D3 D2 AORD R/W D1 AOLD R/W D0 AOPN R/W Reset settings = 0001_1111 Bit 7 6 Name Reserved MNCM Read returns zero. Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. Differential Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control (forces differential voltage to follow VOC value). Speed-Up Mode Enable. 0 = Speed-up disabled. 1 = Automatic speed-up. Read returns zero. Automatic/Manual Ring Trip Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon ring trip detect. Automatic/Manual Loop Closure Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon loop closure detect. Power Alarm Automatic/Manual Detect. 0 = Manual mode. 1 = Enter open state automatically upon power alarm. Function 5 MNDIF 4 SPDS 3 2 Reserved AORD 1 AOLD 0 AOPN 66 Preliminary Rev. 0.5 S i3233 Register 68. Loop Closure/Ring Trip Detect Status Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved DBIRAW Read returns zero. Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded. Ring Trip Detect Indicator (Filtered Output). 0 = Ring trip detect has not occurred. 1 = Ring trip detect occurred. Loop Closure Detect Indicator (Filtered Output). 0 = Loop closure detect has not occurred. 1 = Loop closure detect has occurred. Function D7 D6 D5 D4 D3 D2 DBIRAW R D1 RTP R D0 LCR R 1 RTP 0 LCR Register 69. Loop Closure Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved LCDI[6:0] Read returns zero. Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 LCDI[6:0] R/W D2 D1 D0 Preliminary Rev. 0.5 67 S i3233 Register 70. Ring Trip Detect Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved RTDI[6:0] Read returns zero. Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 RTDI[6:0] R/W D2 D1 D0 Register 71. Loop Current Limit Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved ILIM[2:0] Read returns zero. Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps. Function D7 D6 D5 D4 D3 D2 D1 ILIM[2:0] R/W D0 68 Preliminary Rev. 0.5 S i3233 Register 72. On-Hook Line Voltage Bit Name Type D7 D6 VSGN R/W D5 D4 D3 D2 D1 D0 VOC[5:0] R/W Reset settings = 0010_0000 Bit 7 6 Name Reserved VSGN Read returns zero. On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP–VRING). 0 = VTIP–VRINGis positive 1 = VTIP–VRING is negative On-Hook Line Voltage. The value written to this register sets the on-hook line voltage (VTIP–VRING). Value may be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V. Function 5:0 VOC[5:0] Register 73. Common Mode Voltage Bit Name Type Reset settings = 0000_0010 Bit 7:6 5:0 Name Reserved VCM[5:0] Read returns zero. Common Mode Voltage. The value written to this register sets VTIP for forward active and forward on-hook transmission states and VRING for reverse active and reverse on-hook transmission states. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = –3 V. Function D7 D6 D5 D4 D3 D2 D1 D0 VCM[5:0] R/W Preliminary Rev. 0.5 69 S i3233 Register 74. High Battery Voltage Bit Name Type Reset settings = 0011_0010 Bit 7:6 5:0 Name Reserved VBATH[5:0] Read returns zero. High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = –75 V. Function D7 D6 D5 D4 D3 D2 D1 D0 VBATH[5:0] R/W Register 75. Low Battery Voltage Bit Name Type Reset settings = 0001_0000 Bit 7:6 5:0 Name Reserved VBATL[5:0] Read returns zero. Low Battery Voltage. The value written to this register sets low battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = –24 V. Function D7 D6 D5 D4 D3 D2 D1 D0 VBATL[5:0] R/W 70 Preliminary Rev. 0.5 S i3233 Register 76. Power Monitor Pointer Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved PWRMP[2:0] Read returns zero. Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined Function D7 D6 D5 D4 D3 D2 D1 PWRMP[2:0] R/W D0 Register 77. Line Power Output Monitor Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PWROM[7:0] Function Line Power Output Monitor. This register reports the realtime power output of the transistor selected using PWRMP. The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4. D7 D6 D5 D4 D3 D2 D1 D0 PWROM[7:0] R Preliminary Rev. 0.5 71 S i3233 Register 78. Loop Voltage Sense Bit Name Type D7 D6 LVSP R D5 D4 D3 LVS[5:0] R D2 D1 D0 Reset settings = 0000_0000 Bit 7 6 Name Reserved LVSP Read returns zero. Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP – VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude. This register reports the magnitude of the differential loop voltage (VTIP–VRING). The range is 0 V to 94.5 V in 1.5 V steps. Function 5:0 LVS[5:0] Register 79. Loop Current Sense Bit Name Type D7 D6 LCSP R D5 D4 D3 LCS[5:0] R D2 D1 D0 Reset settings = 0000_0000 Bit 7 6 Name Reserved LCSP Read returns zero. Loop Current Sense Polarity. This register reports the polarity of the loop current. 0 = Positive loop current (forward direction). 1 = Negative loop current (reverse direction). Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in 1.25 mA steps. Function 5:0 LCS[5:0] 72 Preliminary Rev. 0.5 S i3233 Register 80. TIP Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VTIP[7:0] Function TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0 VTIP[7:0] R Register 81. RING Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VRING[7:0] Function RING Voltage Sense. This register reports the realtime voltage at RING with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0 VRING[7:0] R Register 82. Battery Voltage Sense 1 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS1[7:0] Function Battery Voltage Sense 1. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0 VBATS1[7:0] R Preliminary Rev. 0.5 73 S i3233 Register 83. Battery Voltage Sense 2 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS2[7:0] Function Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps. D7 D6 D5 D4 D3 D2 D1 D0 VBATS2[7:0] R Register 84. Transistor 1 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ1[7:0] Function Transistor 1 Current Sense. This register reports the realtime current through Q1. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ1[7:0] R D3 D2 D1 D0 Register 85. Transistor 2 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ2[7:0] Function Transistor 2 Current Sense. This register reports the realtime current through Q2. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ2[7:0] R D3 D2 D1 D0 74 Preliminary Rev. 0.5 S i3233 Register 86. Transistor 3 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ3[7:0] Function Transistor 3 Current Sense. This register reports the realtime current through Q3. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 µA steps. D7 D6 D5 D4 IQ3[7:0] R D3 D2 D1 D0 Register 87. Transistor 4 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ4[7:0] Function Transistor 4 Current Sense. This register reports the realtime current through Q4. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 µA steps. D7 D6 D5 D4 IQ4[7:0] R D3 D2 D1 D0 Register 88. Transistor 5 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ5[7:0] Function Transistor 5 Current Sense. This register reports the realtime current through Q5. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. D7 D6 D5 D4 IQ5[7:0] R D3 D2 D1 D0 Preliminary Rev. 0.5 75 S i3233 Register 89. Transistor 6 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ6[7:0] Function Transistor 6 Current Sense. This register reports the realtime current through Q6. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. D7 D6 D5 D4 IQ6[7:0] R D3 D2 D1 D0 Register 92. DC-DC Converter PWM Period Bit Name Type D7 DCN[7] R/W D6 1 R D5 D4 D3 D2 D1 D0 DCN[5:0] R/W Reset settings = 1111_1111 Bit 7:0 Name DCN[7:0] Function DC-DC Converter Period. This bit sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40) to 15.564 µs (0xFF) in 61.035 ns steps. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 µs–7.751 µs, used for MOSFET transistor switching. 11.719 µs–15.564 µs, used for BJT transistor switching. 76 Preliminary Rev. 0.5 S i3233 Register 93. DC-DC Converter Switching Delay Bit Name Type D7 DCCAL R/W D6 D5 DCPOL R D4 D3 D2 DCTOF[4:0] R/W D1 D0 Reset settings = 0001_0100 (Si3233) Reset settings = 0011_0100 (Si3233M) Bit 7 Name DCCAL Function DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine. 0 = Normal operation. 1 = Calibration being performed. Read returns zero. DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3233 are offered to support the two relationships. 0 = DCFF pin polarity is opposite of DCDRV pin (Si3233). 1 = DCFF pin polarity is same as DCDRV pin (Si3233M). DC-DC Converter Minimum Off Time. This register sets the minimum off time for the pulse width modulated dc-dc converter control. TOFF = (DCTOF + 4) x 61.035 ns. 6 5 Reserved DCPOL 4:0 DCTOF[4:0] Register 94. DC-DC Converter PWM Pulse Width Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DCPW[7:0] Function DC-DC Converter Pulse Width. Pulse width of DCDRV is given by PW = (DCPW – DCTOF – 4) x 61.035 ns. D7 D6 D5 D4 D3 D2 D1 D0 DCPW[7:0] R Preliminary Rev. 0.5 77 S i3233 Register 96. Calibration Control/Status Register 1 Bit Name Type D7 D6 CAL R/W D5 CALSP R/W D4 CALR R/W D3 CALT R/W D2 CALD R/W D1 CALC R/W D0 CALIL R/W Reset settings = 0001_1111 Bit 7 6 Name Reserved CAL Read returns zero. Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 = Normal operation or calibration complete. 1 = Calibration in progress. Calibration Speedup. Setting this bit shortens the time allotted for VBAT settling at the beginning of the calibration cycle. 0 = 300 ms 1 = 30 ms RING Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ILIM Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function 5 CALSP 4 CALR 3 CALT 2 CALD 1 CALC 0 CALIL 78 Preliminary Rev. 0.5 S i3233 Register 97. Calibration Control/Status Register 2 Bit Name Type Reset settings = 0001_1111 Bit 7:5 4 Name Reserved CALM1 Read returns zero. Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Calibration. Setting this bit begins calibration of the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Calibration. Setting this bit begins calibration of the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function D7 D6 D5 D4 CALM1 R/W D3 CALM2 R/W D2 CALDAC R/W D1 CALADC R/W D0 CALCM R/W 3 CALM2 2 CALDAC 1 CALADC 0 CALCM Preliminary Rev. 0.5 79 S i3233 Register 98. RING Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMR[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for RING Current. Function D7 D6 D5 D4 D3 D2 CALGMR[4:0] R/W D1 D0 Register 99. TIP Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMT[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for TIP Current. Function D7 D6 D5 D4 D3 D2 CALGMT[4:0] R/W D1 D0 Register 100. Differential Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGD[4:0] Read returns zero. Differential DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGD[4:0] R/W D1 D0 80 Preliminary Rev. 0.5 S i3233 Register 101. Common Mode Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGC[4:0] Read returns zero. Common Mode DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGC[4:0] R/W D1 D0 Register 102. Current Limit Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:5 3:0 Name Reserved CALGIL[3:0] Read returns zero. Current Limit Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0 CALGIL[3:0] R/W Register 103. Monitor ADC Offset Calibration Result Bit Name Type Reset settings = 1000_1000 Bit 7:4 3:0 Name CALMG1[3:0] CALMG2[3:0] Function Monitor ADC Offset Calibration Result 1. Monitor ADC Offset Calibration Result 2. D7 D6 D5 D4 D3 D2 D1 D0 CALMG1[3:0] R/W CALMG2[3:0] R/W Preliminary Rev. 0.5 81 S i3233 Register 104. Analog DAC/ADC Offset Bit Name Type Reset settings = 0000_0000 Bit 7:4 3 2 1 0 Name Reserved DACP DACN ADCP ADCN Read returns zero. Positive Analog DAC Offset. Negative Analog DAC Offset. Positive Analog ADC Offset. Negative Analog ADC Offset. Function D7 D6 D5 D4 D3 DACP R/W D2 DACN R/W D1 ADCP R/W D0 ADCN R/W Register 105. DAC Offset Calibration Result Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DACOF[7:0] DAC Offset Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0 DACOF[7:0] R/W Register 106. Common Mode Calibration Result Bit Name Type Reset settings = 0010_0000 Bit 7:6 5:0 Name Reserved CMBAL[5:0] Read returns zero. Common Mode Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0 CMBAL[5:0] R/W 82 Preliminary Rev. 0.5 S i3233 Register 107. DC Peak Current Monitor Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:4 3:0 Name Reserved CMDCPK[3:0] Read returns zero. DC Peak Current Monitor Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0 CMDCPK[3:0] R/W Register 108. Enhancement Enable Bit Name Type D7 ILIMEN R/W D6 FSKEN R/W D5 DCSU R/W D4 D3 D2 LCVE R/W D1 DCFIL R/W D0 HYSTEN R/W Reset settings = 0000_0000 Bit 7 Name ILIMEN Function Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used. 1 = The maximum differential loop current limit is temporarily increased to 41 mA. FSK Generation Enhancement. When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are used for FSK generation (indirect registers 99–104). Audio tones are generated using this new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolution of 41.67 µs. This provides greater resolution during FSK caller ID signal generation. 0 = Tone generator always clocked at 16 kHz; OSC1, OSC1X., and OSC1Y are always used. 1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only when REL = 1; otherwise clocked at 16 kHz. DC-DC Converter Control Speedup. When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes. 0 = Normal control algorithm used. 1 = Multi-threshold error control algorithm used. Read returns zero. 6 FSKEN 5 DCSU 4:3 Reserved Preliminary Rev. 0.5 83 S i3233 Bit 2 Name LCVE Function Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop current. 0 = Loop closure determined by loop current. 1 = Loop closure determined by TIP-to-RING voltage. DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled. 1 DCFIL 0 HYSTEN 84 Preliminary Rev. 0.5 S i3233 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. Table 30. Si3230 to Si3233 Indirect Register Cross Reference Si3230 Indirect Register 13 14 15 16 17 18 19 20 21 22 26 Si3233 Indirect Register 0 1 2 3 4 5 6 7 8 9 13 Indirect Register Name OSC1 OSC1X OSC1Y OSC2 OSC2X OSC2Y ROFF RCO RNGX RNGY DACG Si3230 Indirect Register 27 28 29 30 31 32 33 34 35 36 37 Si3233 Indirect Register 14 15 16 17 18 19 20 21 22 23 24 Indirect Register Name ADCG LCRT RPTP CML CMH PPT12 PPT34 PPT56 NCLR NRTP NQ12 Si3230 Indirect Register 38 39 40 41 43 99 100 101 102 103 104 Si3233 Indirect Register 25 26 27 64 66 69 70 71 72 73 74 Indirect Register Name NQ34 NQ56 VCMR VMIND LCRTL FSK0X FSK0 FSK1X FSK1 FSK01 FSK10 All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. 4.1. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes. Table 31. Oscillator Indirect Registers Summary Addr 0 1 2 3 4 5 6 ROFF[5:0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] Preliminary Rev. 0.5 85 S i3233 Table 31. Oscillator Indirect Registers Summary (Continued) Addr 7 8 9 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RCO[15:0] RNGX[15:0] RNGY[15:0] Table 32. Oscillator Indirect Registers Description Addr 0 1 2 3 4 5 6 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. Oscillator 2 Frequency Coefficient. Sets tone generator 2 frequency. Oscillator 2 Amplitude Register. Sets tone generator 2 signal amplitude. Oscillator 2 Initial Phase Register. Sets initial phase of tone generator 2 signal. Ringing Oscillator DC Offset. Sets dc offset component (VTIP–VRING) to ringing waveform. The range is 0 to 94.5 V in 1.5 V increments. Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. Description Reference Page 27 27 27 27 27 27 29 7 8 9 29 29 29 4.2. Digital Programmable Gain/Attenuation See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes. 86 Preliminary Rev. 0.5 S i3233 Table 33. Digital Programmable Gain/Attenuation Indirect Registers Summary Addr 13 14 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DACG[11:0] ADCG[11:0] Table 34. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. 13 Description Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to –∞ dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –∞ dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. 14 Preliminary Rev. 0.5 87 S i3233 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes. Table 35. SLIC Control Indirect Registers Summary Addr 15 16 17 18 19 20 21 22 23 24 25 26 27 64 66 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LCRT[5:0] RPTP[5:0] CML[5:0] CMH[5:0] PPT12[7:0] PPT34[7:0] PPT56[7:0] NCLR[12:0] NRTP[12:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] VCMR[3:0] VMIND[3:0] LCRTL[5:0] Table 36. SLIC Control Indirect Registers Description Addr 15 Description Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hysteresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps. See "2.2.6. Loop Closure Detection" on page 22. Ring Trip Threshold. Ring trip detection threshold during ringing. See "2.5.6. Ring Trip Detection" on page 31. Common Mode Minimum Threshold for Speed-Up. This register defines the negative common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0–23.625 V in 0.375 V steps. Common Mode Maximum Threshold for Speed-Up. This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0–23.625 V in 0.375 V steps. Power Alarm Threshold for Transistors Q1 and Q2. 16 17 18 19 88 Preliminary Rev. 0.5 S i3233 Table 36. SLIC Control Indirect Registers Description (Continued) Addr 20 21 22 23 24 25 26 27 64 Description Power Alarm Threshold for Transistors Q3 and Q4. Power Alarm Threshold for Transistors Q5 and Q6. Loop Closure Filter Coefficient. Ring Trip Filter Coefficient. Thermal Low Pass Filter Pole for Transistors Q1 and Q2. Thermal Low Pass Filter Pole for Transistors Q3 and Q4. Thermal Low Pass Filter Pole for Transistors Q5 and Q6. Common Mode Bias Adjust During Ringing. Recommended value of 0 decimal. DC-DC Converter VOV Voltage (Si3233 only). This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h). 66 Loop Closure Threshold—Lower Bound. This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps. 4.4. FK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). Table 37. FSK Control Indirect Registers Summary Addr 69 70 71 72 73 74 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0] Preliminary Rev. 0.5 89 S i3233 Table 38. FSK Control Indirect Registers Description Addr 69 Description FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a space or “0”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a space or “0”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Amplitude Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a mark or “1”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a mark or “1”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Transition Parameter from 0 to 1. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). FSK Transition Parameter from 1 to 0. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). Reference Page 29 and AN32 70 29 and AN32 71 29 and AN32 72 29 and AN32 73 29 and AN32 74 29 and AN32 90 Preliminary Rev. 0.5 S i3233 5. Pin Descriptions: Si3233 TEST2 PCLK INT CS SCLK SDI SDO NC FSYNC RESET SDCH SDCL VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC 1 38 37 36 35 34 33 32 31 2 3 4 5 6 7 8 9 10 11 30 29 28 27 26 25 24 23 22 21 12 13 14 15 16 17 18 19 20 SDITHRU DCDRV DCFF TEST1 GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP Pin # 35 Name CS Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. Interrupt. Maskable interrupt output. Open drain output for wire-ORed operation. PCM Bus Clock. Clock input. Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 36 37 38 INT PCLK TEST2 1 2 3 4 5 6 7 NC FSYNC RESET SDCH SDCL VDDA1 IREF No Connect. Frame Synch. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. Reset. Active low input. Hardware reset used to place all control registers in the default state. DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the converter. DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the converter. Analog Supply Voltage. Analog power supply for internal analog circuitry. Current Reference. Connects to an external resistor used to provide a high accuracy reference current. Preliminary Rev. 0.5 STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA Description 91 S i3233 Pin # 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Name CAPP QGND CAPM STIPDC SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. Component Reference Ground. SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. TIP Sense. Analog current input used to sense voltage on the TIP lead. SRINGDC RING Sense. Analog current input used to sense voltage on the RING lead. STIPE SVBAT TIP Emitter Sense. Analog current input used to sense voltage on the Q6 emitter lead. VBAT Sense. Analog current input used to sense voltage on dc-dc converter output voltage lead. SRINGE RING Emitter Sense. Analog current input used to sense voltage on the Q5 emitter lead. STIPAC TIP Transmit Input. Analog ac input used to detect voltage on the TIP lead. SRINGAC RING Transmit Input. Analog ac input used to detect voltage on the RING lead. IGMN GNDA IGMP IRINGN IRINGP VDDA2 ITIPP ITIPN VDDD GNDD Differential Audio Input. Connect to external codec. Analog Ground. Ground connection for internal analog circuitry. Differential Audio Input. Connect to external codec. Negative Ring Current Control. Analog current output driving Q3. Positive Ring Current Control. Analog current output driving Q2. Analog Supply Voltage. Analog power supply for internal analog circuitry. Positive TIP Current Control. Analog current output driving Q1. Negative TIP Current Control. Analog current output driving Q4. Digital Supply Voltage. Digital power supply for internal digital circuitry. Digital Ground. Ground connection for internal digital circuitry. Description 92 Preliminary Rev. 0.5 S i3233 Pin # 28 Name TEST1 Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 29 30 DCFF DCDRV DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency. DC Drive/Battery Switch. DC-DC converter control signal output which drives external bipolar transistor. Battery switch control signal output which drives external bipolar transistor. 31 32 33 34 SDITHRU SDI Passthrough. Cascaded SDI output signal for daisy-chain mode. SDO SDI SCLK Serial Port Data Out. Serial port control data output. Serial Port Data In. Serial port control data input. Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description Preliminary Rev. 0.5 93 S i3233 6. Pin Descriptions: Si3201 TIP NC RING VBAT VBATH NC GND VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ITIPP ITIPN IRINGP IRINGN NC STIPE SRINGE NC Pin # 1 2, 6, 9, 12 3 4 5 7 8 10 11 13 14 15 16 Name TIP NC RING VBAT VBATH GND VDD SRINGE STIPE IRINGN IRINGP ITIPN ITIPP Input/ Output I/O — I/O — — — — O O I I I I — Description TIP Output—Connect to the TIP lead of the subscriber loop. No Internal Connection—Do not connect to any electrical signal. RING Output—Connect to the RING lead of the subscriber loop. Operating Battery Voltage—Connect to the battery supply. High Battery Voltage—This pin is internally connected to VBAT. Ground—Connect to a low impedance ground plane. Supply Voltage—Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 µF/6 V capacitor. RING Emitter Sense Output—Connect to the SRINGE pin of the Si321x pin. TIP Emitter Sense Output—Connect to the STIPE pin of the Si321x pin. Negative RING Current Control—Connect to the IRINGN lead of the Si321x. Positive RING Current Drive—Connect to the IRINGP lead of the Si321x. Negative TIP Current Control—Connect to the ITIPN lead of the Si321x. Positive TIP Current Control—Connect to the ITIPP lead of the Si321x. Exposed Thermal Pad—Connect to the bulk ground plane. Bottom-Side Exposed Pad 94 Preliminary Rev. 0.5 S i3233 7. Ordering Guide1,2,3 Device Si3233-X-FM Si3233-X-GM Si3233M-X-FM Si3233M-X-GM Si3201-X-FS Si3201-X-GS Description ProSLIC ProSLIC ProSLIC ProSLIC Line Interface Line Interface DCFF Pin Output DCDRV DCDRV DCDRV DCDRV n/a n/a Package QFN-38 QFN-38 QFN-38 QFN-38 SOIC-16 SOIC-16 Temp Range 0 to 70 °C –40 to 85 °C 0 to 70 °C –40 to 85 °C 0 to 70 °C –40 to 85 °C Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel options; 2500 quantity per reel. 3. All devices are lead-free and RoHS-compliant. Preliminary Rev. 0.5 95 S i3233 8. Package Outline: 38-Pin QFN Figure 19 illustrates the package details for the Si3233. Table 39 lists the values for the dimensions shown in the illustration. Figure 19. 38-Pin Quad Flat No-Lead Package (QFN) Table 39. Package Diagram Dimensions1,2,3 Millimeters Symbol A A1 b D D2 e E E2 L L1 aaa bbb ccc ddd 5.10 0.35 0.03 — — — — 3.10 Min 0.75 0.00 0.18 Nom 0.85 0.01 0.23 5.00 BSC 3.20 0.50 BSC 7.00 BSC 5.20 0.45 0.05 — — — — 5.30 0.55 0.08 0.10 0.10 0.08 0.10 3.30 Max 0.95 0.05 0.30 Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. The drawing conforms to the JEDEC Solid State Outline MO-220, Variation VHKD-1. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 96 Preliminary Rev. 0.5 S i3233 9. Package Outline: 16-Pin SOIC Figure 20 illustrates the package details for the Si3201. Table 40 lists the values for the dimensions shown in the illustration. 16 9 h E H –B– .25 M B M θ x45° 1 B 8 Bottom Side Exposed Pad 2.3 x 3.6 mm L Detail F .25 M C A M B S –A– D C –C– A See Detail F e A1 Seating Plane γ Weight: Approximate device weight is 0.15 grams. Figure 20. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 40. Package Diagram Dimensions Millimeters Symbol A A1 B C D E e H h L γ θ Min 1.35 0 .33 .19 9.80 3.80 5.80 .25 .40 — 0º Max 1.75 0.15 .51 .25 10.00 4.00 6.20 .50 1.27 0.10 8º 1.27 BSC Preliminary Rev. 0.5 97 S i3233 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.5 Updated Section "2.6. Two-Wire Impedance Matching" on page 34 and Register 10, “Two-Wire Impedance Synthesis Control,” on page 44. Removed invalid reference to ZEXT bit. 98 Preliminary Rev. 0.5 S i3233 NOTES: Preliminary Rev. 0.5 99 S i3233 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 100 Preliminary Rev. 0.5