SI5318-EVB

Si 5 3 1 8 - EVB EVALUATION BOARD FOR Si5318 SONET/SDH PRECISION CLOCK MULTIPLIER IC Description Features The Si5318-EVB is the customer evaluation board for the Si5318 SONET/SDH Precision Port Card Clock IC. This board is supplied to customers for evaluation of the Si5318 device. The board provides access to signals associated with normal operation of the device. „ Single supply at 3.3 V Differential I/Os ac coupled on board „ Differential inputs terminated on board „ Control input signals are switch configurable „ Status outputs brought out to headers for easy access. „ Function Block Diagram 3.3 V Supply Power Supply Input CLKIN Rev. 1.0 3/05 + – CLKIN Control Input Jumper Header Status Output Signal Header Control Inputs Status Outputs Si5318 + 50 Ω – 50 Ω t e x t CLKOUT CLKOUT Copyright © 2005 by Silicon Laboratories t e x t Si5318-EVB Si5318-EVB 1. Functional Overview 1.4. Status Signals The Si5318-EVB is the customer evaluation board for the Si5318 SONET/SDH Precision Port Card Clock IC. It is supplied to customers for evaluation of the Si5318 device. The board provides access to signals associated with normal operation of the device. The status outputs from the Si5318 device are each routed to one pin of a two-row header. The signals are arranged so that each signal has a ground pin adjacent to the signal pin for reference. The row of signal pins is marked with an “S”, and the row of ground pins is marked with a “G”. 1.1. Power Consumption Typical supply current draw for the Si5318-EVB is 140 mA. 1.2. Si5318 Control Inputs The control inputs to the Si5318 are each routed from the center pin of a SPDT switch, JP5, to the Si5318 device. Additionally, the switches at JP5 are connected to GND on one side of the switch and to VDD33 on the other side. This arrangement allows easy configuration of each input to either a high or low state. To further reduce the coupling of noise into the device through these control inputs, the signals are routed on internal layers between ground planes. 1.3. RSTN/CAL Settings for Normal Operation and Self-Calibration The RSTN/CAL signal is an LVTTL input to the Si5318 and has an on-chip pulldown mechanism. This pin must be set high for normal operation of the Si5318 device. Setting RSTN/CAL low forces the Si5318 into the reset state. A low-to-high transition of RSTN/CAL enables the part and initiates a self-calibration sequence. The Si5318 device initiates self-calibration at powerup if the RSTN/CAL signal is held high. A self-calibration of the device also can be manually initiated by momentarily pushing and then releasing the RSTN/CAL switch, SW1. Manually initiate self-calibration after changing the state of the BWSEL[1:0]. Whether manually initiated or automatically initiated at powerup, the self-calibration process requires a valid input clock. If the self-calibration is initiated without a valid clock present, the device waits for a valid clock before completing the self-calibration. The Si5318 clock output is set to the lower end of the operating frequency range while the device waits for a valid clock. After the clock input is validated, the calibration process runs to completion, the device locks to the clock input, and the clock output shifts to its target frequency. Subsequent losses of the input clock signal do not require recalibration. If the clock input is lost after self-calibration, the device enters Digital Hold mode. When the input clock returns, the device re-locks to the input clock without performing a self-calibration. 2 Visible indicators, D1 and D2, are added to the LOS and CAL_ACTV signals. The LEDs glow when the signal is active. The LOS LED D1 is illuminated when the device does not recognize a valid clock input. The CAL_ACTV LED, D2, is illuminated when the device is calibrating to an input clock. 1.5. Differential Clock Input Signals The differential clock inputs to the Si5318-EVB board are ac coupled and terminated on the board at a location near the SMA input connectors, J1 and J2. The termination components are located on the top side of the board resistors. The termination circuit consists of two 50 Ω and a 0.1 µF capacitor, such that the positive and negative inputs of the differential pair each see a 50 Ω termination to “ac ground,” and the line-to-line termination impedance is 100 Ω. For single-ended operation, supply a signal to one of the differential inputs (usually the positive input). The other input should be shorted to ground using an SMA shorting plug. The on-board termination circuit provides a 50 Ω termination to ac-ground for each leg of the differential pair. 1.6. Differential Clock Output Signals The differential clock outputs from the Si5318 device are routed to the perimeter of the circuit board using 50 Ω transmission line structures. The capacitors that provide ac-coupling are located near the clock output SMA connectors, J4 and J5. 1.7. Internal Regulator Compensation The Si5318-EVB contains pad locations for a resistor and a capacitor between the VDD25 node and ground. The resistor pads are populated with a 0 Ω resistor. The capacitor pads are populated with a low ESR 33 µF tantalum capacitor. This is the suggested compensation circuit for Si5318 devices. The acceptable range for the time constant at this node is 15 µs to 50 µs. The capacitor used on the board is a 33 µF capacitor with an ESR of .8 Ω. This yields a time constant of 26.4 µs. Preliminary Rev. 1.0 Si5318-EVB 1.8. Default Jumper Settings The default jumper settings for the Si5318-EVB board are given in Table 1. Table 1. Si5318-EVB Assembly Rev. A Default Jumper/Switch Settings Location JP5 Signal State Notes VALTIME 0 100 ms Validation Time BWSEL[0] 0 Loop Filter Bandwidth = 800 Hz BWSEL[1] 1 Loop Filter Bandwidth = 800 Hz INFRQSEL[0] 1 Clock IN = 19.44 MHz INFRQSEL[1] 0 Clock IN = 19.44 MHz INFRQSEL[2] 0 Clock IN = 19.44 MHz FRQSEL[0] 0 Clock Out = 155.52 MHz FRQSEL[1] 1 Clock Out = 155.52 MHz DBLBW 0 Selected bandwidth not doubled FXDDELAY 0 Fixed Delay disabled Preliminary Rev. 1.0 3 Preliminary Rev. 1.0 3.3V 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 25 27 28 30 101-0161 SW1 R13 4.99k, 0603 3.3V POS2 1 3 4 6 7 9 10 12 13 15 16 18 19 21 22 24 25 27 28 30 JP5 29 26 23 20 17 14 11 8 5 2 1 3 + 1 3 JP8 0, 0603 R14 10x3 HEADER 29 26 23 20 17 14 11 8 5 2 L1 2 2 FXDDELAY VALTIME BWSEL_0 BWSEL_1 DBLBW FRQSEL_0 FRQSEL_1 INFRQSEL_0 INFRQSEL_1 INFRQSEL_2 C8 33uf, 3528 RSTN/CAL C9 0.1uf, 0603 ClkIn- R3 49.9, 0603 ClkIn+ C3 R2 49.9, 0603 0.1uf, 0603 22pf, 0603 C11 C10 2200pf, 0603 3.3V REXT RSTN/CAL VALTIME FXDDELAY DBLBW BWSEL[1] BWSEL[0] RSVD_GND RSVD_GND FRQSEL[1] FRQSEL[0] INFRQSEL[2] INFRQSEL[1] INFRQSEL[0] CLKIN+ CLKIN- CAL_ACTV DH_ACTV LOS R4 10k, 0603 H2 H3 H4 B4 D2 C1 B1 A2 A3 H8 H5 H1 G1 F1 D1 E1 3.3V 0, 0603 R9 + 2.5V C15 33uf, 3528 U1 Si5318BC 1 3 5 1 3 5 JP2 2 4 6 2 4 6 RSVD_GND RSVD_GND RSVD_GND RSVD_GND RSVD_GND RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC RSVD_NC CAL_ACTV DH_ACTV LOS CLKOUT+ CLKOUT- C8 B7 B6 B3 B2 B5 A6 A5 A4 A7 A8 B8 E8 D8 F8 H6 H7 CAL_ACTV DH_ACTV LOS ClkOut+ ClkOut- Figure 1. Si5318-EVB Schematic RSTN/CAL VALTIME FXDDELAY DBLBW BWSEL_1 BWSEL_0 FRQSEL_1 FRQSEL_0 INFRQSEL_2 INFRQSEL_1 INFRQSEL_0 2.5V D3 D4 D5 E3 E4 E5 C2 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 600 ohm, 1206 D6 D7 E6 E7 F3 F4 F5 F6 F7 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND C3 C4 C5 C6 C7 E2 F2 G2 G3 G4 G5 G6 G7 G8 POS1 C1 0.1uf, 0603 G SMA, thruhole RA 0.1uf, 0603 C2 SMA, thruhole RA CAL_ACTV J2 J1 D S 4 Q2 FDN337N LN1271RAL D2 R12 1k, 0603 ClkIn- ClkIn+ LOS G ClkOut- ClkOut+ D S J3 J4 J5 Q1 FDN337N LN1271RAL D1 0, 0603 R6 1k, 0603 R7 SMA, thruhole RA 0.1uf, 0603 C7 SMA, thruhole RA 0.1uf, 0603 C6 3.3V Si5318-EVB . Si5318-EVB 2. Bill of Materials Reference Description Manufacturer Part Number C1,C2,C3,C6,C7,C9 0.1 µf, 0603 Venkel C0603X7R160104KNE C15,C8 33 µf, 3528 Venkel TA6R3TCR336KBR C10 2200pf, 0603 Venkel C0603X7R160222KNE C11 22pf, 0603 Venkel C0603C0G500220KNE D1, D2 LED, SM, red Panasonic LN1271RA2 JP8 1x3 HEADER JP2 HEADER 3x2 JP5 10x3 HEADER J1,J2,J4,J5 SMA, thruhole RA Johnson Components 142-0701-301 J3 power connector, 2 pin Phoenix Contact 140-A-111-02 1729018 L1 600 Ω, 1206 Murata BLM31A601S Q1,Q2 MOS, SM, FDN337N Fairchild FDN337N R13 4.99 kΩ, 0603 Venkel CR0603-16W-4991FT R2,R3 49.9 Ω, 0603 Venkel CR0603-16W-49R9FT R9, R14, R7 0, 0603 Venkel CR0603-16W-000T R4 10 kΩ, 0603 Venkel CR0603-16W-1002FT R6, R12 1 k, 0603 Venkel CR0603-16W-1001FT SW1 101-0161 Mouser 101-0161 U4 Si5318_revA Silicon Laboratories Si5318-A-BC Preliminary Rev. 1.0 5 Figure 2. Si5318-EVB Top Silkscreen Si5318-EVB 6 Preliminary Rev. 1.0 Figure 3. Si5318-EVB—Layer 1, Component Side Si5318-EVB Preliminary Rev. 1.0 7 Figure 4. Si5318-EVB—Layer 2, High Speed Signals Si5318-EVB 8 Preliminary Rev. 1.0 Figure 5. Si5318-EVB—Layer 3, GND Si5318-EVB Preliminary Rev. 1.0 9 Figure 6. Si5318-EVB—Layer 4, VDD 2.5 Si5318-EVB 10 Preliminary Rev. 1.0 Figure 7. Si5318-EVB—Layer 5, GND Si5318-EVB Preliminary Rev. 1.0 11 Figure 8. Si5318-EVB—Layer 6, VDD 3.3 Si5318-EVB 12 Preliminary Rev. 1.0 Figure 9. Si5318-EVB—Layer 7, GND Si5318-EVB Preliminary Rev. 1.0 13 Figure 10. Si5318-EVB—Layer 8, Bottom Si5318-EVB 14 Preliminary Rev. 1.0 Figure 11. Si5318-EVB Bottom Silkscreen Si5318-EVB Preliminary Rev. 1.0 15 Si5318-EVB CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 16 Preliminary Rev. 1.0