Si5318
SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C
Features
Jitter generation as low as
0.7 psRMS (typ), compliant with
GR-253-CORE OC-48
specifications
No external components
(other than a resistor and
standard bypassing)
Input clock ranges at 19, 39, 78,
and 155 MHz
Output clock ranges at 19 or
155 MHz
Digital hold for loss of input clock
Selectable loop bandwidth
Loss-of-signal alarm output
Low power
Small size (9x9 mm)
Si5318
Si5318
Ordering Information:
Applications
SONET/SDH line/port cards
Optical modules
Core switches
Digital cross connects
Terabit routers
See page 26.
Description
The Si5318 is a precision clock multiplier designed to exceed the requirements of
high-speed communication systems, including OC-48. The device phase locks to
an input clock in the 19, 39, 78, or 155 MHz frequency range and generates a low
jitter output clock in the 19 or 155 MHz range. Silicon Laboratories’ DSPLL®
technology delivers all PLL functionality with unparalleled performance while
eliminating external loop filter components, providing programmable loop
parameters, and simplifying design. The Si5318 establishes a new standard in
performance and integration for ultra-low-jitter clock generation. It operates from a
single 3.3 V supply.
Functional Block Diagram
REXT
VDD
GND
Biasing & Supply Regulation
FXDDELAY
CLKIN+
CLKIN–
VALTIME
LOS
CAL_ACTV
2
÷
÷
Signal
Detect
3
INFRQSEL[2:0]
Rev. 1.0 4/05
DSPLL
DH_ACTV
®
2
Calibration
BWSEL[1:0]
2
CLKOUT+
CLKOUT–
FRQSEL[1:0]
RSTN/CAL
DBLBW
Copyright © 2005 by Silicon Laboratories
Si5318
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5318
NOTES:
2
Rev. 1.0
Si5318
TA B L E O F C O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Pin Descriptions: Si5318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 1.0
3
Si5318
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5318 Supply Voltage3
Symbol
Test Condition
Min1
Typ
Max1
Unit
TA
–202
25
85
°C
VDD33
3.135
3.3
3.465
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5318 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient
temperature of –20 to 85° C.
3. The Si5318 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of Figure 5 on page 13.
4
Rev. 1.0
Si5318
CLKIN+
CLKIN–
VIS
A. Operation with Single-Ended Clock Input
Note: When using single-ended clock sources, the unused clock
input on the Si5318 must be ac-coupled to ground.
CLKIN+
0.5 VID
CLKIN–
(CLKIN+) – (CLKIN–)
VID
B. Operation with Differential Clock Input
Note: Transmission line termination, when required, must be provided
externally.
Figure 1. CLKIN Voltage Characteristics
80%
20%
tF
tR
Figure 2. Rise/Fall Time Measurement
(C L K IN + ) – (C L K IN – )
0 V
tLOS
Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition
Rev. 1.0
5
Si5318
Table 2. DC Characteristics, VDD = 3.3 V
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Supply Current
Power Dissipation Using 3.3 V Supply
Common Mode Input Voltage
(CLKIN)
1,2,3
Symbol
Test Condition
Min
Typ
Max
Unit
IDD
Clock in = 19.44 MHz
Clock out = 155.52 MHz
—
135
145
mA
PD
Clock in = 19.44 MHz
Clock out = 155.52 MHz
—
445
479
mW
1.0
1.5
2.0
V
VICM
Single-Ended Input Voltage2,3,4
(CLKIN)
VIS
See Figure 1A
200
—
5004
mVPP
Differential Input Voltage Swing2,3,4
(CLKIN)
VID
See Figure 1B
200
—
5004
mVPP
Input Impedance
(CLKIN+, CLKIN–)
RIN
—
80
—
kΩ
Differential Output Voltage Swing
(CLKOUT)
VOD
100 Ω Load
Line-to-Line
720
938
1155
mVPP
Output Common Mode Voltage
(CLKOUT)
VOCM
100 Ω Load
Line-to-Line
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
ISC(–)
–60
—
—
mA
Output Short to VDD25 (CLKOUT)
ISC(+)
—
15
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
IIL
—
—
50
µA
Input High Current (LVTTL Inputs)
IIH
—
—
50
µA
Internal Pulldowns (All LVTTL Inputs)
Ipd
—
—
50
µA
Input Impedance (LVTTL Inputs)
RIN
50
—
—
kΩ
Output Voltage Low (LVTTL Outputs)
VOL
IO = .5 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO = .5 mA
2.0
—
—
V
Notes:
1. The Si5318 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5318 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mVPP for optimal performance.
6
Rev. 1.0
Si5318
Table 3. AC Characteristics
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
19.436
38.872
77.744
155.48
—
—
—
—
21.685
43.369
86.738
173.48
MHz
Input Clock Frequency (CLKIN)
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
fCLKIN
Input Clock Rise Time (CLKIN)
tR
Figure 2
—
—
11
ns
Input Clock Fall Time (CLKIN)
tF
Figure 2
—
—
11
ns
CDUTY_IN
40
50
60
%
fO_19
fO_155
—
19.436
155.48
—
—
—
—
21.685
173.48
MHz
Input Clock Duty Cycle
CLKOUT Frequency Range*
FRQSEL[1:0] = 00 (no output)
FRQSEL[1:0] = 01
FRQSEL[1:0] = 10
CLKOUT Rise Time
tR
Figure 2; single-ended; after
3 cm of 50 Ω FR4 stripline
—
213
260
ps
CLKOUT Fall Time
tF
Figure 2; single-ended; after
3 cm of 50 Ω FR4 stripline
—
191
260
ps
CDUTY_O
Differential:
(CLKOUT+) – (CLKOUT–)
48
—
52
%
20
—
—
ns
6/
fo_155
8/
fo_155
s
/fo_155
3
/fo_155
5/
2 x fo_155
9
/4 x fo_155
9
/4 x fo_155
—
—
—
—
—
—
0.09
12.0
—
—
0.22
14.1
s
CLKOUT Duty Cycle
UT
RSTN/CAL Pulse Width
tRSTN
Transitionless Period Required on
CLKIN for Detecting a LOS
Condition.
INFRQSEL[2:0] = 001
INFRQSEL[2:0] = 010
INFRQSEL[2:0] = 011
INFRQSEL[2:0] = 100
INFRQSEL[2:0] = 101
INFRQSEL[2:0] = 110
tLOS
Recovery Time for Clearing an
LOS Condition
VALTIME = 0
VALTIME = 1
tVAL
Figure 3
4
Measured from when a valid
reference clock is applied
until the LOS flag clears
8
/fo_155
8
/fo_155
8/
fo_155
8
/fo_155
8
/fo_155
*Note: The Si5318 provides a 1/8, 1/4, 1/2, 1, 2, 4 or 8x clock frequency multiplication function.
Rev. 1.0
7
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 8 Hz
1000
—
—
ns
f = 80 Hz
100
—
—
ns
f = 800 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.87
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.3
10.0
ps
FBW
BW = 800 Hz
—
800
—
Hz
JP
< 800 Hz
—
0.0
0.05
dB
f = 16 Hz
500
—
—
ns
f = 160 Hz
50
—
—
ns
f = 1600 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.78
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.0
9.0
ps
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.00
0.05
dB
JTOL(PP)
f = 16 Hz
1000
—
—
ns
f = 160 Hz
100
—
—
ns
f = 1600 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.82
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.3
10.0
ps
FBW
BW = 1600 Hz
—
1600
—
Hz
JP
< 1600 Hz
—
0.0
0.1
dB
Wander/Jitter at 800 Hz Bandwidth
(BWSEL[1:0] = 10 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 10 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 1600 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 10)
Wander/Jitter Transfer Peaking
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
8
Rev. 1.0
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
f = 32 Hz
500
—
—
ns
f = 320 Hz
50
—
—
ns
f = 3200 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.72
0.9
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.8
10.0
ps
FBW
BW = 3200 Hz
—
3200
—
Hz
JP
< 3200 Hz
—
0.05
0.1
dB
JTOL(PP)
f = 32 Hz
1000
—
—
ns
f = 320 Hz
100
—
—
ns
f = 3200 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.86
1.2
ps
JGEN(PP)
12 kHz to 20 MHz
—
7.7
10.0
ps
FBW
BW = 3200 Hz
—
3200
—
Hz
JP
< 3200 Hz
—
0.05
0.1
dB
f = 64 Hz
500
—
—
ns
f = 640 Hz
50
—
—
ns
f = 6400 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.7
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.6
9.0
ps
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 01 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 3200 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 0)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 00 and DBLBW = 1)
Jitter Tolerance (see Figure 7)
CLKOUT RMS Jitter Generation
CLKOUT Peak-Peak Jitter Generation
Jitter Transfer Bandwidth (see Figure 6)
Wander/Jitter Transfer Peaking
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude
for the Si5318 (tPT_MTIE) never reaches one nanosecond.
Rev. 1.0
9
Si5318
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
JTOL(PP)
f = 64 Hz
1000
—
—
ns
f = 640 Hz
100
—
—
ns
f = 6400 Hz
10
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
1.0
1.4
ps
JGEN(PP)
12 kHz to 20 MHz
—
9.4
12.0
ps
FBW
BW = 6400 Hz
—
6400
—
Hz
JP
< 6400 Hz
—
0.05
0.1
dB
f = 128 Hz
500
—
—
ns
f = 1280 Hz
50
—
—
ns
f = 12800 Hz
5
—
—
ns
JGEN(RMS)
12 kHz to 20 MHz
—
0.74
1.0
ps
JGEN(PP)
12 kHz to 20 MHz
—
6.9
9.0
ps
FBW
BW = 12800 Hz
—
12800
—
Hz
JP
< 12800 Hz
—
0.05
0.1
dB
TAQ
RSTN/CAL high to
CAL_ACTV low, with valid
clock input and
VALTIME = 0
—
300
350
ms
CCO_TG
Stable Input Clock;
Temperature
Gradient
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