SI5383A-D10632-GMR

Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs KEY FEATURES The Si5383/84 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization. The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588 DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows the device to accept a TCXO/OCXO reference with a wide frequency range, and the reference clock jitter does not degrade the output performance. The Si5383/84 is configurable via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro software. Factory pre-programmed devices are also available. • One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures • Input frequency range: • External crystal: 25-54 MHz • REF clock: 5-250 MHz • Diff clock: 8 kHz - 750 MHz • LVCMOS clock: 1 PPS, 8 kHz - 250 MHz • Output frequency range: • Differential: 1 PPS, 100 Hz - 718.5 MHz • LVCMOS: 1 PPS, 100 Hz - 250 MHz • Ultra-low jitter of less than 150 fs Applications • Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2 • Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1 • Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.8273.2 • IEEE 1588 (PTP) slave clock synchronization • Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization • 1 Hz/1 PPS Clock Multiplier XTAL REF XA REFb XB Si5383/84 OCXO/ TCXO OSC IN4 DSPLL D IN2 ÷FRAC IN1 ÷FRAC IN0 ÷FRAC DSPLL A I2C 1 FLASH Control/ Status Si5383 Si5384 IN3 ÷INT OUT0 ÷INT OUT1 ÷INT OUT2 ÷INT OUT3 ÷INT OUT4 ÷INT OUT5 ÷INT OUT6 DSPLL C Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 1 Si5383/84 Rev D Data Sheet • Feature List 1. Feature List The Si5383/84 highlighted features are listed below. • One or three DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures • Meets the requirements of: • ITU-T G.8273.1 T-GM • ITU-T G.8273.2 T-BC, T-TSC • Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2 • ITU-T G.812 Type III, IV • ITU-T G.813 Option 1 • Telcordia GR-1244, GR-253 (Stratum-3/3E) • Each DSPLL generates any output frequency from any input frequency • Input frequency range: • External crystal: 25 - 54 MHz • REF clock: 5 - 250 MHz • Diff clock: 8 kHz - 750 MHz • LVCMOS clock: 1 PPS, 8 kHz - 250 MHz • Output frequency range: • Differential: 1 PPS, 100 Hz - 718.5 MHz • LVCMOS: 1 PPS, 100 Hz - 250 MHz • Pin or software controllable DCO on each DSPLL with typical resolution to 1 ppt/step 2 • TCXO/OCXO reference input determines DSPLL free-run/holdover accuracy and stability • Excellent jitter performance • Programmable loop bandwidth per DSPLL: • 1 PPS inputs: 1 mHz and 10 mHz • All other inputs: 1 mHz to 4 kHz • Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML • Core voltage: • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% • Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V • Built-in power supply filtering • Status monitoring: • LOS, LOL: 1 PPS-750 MHz • OOF: 8 kHz-750 MHz 2 • I C Serial Interface • ClockBuilderTM Pro software tool simplifies device configuration • 5 input, 7 output, 56-pin LGA • Temperature range: –40 to +85 °C • Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 2 Si5383/84 Rev D Data Sheet • Ordering Guide 2. Ordering Guide Table 2.1. Ordering Guide Ordering Part Number (OPN)1,2 Si5383A-Dxxxxx-GM # of DSPLLs Maximum Output Frequency Package RoHS-6, Pb-Free Temperature Range 3 718.5 MHz 56-Lead 8×8 LGA Yes –40 to 85 °C Si5383B-Dxxxxx-GM Si5384A-Dxxxxx-GM 350 MHz 1 Si5384B-Dxxxxx-GM 718.5 MHz 350 MHz Si5383-D-EVB3 — — Evaluation Board — — SiOCXO1-EVB — — OCXO Evaluation Board — — Notes: 1. Add an R at the end of the OPN to denote tape and reel ordering options. 2. Custom, factory preprogrammed devices are available as well as unconfigured base devices. See figures below for 5-digit numerical sequence nomenclature. 3. The Si5383-D-EVB ships with an SiOCXO1-EVB board included. Additional SiOCXO1-EVB boards may be ordered separately if needed. 2.1 Ordering Part Number Fields Si538fg-R00xxx-GM Timing product family f = Network Sync family member (3, 4) g = Device grade (A, B) Product Die Revision (D) Base device indicator* Firmware revision indicator** Package, ambient temperature range (LGA, -40°C to + 85°C) * Firmware is preprogrammed into base devices, but no configuration settings are present in the device ** 3 digits corresponding to the firmware revision preprogrammed into base devices Figure 2.1. Ordering Guide Part Number Fields for Base Devices 3 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 3 Si5383/84 Rev D Data Sheet • Ordering Guide Si538fg-Rxxxxx-GM Timing product family f = Network Sync family member (3, 4) g = Device grade (A, B) Product Die Revision (D) Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (LGA, -40°C to +85°C) ** 5 digits; assigned by ClockBuilder Pro for custom, factory-preprogrammed OPN devices. The firmware revision for custom OPN devices is determined by ClockBuilder Pro when a custom part number is created. Figure 2.2. Ordering Guide Part Number Fields for Custom OPN Devices 4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 4 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 3.1 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 DSPLL Loop Bandwidth in Standard Input Mode 3.3.1 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 7 3.4 DSPLL Loop Bandwidth in 1 PPS Mode 3.4.1 Smartlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 7 3.5 Modes of Operation . . 3.5.1 Initialization and Reset 3.5.2 Free-run Mode . . 3.5.3 Lock Acquisition Mode 3.5.4 Locked Mode . . . 3.5.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . 3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) 3.6.2 Frequency Increment/Decrement Using the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .11 3.7 External Reference (XA/XB, REF/REFb) . 3.7.1 External Crystal (XA/XB) . . . . . 3.7.2 External Reference (REF/REFb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 8 9 9 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 .12 .13 3.8 Inputs (IN0, IN1, IN2, IN3, IN4) . . . . . . . . . . . . 3.8.1 Input Selection . . . . . . . . . . . . . . . . 3.8.2 Manual Input Selection . . . . . . . . . . . . . . 3.8.3 Automatic Input Selection in Standard Input Mode . . . . 3.8.4 Input Configuration and Terminations . . . . . . . . . 3.8.5 Hitless Input Switching in Standard Input Mode . . . . . 3.8.6 Ramped Input Switching in Standard Input Mode . . . . . 3.8.7 Glitchless Input Switching . . . . . . . . . . . . . 3.8.8 Synchronizing to Gapped Input Clocks in Standard Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 .14 .14 .14 .15 .15 .16 .16 .16 3.9 Fault Monitoring . . . . 3.9.1 Input LOS Detection. . 3.9.2 XA/XB LOS Detection . 3.9.3 OOF Detection . . . 3.9.4 Precision OOF Monitor . 3.9.5 Fast OOF Monitor . . 3.9.6 LOL Detection . . . . 3.9.7 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 .17 .17 .18 .18 .18 .19 .21 3.10 Outputs . . . . . . . . 3.10.1 Output Crosspoint . . . 3.10.2 Support For 1 Hz Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 .22 .23 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 5 3.10.3 Differential Output Terminations . . . . . . . . . . . 3.10.4 Output Signal Format . . . . . . . . . . . . . . . 3.10.5 Programmable Common-Mode Voltage For Differential Outputs 3.10.6 LVCMOS Output Impedance Selection . . . . . . . . . 3.10.7 LVCMOS Output Signal Swing . . . . . . . . . . . . 3.10.8 LVCMOS Output Polarity. . . . . . . . . . . . . . 3.10.9 Output Enable/Disable . . . . . . . . . . . . . . 3.10.10 Output Disable During LOL . . . . . . . . . . . . 3.10.11 Output Disable During XAXB_LOS . . . . . . . . . . 3.10.12 Output Driver State When Disabled. . . . . . . . . . 3.10.13 Synchronous/Asynchronous Output Disable . . . . . . . 3.10.14 Output Divider (R) Synchronization . . . . . . . . . . 3.10.15 Programmable Phase Offset in 1 PPS Mode. . . . . . . 3.11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 .24 .24 .25 .25 .25 .25 .25 .25 .25 .25 .26 .26 . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.12 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.13 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .26 3.14 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .26 3.15 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .27 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Typical Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 42 7. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . 44 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 . . . Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 6 Si5383/84 Rev D Data Sheet • Functional Description 3. Functional Description The Si5383 offers three DSPLLs and the Si5384 offers one DSPLL that can be independently configured and controlled through the serial interface. In standard input mode, all DSPLLs support high frequency inputs. DSPLL D can be configured to operate in 1 PPS input mode to lock to a 1 Hz input clock. Regardless of the input mode, any of the DSPLLs can be used to generate any valid output frequency. Each of the DSPLLs have locked, free-run, and holdover modes of operation with an optional DCO mode for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The reference input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs (IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine. Two additional single-ended inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any of the DSPLLs using a flexible crosspoint connection. Output 5 is the only output that can be configured for a 1 Hz output to support 1 PPS. 3.1 Standards Compliance Each of the DSPLLs meet the applicable requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia GR-1244 and GR-253 as shown in the compliance report for standard input mode. The DCO feature enables IEEE1588 (PTP) implementations in addition to hybrid SyncE + IEEE1588 (T-BC). 3.2 Frequency Configuration The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 3.3 DSPLL Loop Bandwidth in Standard Input Mode The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. Table 3.1. Loop Bandwidth Requirements SONET (Telcordia) SDH (ITU-T) SyncE (ITU-T) Loop Bandwidth GR-253 Stratum 3E G.812 Type III — 0.001 Hz GR-253 Stratum 3 G.812 Type IV G.8262 EEC Option 2 < 0.1 Hz — G.813 Option 1 G.8262 EEC Option 1 1 - 10 Hz 3.3.1 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. In standard input mode, the fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock feature can be enabled or disabled independently for each of the DSPLLs for input frequencies > 8 kHz.. 3.4 DSPLL Loop Bandwidth in 1 PPS Mode When operating in 1 PPS input mode, the Si5383/84 offers two choices of loop bandwidth for DSPLL D: 1 mHz or 10 mHz. 3.4.1 Smartlock Feature When operating in 1 PPS input mode, the Si5383/84 offers the Smartlock feature to achieve fast locking to 1 PPS inputs. The Smartlock feature locks to 1 PPS inputs in two phases. During the first phase, large adjustments are made to eliminate the majority of the frequency and phase error. During the second phase, finer adjustments are made until the PLL is locked. Once the PLL is locked, the DSPLLs loop bandwidth will automatically revert to the DSPLL loop bandwidth setting. 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 7 Si5383/84 Rev D Data Sheet • Functional Description 3.5 Modes of Operation Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 8. The following sections describe each of these modes in greater detail. 3.5.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs, while a soft reset can either affect all or each DSPLL individually. It is recommended that the device be held in reset during power-up by asserting the RSTb pin. RSTb should be released once all supplies have reached operational levels. The RSTb pin functions as an open-drain output, which drives low during POR. External devices must be configured as open-drain to avoid contention. Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected Lock Acquisition (Fast Lock or Smart Lock) An input is qualified and available for selection No valid input clocks available for selection Phase lock on selected input clock is achieved An input is qualified and available for selection Holdover Mode (1 PPS) Locked Mode Holdover Mode Input Clock Switch Yes No Selected input clock fails (Standard input mode) Holdover History Valid? Yes No No valid input clocks available for selection Selected input clock fails (1 PPS input mode) Other Valid Clock Inputs Available? Figure 3.1. Modes of Operation 3.5.2 Free-run Mode Once power is applied to the Si5383/84 and initialization is complete, all three DSPLLs will automatically enter freerun if no clock input is applied. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the clock source at the reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy and stability to meet the synchronization standards as shown in the following table: 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 8 Si5383/84 Rev D Data Sheet • Functional Description Table 3.2. Free-run Accuracy for North American and European Synchronization Standards SONET (Telcordia) SDH (ITU-T) SyncE (ITU-T) Free-run Accuracy GR-253 Stratum 3E G.812 Type III — ±4.6 ppm GR-253 Stratum 3 G.812 Type IV G.8262 EEC Option 2 ±4.6 ppm — G.813 Option 1 G.8262 EEC Option 1 ±4.6 ppm 3.5.3 Lock Acquisition Mode Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled for inputs > 8 kHz, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. If the input frequency is configured for 1 PPS, the Smartlock mode is used. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 3.5.4 Locked Mode Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is achieved. Refer to Section 3.9.6 LOL Detection for more details on the operation of the loss of lock circuit. 3.5.5 Holdover Mode Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores several seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time Programmable historical data window used to determine the final holdover value (Seconds) Programmable delay (Seconds) 0s Figure 3.2. Programmable Holdover Window When entering holdover, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. When the clock input becomes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless. In standard input mode, the DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching see Section 3.8.6 Ramped Input Switching in Standard Input Mode. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 9 Si5383/84 Rev D Data Sheet • Functional Description 3.6 Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or decrements (FDEC). However due to slower update rates over the I2C interface, it is recommended to use pin controls for adjusting the frequency in DCO mode. A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO mode is available when the DSPLL is operating in locked mode. The DCO mode is mainly used with standard input mode in IEEE1588 (PTP) applications where a clock needs to be generated based on recovered timestamps. In this case timestamps are recovered by the PHY/MAC. A processor containing servo software controls the DCO to close the timing loop between the master and slave nodes. The processor has the option of using the FINC/FDEC pin controls to update the DCO frequency or by controlling it through the serial interface. When operating in 1 PPS input mode, an additional enhanced DCO mode is enabled in the holdover state to facilitate DCO steering. This is useful for applications that require Assisted Partial Timing Support (APTS). 3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) Controlling the output frequency with pin controls is available in standard input mode. This feature involves asserting the FINC or FDEC pins to step (increment or decrement) the DSPLL’s output frequency. Both the step size and DSPLL selection (A, C, D) is made through the serial interface by writing to register bits. Si5383/84 PD LPF FSW_MASK_A ÷ 0x0422 + - FINC FDEC Mn_A Md_A DSPLL A Frequency Step Word 0x0423 – 0x0429 0x001D 0x0622 Si5383 PD FSW_MASK_C LPF ÷ Mn_C Md_C DSPLL C + - Frequency Step Word 0x0623 – 0x0629 PD LPF 0x0723 SDA 2 IC Si5384 FSW_MASK_D ÷ Mn_D Md_D DSPLL D + - Frequency Step Word 0x0724 – 0x072A FINC FDEC SCL Figure 3.3. Controlling the DCO Mode By Pin Control 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 10 Si5383/84 Rev D Data Sheet • Functional Description 3.6.2 Frequency Increment/Decrement Using the Serial Interface Controlling the DSPLL frequency through the serial interface is available. This feature involves asserting the FINC or FDEC bits to activate the frequency change defined by the frequency step word. A set of mask bits selects the DSPLL(s) that is affect by the frequency change. 3.7 External Reference (XA/XB, REF/REFb) The external crystal at the XA/XB pins determines jitter performance of the output clocks, and the external reference clock at the REF/ REFb pins determines the frequency accuracy and stability during free-run or holdover modes, and the MTIE/TDEV performance when the DSPLL is locked. Jitter from the external clock on the REF/REFb pins will have little to no effect on the output jitter performance, depending upon the selected bandwidth. This allows using a lower-cost TCXO/OCXO with a higher phase noise floor or an external reference clock distributed over long PCB traces or across a backplane, without impacting output jitter. XTAL + OSC Determines Output Jitter Performance XTAL TCXO/ OCXO XA XB REF External Reference Clock Determines Output Frequency Accuracy and Stability, and MTIE/TDEV Performance REFb OSC Si5383/84 Figure 3.4. External Reference Connections 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 11 Si5383/84 Rev D Data Sheet • Functional Description 3.7.1 External Crystal (XA/XB) The external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLLs. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. A crystal in the range of 48 to 54 MHz is recommended for best jitter performance. Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accommodated. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of ±1000 ppm. The Si5383/84 Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Although it is not recommended, the device can also accommodate an external clock at the XA/XB pins instead of a crystal. Selection between the external crystal or clock is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. Refer to Chapter 5. Electrical Specifications for reference clock requirements when using this mode. The Si5383/84 Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. C1 is recommended to increase the slew rate at Xa C1 R1 48-54 MHz XTAL Note: See Pin Descriptions for X1/X2 connections 0.1 uF 0.1 uF XB 2xCL XA X1 2xCL OSC XB 2xCL nc XA XB 2xCL XA nc X1 R1 453 665 274 R2 549 549 732 C1 12 pF 10 pF 30 pF 3.3 V * These settings should be used if the CMOS level is up to 4 V pp in order to limit the input at Xa to less than 2 V ppse. 2xCL OSC OSC Crystal Resonator Connections (Recommended) 0.1 uF nc 0.1 uF X1 2xCL ÷PXAXB ÷PXAXB Si5383/84 XO VDD 3.3 V 3.3 V 2.5 V R2 100 nc X2 0.1 uF Si5383/84 Differential XO/Clock Connection (Not Recommended) ÷PXAXB Si5383/84 Single-Ended XO Connection (Not Recommended) Note: XA and XB must not exceed the maximum input voltage listed in Data Sheet Table Input Clock Specifications Figure 3.5. Crystal Resonator Connections 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 12 Si5383/84 Rev D Data Sheet • Functional Description 3.7.2 External Reference (REF/REFb) The external reference at the REF/REFb pins is used to determine output frequency accuracy and stability during free-run and holdover modes. This reference is usually from a TCXO or OCXO and can be connected differentially or single-ended as shown in the figure below: Standard Differential AC-Coupled Input Buffer 5 – 250 MHz TCXO/OCXO 0.1 µF REF 100 REFb Si5383/84 0.1 µF Standard Single-Ended - AC-Coupled Input Buffer 5 – 250 MHz TCXO/OCXO C1 Rs 0.1 µF 50 3.3/2.5/1.8 V LVCMOS RS matches the CMOS driver to a 50 ohm transmission line (if used) R1 R2 REF REFb 0.1 µF Si5383/84 0.1 µF * When 3.3 V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the output jitter due to faster input slew rate at INx. If attenuation is not needed for Inx 2.2 V 10 — — µs Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 29 Si5383/84 Rev D Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. 1 PPS input enabled on DSPLL D. Excludes power in termination resistors. 2. Test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. 1 PPS input not enabled. Excludes power in termination resistors. 3. Differential outputs terminated into an AC coupled 100 Ω load. 4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV= 3, which is the strongest driver setting. Refer to the Si5383/84 Reference Manual for more details on register settings. 5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. LVCMOS Output Test Configuration Differential Output Test Configuration IDDO OUT 50 IDDO 0.1 uF 100 OUTb 50 30 Trace length 5 inches 0.1 uF 50 OUT OUTb 499 Ω 4.7 pF 50 499 Ω 4.7 pF 0.1 uF 50 Ω Scope Input 56 Ω 0.1 uF 50 Ω Scope Input 56 Ω Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 30 Si5383/84 Rev D Data Sheet • Electrical Specifications Table 5.3. Input Clock Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Standard Input Buffer with Differential or Single-Ended Configuration - AC-Coupled (IN0, IN1, IN2, REF) Input Frequency Range Voltage Swing 1 fIN VIN Differential 0.008 — 750 Single-ended/LVCMOS 0.008 — 250 REF 5 — 250 Differential AC-coupled fIN< 250 MHz 100 — 1800 mVpp_se Differential AC-coupled 250 MHz < fIN< 750 MHz 225 — 1800 mVpp_se Single-Ended AC-coupled fIN < 250 MHz 100 — 3600 mVpp_se MHz Slew Rate 2,3 SR 400 — — V/μs Duty Cycle DC 40 — 60 % Input Capacitance CIN — 2.4 — pF Input Resistance RIN Differential — 16 — Single-ended/LVCMOS — 8 — LVCMOS Mode 0.008 — 250 MHz Pulsed CMOS Mode 0.008 — 1 MHz 1 PPS Mode — 1 — Hz VIL — — 0.4 V VIH 0.8 — — V SR 400 — — V/μs LVCMOS CMOS Mode (250 MHz @ 40% Duty Cycle) 1.6 — — ns Pulsed CMOS (1 MHz @ 5% Duty Cycle) 50 — — ns 1 PPS Mode 10 — — us LVCMOS 40 — 60 % Pulsed CMOS 5 — 95 % — 8 — kΩ kΩ LVCMOS/Pulsed CMOS - DC-Coupled (IN0, IN1, IN2) 4 Input Frequency Input Voltage Slew Rate 2,3 Minimum Pulse Width fIN_ CMOS PW Duty Cycle DC Input Resistance RIN LVCMOS - DC Coupled (IN3, IN4) Input Frequency Input Voltage 31 fIN_PULSE Standard Mode 0.008 — 2.048 MHz D 1 PPS Mode — 1 — Hz VIL — — 0.3xVDDA V VIH 0.7xVDDA — — V Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 31 Si5383/84 Rev D Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Standard Mode, Pulse Input 50 — — ns 1 PPS Mode, Pulse Input 10 — — us — 20 — kΩ Full operating range. Jitter performance may be reduced. 24.97 — 54.06 MHz Frequency range for best output jitter performance. 48 — 54 MHz VIN_SE Single-ended 365 — 2000 mVpp_se VIN_DIFF Differential 365 — 2500 mVpp_diff Slew rate 2,3 SR Imposed for best jitter performance 400 — — V/μs Input Duty Cycle DC 40 — 60 % Minimum Pulse Width PW Input Resistance RIN XA/XB (if driven from external oscillator) fIN_XAXB XA/XB Frequency Input Voltage Swing Note: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Imposed for jitter performance. 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR. 4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for DC-coupled Pulsed LVCMOS in the Si5383/84 Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard AC-coupled, Single-ended input mode. 32 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 32 Si5383/84 Rev D Data Sheet • Electrical Specifications Table 5.4. Control Input Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit VIL — — 0.3 x VDDA V VIH 0.7 x VDDA — — V Input Capacitance CIN — 1.5 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW FINC, FDEC 100 — — ns Update Rate FUR FINC, FDEC — — 1 MHz VIL — — 0.3 x VDDA V VIH 0.7 x VDDA — — V Input Capacitance CIN — 7 — pF Minimum Reset Pulse Width PW 15 — — μs Si5383/84 Control Input Pins (FINC, FDEC, OEb) Input Voltage Si5383/84 Control Input Pin (SCL, SDA, A1, A0, BLMDb, RSTb) Input Voltage 33 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 33 Si5383/84 Rev D Data Sheet • Electrical Specifications Table 5.5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol fOUT Output Frequency fOUT1Hz Test Condition Min Typ Max Unit Standard input mode 0.0001 — 718.5 MHz DSPLL D in 1 PPS mode 0.0001 — 685 MHz 1 PPS signal only available on Output 5 — 1 — Hz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 718.5 MHz 45 — 55 % Duty Cycle DC Output-Output Skew TSK Outputs on same DSPLL (measured at 712.5 MHz) — — 65 ps TSK_OUT Measured from the positive to negative output pins — 0 50 ps OUT-OUTb Skew Output Voltage Amplitude 1 VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 430 510 VDDO = 3.3 V, or 2.5 V LVPECL 640 750 900 LVDS 1.10 1.20 1.30 LVPECL 1.90 2.00 2.10 VDDO = 2.5 V LVPECL, LVDS 1.10 1.20 1.30 VDDO = 1.8 V subLVDS 0.80 0.90 1.00 tR/tF — 100 150 ps ZO — 100 — Ω 10 kHz sinusoidal noise — –99 — 100 kHz sinusoidal noise — –96 — 500 kHz sinusoidal noise — –94 — 1 MHz sinusoidal noise — –93 — Measured spur from adjacent output 3 — –86 — VOUT VDDO = 3.3 V Common-Mode Voltage 1 Rise and Fall Times (20% to 80%) Differential Output Impedance Power Supply Noise Rejection 2 Output-output Crosstalk 3 34 VCM PSRR XTALK mVpp_se V dBc dBc Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 17, 2021 34 Si5383/84 Rev D Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Output amplitude and common-mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/ EIA-644 maximum. Refer to the Si5383/84 Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common-mode voltages settings are possible. Vpp_diff = 2*Vpp_se 2. Measured for 156.25 MHz carrier frequency. 100mVpp of sinewave noise added to VDDO = 3.3V and noise spur amplitude measured. 3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems, for guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx Vcm Vpp_se Vcm Vpp_se OUTxb Table 5.6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Output Frequency Symbol Test Condition Min Typ Max Unit 0.0001 — 250 MHz Only Available on Output 5 — 1 — Hz fOUT 1 MHz. Consult your CBPro design report for the FPFD frequency of your configuration. 8. Time from first rising edge on 1 pps input until the phase offset between the input and output 1 pps signals is