SPF-3043

Preliminary Product Description Sirenza Microdevices’ SPF-3043 is a high performance 0.25µm pHEMT Gallium Arsenide FET. This 300µm device is ideally biased at 3V,20mA for lowest noise performance and battery powered requirements. At 5V,40mA the device can deliver OIP3 of 32dBm. It provides ideal performance as a driver stage in many commercial and industrial LNA applications. Typical Gain Performance 35 30 25 20 15 3V,20mA 5V,40mA SPF-3043 Low Noise pHEMT GaAs FET Pending Obsolescence Last Time Buy Date: Dec. 19, 2003 Product Features • • • • • • • DC-10 GHz Operation 0.5 dB NFMIN @ 2 GHz 22 dB GMAX @ 2 GHz +32 dBm OIP3 (5V,40mA) +20 dBm P1dB (5V,40mA) Low Current, Low Cost Apps circuits available for key bands Gain, Gmax (dB) Gmax Gain 10 5 0 2 4 6 8 10 Applications • • • • Analog and Digital Wireless Systems 3G, Cellular, PCS Fixed Wireless, Pager Systems Driver Stage for Low Power Applications Test Frequency 0.9 GHz 1.9 GHz 0.9 GHz 1.9 GHz 0.9 GHz 1.9 GHz 1.9 GHz 1.9 GHz 1.9 GHz U nits Min. Typ. 26.5 23.4 0.32 0.54 18.5 20.0 1.05 14.0 26.0 15.0 -1.1 30 90 15.3 28.5 17.0 -0.8 60 150 -10 -10 150 5.5 55 -8 -8 -0.5 120 21.5 1.40 Max. Frequency (GHz) Symbol D evice C haracteristics Test C onditions VDS=5V, IDQ=40mA, 25ºC (unless otherw ise noted) GMAX NFMIN S 21 NF Gai n OIP3 P 1dB VP IDSS gm BVGSO BVGDO Rth V DS IDS Maxi mum Avai lable Gai n Mi ni mum Noi se Fi gure Inserti on Gai n [1] Noi se Fi gure Gai n [2] [2] ZS=ZS*, ZL=ZL* ZS=ΓOPT , ZL=ZL* ZS=ZL= 50Ω LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board VDS= 2V, IDS= 0.1 mA dB dB dB dB dB dB m dB m V mA mS V V ºC /W V mA Output Thi rd Order Intercept Poi nt [2] Output 1dB C ompressi on Poi nt [2] Pi nchoff Voltage [1] [1] Saturated D rai n C urrent Transconductance [1] VDS= 2V, VGS= 0 V VDS= 2V, VGS= 0 V [1] Gate-Source Breakdown Voltage Gate-D rai n Breakdown Voltage Thermal Resi stance Operati ng Voltage Operati ng C urrent [1] IGS= 0.03 mA, drai n open IGD= 0.03 mA, source open juncti on-to-lead drai n-source drai n-source [1] 100% tested - DC parameters tested on-wafer, insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from 500 devices across 5 wafers, 3 wafer lots. The test fixture is an engineering application circuit board (parts are pressed down on the circuit board). The application circuit represents a trade-off between the optimal noise match and input return loss. The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-101772 Rev D 1 Preliminary Pending Obsolescence Junction Temperature Calculation MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the device operating conditions should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = IDS * VDS (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 2) (C) RTH = Thermal Resistance (C/W) SPF-3043 Low Noise pHEMT GaAs FET Absolute Maximum Ratings Parameter Drain Current Forward Gate Current Reverse Gate Current Drain-to-Source Voltage Gate-to-Source Voltage RF Input Power Storage Temperature Range Symbol IDS IGSF IGSR VDS VGS PIN Tstor PDISS TJ Value 60 30 30 7 0 15 -40 TO +150 420 +150 Unit mA µA µA V V dB m C mW C Biasing Details The SPF-3043 is a depletion mode FET and requires a negative gate voltage to achieve pinchoff. As such, power supply sequencing circuitry is strongly recommended to prevent damaging bias transients during turn-on. Active bias circuitry is also recommended to maintain a constant drain current from part-to-part. Power Dissipation Junction Temperature Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1. Typical Performance - Engineering Application Circuits (See App Note AN-043) Freq VDS (GH z ) (V) 0.90 0.90 1.90 1.90 2.14 2.45 5.50 [3] IDQ NF (mA) (dB ) 40 80 40 80 40 40 40 1.00 0.75 1.05 0.95 1.80 1.25 1.30 Gain (dB ) 19.3 23.3 15.3 20.0 15.3 14.9 15.5 P1dB OIP3[3] S11 S22 C onfiguration (dB m) (dB m) (dB ) (dB ) 19.0 19.9 17.0 23.0 18.5 18.5 18.0 29.0 30.0 28.5 32.5 30.0 27.5 29.0 -10 -20 -10 -20 -20 -15 -18 -15 -20 -15 -20 -8 -18 -18 Balanced Si ngle-Ended Balanced C omments 5 5 5 5 5 5 5 Si ngle-Ended 0.85-0.96 GHz, dual-supply 0.8-1.0 GHz, dual-supply 1.8-2.0 GHz, dual-supply 1.8-2.0 GHz, dual-supply Si ngle-Ended 2.1-2.2 GHz, dual-supply Si ngle-Ended 2.4-2.5 GHz, dual-supply Si ngle-Ended 5.1-5.9 GHz, dual-supply POUT= 0 dBm per tone, 1MHz tone spacing Refer to the application note for additional RF data, PCB layouts, BOMs, biasing instructions, and other key issues to be considered. For the latest application note please visit our site at www.sirenza.com. Peak RF Performance Under Optimum Matching Conditions Freq (GHz ) 0.90 1.90 [4] VDS (V) 3 5 3 5 IDQ (mA) 20 40 20 40 NFMIN [4] (dB) 0.25 0.32 0.50 0.54 Gmax (dB) 25.5 26.5 22.4 23.3 P1dB [5] (dBm) 15.5 20.0 15.5 20.0 OIP3 [6] (dBm) 29 32 29 32 ZSOPT S G D Z LOPT ZS=ΓOPT, ZL=ZL*, The input matching circuit losses have been de-emebedded. [5] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max P1dB [6] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max OIP3 Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-101772 Rev D 2 Preliminary Pending Obsolescence SPF-3043 Low Noise pHEMT GaAs FET Typical Performance - De-embedded S-Parameters Gain vs Frequency (3V,20mA) 35 0 Isolation Gain vs Frequency (5V,40mA) 35 0 Isolation Gain, Gmax (dB) Gain, Gmax (dB) 30 25 20 15 10 5 0 2 4 -10 30 25 20 15 10 5 0 2 4 -10 Isolation (dB) Isolation (dB) -20 Gmax Gain -20 Gmax Gain -30 -40 -50 -60 -30 -40 -50 -60 6 8 10 6 8 10 Frequency (GHz) S11,S22 vs Frequency (3V,20mA) 1.0 0.5 2.0 Frequency (GHz) S11,S22 vs Frequency (5V,40mA) 1.0 0.5 2.0 0.2 S11 10 GHz 8 GHz 5.0 0.2 S11 10 GHz 8 GHz 5.0 0.0 0.2 0.5 S22 1.0 2.0 5.0 inf 0.0 0.2 0.5 S22 1.0 2.0 5.0 inf 6 GHz 0.2 1 GHz 2 GHz 4 GHz 3 GHz 6 GHz 5.0 0.2 1 GHz 2 GHz 4 GHz 3 GHz 5.0 0.5 2.0 0.5 2.0 1.0 1.0 Note: S-parameters are de-embedded to the device leads with ZS=ZL=50Ω. The device was mounted on a 0.010” PCB with plated-thru holes close to pins 2 and 4. De-embedded s-parameters can be downloaded from our website (www.sirenza.com). Typical Performance - Noise Parameters Freq (GH z ) 0.90 1.90 [7] VDS (V) 3 5 3 5 IDS (mA) 20 40 20 40 N FMIN [7] (dB ) 0.25 0.32 0.50 0.54 Γ OPT Mag ∠ Ang 0.79 ∠ 12 0.75 ∠ 12 0.62 ∠ 34 0.62 ∠ 33 rN 0.22 0.25 0.19 0.20 Gmax (dB ) 25.5 26.5 22.4 23.3 ZS=ΓOPT, ZL=ZL*, NFMIN is a noise parameter for which the input matching circuit losses have been de-emebedded. The noise parameters were measured using a Maury Microwave Automated Tuner System. The device was mounted on a 0.010” PCB with platedthru holes close to pins 2 and 4. 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-101772 Rev D 3 Preliminary Pending Obsolescence Caution: ESD sensitive Appropriate precautions in handling, packaging and testing devices must be observed. SPF-3043 Low Noise pHEMT GaAs FET Pin Description Pin # 1 2 3 4 Part Number Ordering Information Part Number SPF-3043 Reel Siz e 7" Devices/Reel 3000 Function Gate Source Drain Source RF Input / Gate Bias Description Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. RF Output / Drain Bias Same as Pin 2 Part Symbolization The part will be symbolized with the “F3” designator and a dot signifying pin 1 on the top surface of the package. Pin Designation 4 3 Recommended PCB Layout SOT-343 Package 1 2 Plated Thru Holes (0.020" DIA) Ground Plane Use multiple plated-through vias holes located close to the package pins to ensure a good RF ground connection to a continuous groundplane on the backside of the board. D e e Package Dimensions L HE C L F3 C L E SYMBOL E MIN 1.15 1.85 1.80 0.80 0.80 0.00 0.10 MAX 1.35 2.25 2.40 1.10 1.00 0.10 0.40 Q1 b1 C D HE A A2 A1 b NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70. 5. DIE IS FACING UP FOR MOLD AND FACING DOWN FOR TRIM/FORM. ie :REVERSE TRIM/FORM. 6. PACKAGE SURFACE TO BE MIRROR FINISH. Q1 e b b1 c L 0.65 BSC 0.25 0.55 0.10 0.10 0.40 0.70 0.18 0.30 A2 A1 A 522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com EDS-101772 Rev D 4