CXA1166K

CXA1166K 8-bit 250 MSPS Flash A/D Converter Description The CXA1166K is an 8-bit ultrahigh-speed flash A/D converter IC capable of digitizing analog signals at a maximum rate of 250 MSPS. The digital I/O level of this A/D converter is compatible with the ECL 100K/10KH/10K. This IC is pin-compatible with the conventional CXA1076AK/CXA1176K/CXA1176AK, and can replace the conventional models easily. Compared with the conventional models, the CXA1166K has a greatly improved performance because of the new circuit design and carefully considered layout. Features • Differential linearity error: ±0.5 LSB or less • Integral linearity error: ±0.5 LSB or less • Built-in integral linearity compensation circuit • Ultrahigh-speed operation with maximum conversion rate of 250 MSPS • Low input capacitance: 18pF • Wide analog input bandwidth: 250MHz (full-scale input, standard) • Single power supply: –5.2V • Low power consumption: 1.4W (Typ.) • Low error rate • Good temperature characteristics • Capable of driving 50Ω loads 68 pin LCC (Ceramic) Structure Bipolar silicon monolithic IC Applications • Digital oscilloscopes • Other apparatus requiring ultrahigh-speed A/D conversion Pin Configuration (Top View) Pins without name are NC pins (not connected internally). AGND VIN1 VIN1 AGND VRM AGND VIN2 VIN2 AGND AVEE AGND AVEE VRT VRTS AVEE AVEE LINV OR OR D0 D0 D1 D1 DVEE 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 AGND AVEE VRB VRBS AVEE AVEE CLK CLK MINV D7 D7 D6 D6 DVEE Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. D2 D2 D3 D3 DGND2 DGND2 DGND1 D4 D4 D5 D5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 –1– E90406-ST CXA1166K Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVEE, DVEE • Analog input voltage VIN • Reference input voltage VRT, VRB, VRM | VRT – VRB | • Digital input voltage MINV, LINV, CLK, CLK | CLK – CLK | • VRM pin input current IVRM • Digital output current ID0 to ID7, IOR, ID0 to ID7, IOR • Storage temperature Tstg Operating Conditions • Supply voltage Min. –5.5 –0.05 –0.05 –0.1 –2.2 VRB –20 –7 to +0.5 –2.7 to +0.5 –2.7 to +0.5 2.5 –4 to +0.5 2.7 –3 to +3 –30 to 0 –65 to +150 Typ. –5.2 0 0 0 –2.0 Max. –4.95 0.05 0.05 0.1 –1.8 VRT 100 V V V V V V mA mA °C Unit V V V V V °C • Reference input voltage • Analog input voltage • Operating temperature AVEE, DVEE AVEE – DVEE AGND – DGND VRT VRB VIN Tc –2– CXA1166K Block Diagram MINV 33 r1 VRT 64 r/2 r2 VRTS 65 r r r 0 1 2 • • • 63 64 r 65 • • • 126 127 128 129 • • • 191 192 r r r4 VRBS 39 r5 VRB 40 r r/2 193 • • • 254 255 31 D7 (MSB) 32 D7 29 D6 30 D6 21 D5 22 D5 2 OR 3 OR Comparator VIN1 54 r 55 r r r3 VRM 52 r r ENCODE LOGIC OUTPUT 19 D4 20 D4 14 D3 15 D3 12 D2 13 D2 6 D1 7 D1 4 D0 (LSB) 5 D0 r r VIN2 49 50 CLK 35 CLK 34 CLOCK DRIVER 1 LINV –3– CXA1166K Pin Description Pin No. Symbol I/O Standard voltage level DGND1 18 Equivalent circuit Description Polarity selection other than MSB and overrange. (Refer to the table of input voltage vs. Digital output) Low level is maintained with left open. –1.3V 1 LINV I ECL LINV or 1 r r r 33 MINV 33 MINV I ECL DVEE 8 28 r Polarity selection for MSB (Refer to the table of input voltage vs. Digital output) Low level is maintained with left open. Reference voltage (Top) (0V typ.) Reference voltage sense (Top) 64 VRT I 0V VRT 64 r2 VRTS 65 r1 r⁄2 65 VRTS O 0V r3 r 52 VRM I VRB/2 VRM 25 r To Comparator Reference voltage mid-point. Can be used for linearity compensation. Reference voltage sense (Bottom) Reference voltage (Bottom) 39 VRBS O –2V r4 VRBS 39 r r ⁄2 r5 VRB 40 43, 48, 51, 53, 56, 61 AGND 40 VRB I –2V VIN1 54 55 VIN1 I VRTS to VRBS 54 55 49 50 VIN2 To Comp 0 to 127 128 to 255 49 50 Analog input. Pins 49, 50 and Pins 54, 55 should be connected externally. VIN2 DGND1 35 CLK I ECL 18 r r CLK 35 CLK 34 r r CLK input 34 CLK I ECL DVEE 8 28 r r Complementary CLK input. ECL threshold potential (–1.3V) is maintained with left open. The complementary input is recommended for stable operation at high speed though the operation only with the CLK input is possible when the CLK input is left open. –4– CXA1166K Pin No. 31 32 29 30 21 22 19 20 14 15 12 13 6 7 4 5 Symbol D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 I/O O O O O O Standard voltage level Equivalent circuit Description MSB and complementary MSB output DGND2 16 17 Di Di D1 to D6: Output D1 to D6: Complementary output ECL O O DVEE 8 28 O LSB and complementary LSB output Overrange output; Low level for overrange. Overrange complementary output; High level for overrange. 2 3 OR OR O 37, 38, 42, 58, AVEE∗ 62, 66, 67 43, 48, 51, 53, AGND∗ 56, 61 8 28 18 16 17 DVEE∗ AGND –5.2V 61 48 53 DGND1 43 51 56 18 DGND2 16 17 Analog supply. Internally connected with DVEE (resistance: 4 to 6Ω). 0V Internal Analog Circuit Internal Digital Circuit Di Di Analog ground. Separated from DGND. Digital supply. Internally connected with AVEE (resistance: 4 to 6Ω). Digital ground Digital ground for output drive No connected. It is recommended to connect these pins to AGND. –5.2V 4 to 6Ω 42 37 58 8 28 DVEE DGND1 DGND2∗ 0V 0V 62 38 66 67 AVEE 41, 44, 45, 46, 47, 57, NC 59, 60, 63 9, 10, 11, 23, 24, 25, NC 26, 27, 36, 68 — — No connected. It is recommended to connect these pins to DGND. ∗ For stable operation, all of these pins must be connected on the corresponding PCB pattern. –5– CXA1166K Electrical Characteristics Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Input bias current Reference inputs Reference resistance Residual resistance∗1 r1 r2 r3 r4 r5 Digital inputs Logic High level Logic Low level Logic High current Logic Low current Input capacitance Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Output delay Clock High pulse width Clock Low pulse width Digital output Logic High level Logic Low level Output rise time Output fall time Dynamic characteristics Input bandwidth SNR EIL EDL CIN RIN IIN RREF r1 r2 r3 r4 r5 VIH VIL IIH IIL Symbol (AVEE = DVEE = –5.2V, VRT, VRTS = 0V, VRB, VRBS = –2V, Ta = 25°C) Condition Min. Typ. 8 ±0.5 ±0.5 VIN = –1V + 0.07Vrms VIN = –1V VIN = –1V 18 120 450 125 0.6 500 2.0 500 0.6 182 2.0 700 5.0 700 2.0 Max. Unit bits LSB LSB pF kΩ µA Ω Ω Ω Ω Ω Ω V V µA µA pF MSPS ps ns ns ns ns V V ns ns MHz dB dB 10–9 TPS∗2 TPS∗2 50 20 83 0.1 300 0.5 300 0.1 –1.13 VIH = –0.8V VIL = –1.6V 0 –50 4 –1.50 70 50 Fc Taj Tds Tdo TPW1 TPW0 VOH VOL Tr Tf 250 RL = 50Ω to –2V 0.4 1.8 1.8 1.8 –1.00 0.6 0.6 200 44 30 –1.60 1.5 1.5 9 1.4 2.5 2.4 3.2 }T PW1 + TPW0 = 4.0ns RL = 50Ω to –2V RL = 50Ω to –2V RL = 50Ω to –2V RL = 50Ω to –2V VIN=2Vp-p Input = 1kHz, FS Clock = 250MHz Input = 62.499MHz, FS Clock = 250MHz Input = 49.999MHz, FS Error > 16LSB Clock = 200MHz Input = 62.499MHz, FS Error > 16LSB Clock = 250MHz NTSC 40IRE mod. ramp, Fc = 250MSPS SNR { { 46 35 Error rate { { DG DP IEE Pd 10–8 10–6 Differential gain error Differential phase error Power supply Supply current Power consumption∗3 ∗1 See Block Diagram. ∗2 TPS: Times Per Sample 2 ∗3 Pd = IEE • VEE + (VRT – VRB) RREF } 1.0 0.5 –360 –270 1.4 % deg mA W 1.9 –6– CXA1166K Input Voltage vs. Digital Output VIN∗ Step 0 0 1 1 1 MINV LINV OR D7 0V 1 1 D0 OR D7 0 1 1 0 1 D0 OR D7 0 1 1 1 0 D0 OR D7 0 1 1 0 0 D0 0 0 0 …… 0 0 0 0 0 …… 0 0 0 0 0 …… 0 1 : : 0 1 1 …… 1 1 1 0 0 …… 0 0 : : 1 1 1 …… 1 0 1 1 1 …… 1 1 1 1 1 …… 1 1 1 0 0 …… 0 0 1 0 0 …… 0 0 1 0 0 …… 0 1 : : 1 1 1 …… 1 1 0 0 0 …… 0 0 : : 0 1 1 …… 1 0 0 1 1 …… 1 1 0 1 1 …… 1 1 0 1 1 …… 1 1 0 1 1 …… 1 1 0 1 1 …… 1 0 : : 0 0 0 …… 0 0 1 1 1 …… 1 1 : : 1 0 0 …… 0 1 1 0 0 …… 0 0 1 0 0 …… 0 0 1 1 1 …… 1 1 1 1 1 …… 1 1 1 1 1 …… 1 0 : : 1 0 0 …… 0 0 0 1 1 …… 1 1 : : 0 0 0 …… 0 1 0 0 0 …… 0 0 0 0 0 …… 0 0 –1V 127 128 254 255 –2V 1 1 : : 1 1 1 1 1 : : 1 1 1 1 1 : : 1 1 1 1 1 : : 1 1 1 ∗ VRT = VRTS = 0V, VRM = –1V or Open, VRB = VRBS = –2V Timing Diagram Tds N Analog input N+1 N+2 Tpw1 CLK CLK Tpw0 Digital output Td N–1 20% 80% N 80% N+1 20% Tf Tr –7– CXA1166K Electrical Characteristics Measurement Circuit Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit +V S2 S1:ON when AB S1 –V AB Comparator VIN DUT CXA1166K 8 A8 to A1 A0 “0” DVM Controller B8 to B1 B0 “1 ” 000•••00 to 111•••10 8 Buffer Sampling Delay Measurement circuit Aperture Jitter Measurement circuit 60MHz Amp OSC1 φ:Variable VIN fr CLK OSC2 ECL Buffer 60MHz 1024 samples CXA1166K 8 Logic Analizer Aperture Jitter Measurement Method 0V VIN –1V –2V CLK ∆υ ∆t VIN 129 128 127 126 125 t σ (LSB) CLK Sampling timing fluctuation ( = aperture jitter) When the distribution of the output codes is σ (unit: LSB) If the maximum slew rate point is sampled with the clock signal having the same frequency as that of the analog input signal, Aperture jitter (Taj) is defined as follows: Taj = σ/ 256 ∆υ = σ/ ( × 2πf ) ∆t 2 –8– CXA1166K Error Rate Measurement Circuit Signal Source Vin 8 ECL Latch + ECL Latch A B Comparator A