CXD1175AP

CXD1175AM/AP 8-bit 20MSPS Video A/D Converter (CMOS) Description The CXD1175A is an 8-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low consumption at a maximum conversion speed of 20MSPS minimum, 35MSPS typical. Features • Resolution: 8 bit ± 1/2LSB (DL) • Maximum sampling frequency: 20MSPS • Low power consumption: 60mW (at 20MSPS typ.) (reference current excluded) • Built-in sampling and hold circuit • Built-in reference voltage self-bias circuit • 3-state TTL compatible output • Power supply: 5V single • Low input capacitance: 11pF • Reference impedance: 300Ω (typ.) Applications TV, VCR digital systems and a wide range of fields where high speed A/D conversion is required. Structure Silicon gate CMOS monolithic IC CXD1175AM 24 pin SOP (Plastic) CXD1175AP 24 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 7 V • Supply voltage VDD • Reference voltage VRT,VRB VDD + 0.5 to Vss – 0.5V • Input voltage VIN VDD + 0.5 to Vss – 0.5V (Analog) • Input voltage VI VDD + 0.5 to Vss – 0.5V (Digital) • Output voltage VO (Digital) • Storage temperature Tstg VDD + 0.5 to Vss – 0.5V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVss 4.75 to 5.25 V DVDD, DVss | DVss – AVss | 0 to 100 mV • Reference input voltage VRB 0 and above V VRT 2.8 and below V • Analog input VIN 1.8Vp-p above • Clock pulse width TPW1, TPW0 23ns (min) to 1.1µs (max) • Operating ambient temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89321F78-PS CXD1175AM/AP Block Diagram and Pin Configuration OE 1 Reference voltage DVSS 2 D0 (LSB) 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 (MSB) 10 DVDD 11 CLK 12 Clock generator Upper data latches Upper encoder (4 bit) Upper comparators with S/H (4 bit) Lower encoder (4 bit) Lower comparators with S/H (4 bit) Lower data latches Lower comparators with S/H (4 bit) 24 DVSS 23 VRB 22 VRBS 21 AVSS 20 AVSS 19 VIN 18 AVDD 17 VRT 16 VRTS 15 AVDD 14 AVDD 13 DVDD Lower encoder (4 bit) –2– CXD1175AM/AP Pin Description and Equivalent Circuits No. Symbol Equivalent circuit DVDD Description 1 OE 1 When OE = Low, Data is output. When OE = High, D0 to D7 pins turn to High impedance. DVSS 2, 24 DVSS Digital ground 3 to 10 D0 to D7 Di D0 (LSB) to D7 (MSB) output 11, 13 DVDD DVDD Digital +5V 12 CLK 12 Clock input DVSS AVDD 16 VRTS 16 AVDD Shorted with VRT generates, +2.6V. 17 VRT 17 23 Reference voltage (Top) 23 VRB AVSS Reference voltage (Bottom) 14, 15, 18 AVDD AVDD Analog +5V 19 VIN 19 Analog input AVSS 20, 21 AVSS AVSS Analog GND 22 VRBS 22 Shorted with VRB generates +0.6V. –3– CXD1175AM/AP Digital output Compatibility between analog input voltage and the digital output code is indicated in the chart below. Input signal voltage VRT : : : : VRB Digital output code MSB LSB 11111111 : 10000000 01111111 : 00000000 Step 0 : 127 128 : 255 TPW1 TPW0 Clock Amalog input N N+1 N+2 N–1 N+3 N+4 N+1 Data output N–3 N–2 N Td = 18ns : Point for analog signal sampling. Timing Chart 1 tr = 4.5ns tf = 4.5ns 90% 5V OE input 2.5V 10% tPLZ tPZL 0V VOH Output 1 10% tPHZ tPZH 90% Output 2 1.3V VOL (≠DVSS) VOH (≠DVDD) 1.3V VOL Timing Chart 2 –4– CXD1175AM/AP Electrical Characteristics Analog characteristics Item Symbol (Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Conditions VDD = 4.75 to 5.25V Ta = –40 to +85°C VIN = 0.5 to 2.5V fIN = 1kHz ramp Envelope Potential difference to VRT Potential difference to VRB End point NTSC 40 IRE mod ramp Fc = 14.3MSPS –10 0 Min. Typ. Max. Unit Conversion speed Fc 0.5 20 MSPS Analog input band width (–1dB) Offset voltage∗1 Integral non-linearity error BW EOT EOB EL 18 –35 +15 +0.5 ±0.3 1.0 0.5 30 4 –60 +45 +1.3 ±0.5 MHz mV LSB % deg ps ns Differential non-linearity error ED Differential gain error Differential phase error Aperture jitter Sampling delay DG DP taj tsd ∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from “11111111” to “11111110”. –5– CXD1175AM/AP DC characteristics Item Supply current Reference pin current Analog input capacitance Reference resistance (VRT to VRB) Self-bias I Self-bias II Digital input voltage Symbol IDD IREF CIN RREF VRB1 VRT1 – VRB1 VRT2 VIH VIL IIH IIL IOH Digital output current IOL IOZH IOZL (Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Conditions Fc = 20MSPS NTSC ramp wave input 4.5 VIN = 1.5V + 0.07Vrms 230 Shorts VRB and VRBS Shorts VRT and VRTS VRB = AGND Shorts VRT and VRTS VDD = 4.75 to 5.25V Ta = –40 to +85°C VIH = VDD VDD = max OE = VSS VDD = min OE = VDD VDD = max VIL = 0V VOH = VDD – 0.5V VOL = 0.4V VOH = VDD VOL = 0V –1.1 3.7 16 16 0.60 1.96 2.25 3.5 1.0 5 5 Min. Typ. 12 6.6 11 300 0.64 2.09 2.39 450 0.68 2.21 2.53 Max. 17 8.7 Unit mA mA pF Ω V V V Digital input current µA mA µA Timing Item Output data delay Tri-state output enable time Tri-state output disable time (Fc = 20MSPS, VDD = 4.75 to 5.25V, VRB = 0.5V, VRT = 2.5V, Ta = –40 to +85°C) Symbol TDL Conditions With TTL 1 gate and 10pF load RL = 1kΩ, CL = 20pF OE = 5V → 0V RL = 1kΩ, CL = 20pF OE = 0V → 5V 3 7 Min. Typ. 18 7 15 Max. 30 13 26 Unit ns ns ns tPZH tPZL tPHZ tPLZ –6– CXD1175AM/AP Electrical Characteristics Measurement Circuit Integral non-linearity error Differential non-linearity error Offset voltage +V } 3-state output measurement circuit measurement circuit Measurement point DVDD S2 S1: ON IF A < B S2: ON IF B > A S1 To output pin RL –V AB COMPARATOR A8 B8 to to A1 B1 A0 B0 CL 8 BUFFER Note) CL includes the capacitance of the probe and others. RL VIN 8 DUT CXD1175A "0" CLK (20MHz) DVM "1" 8 CONTROLLER 000 · · · 00 to 111 · · · 10 Maximum operational speed Differential gain error Differential phase error } measurement circuit 2.5V Fc – 1kHz ERROR RATE CX20202A-1 S.G. 0.5V H.P.F 1 2 COUNTER 1 AMP 2 100 VIN CXD 1175A 8 TTL ECL 8 620 –5.2V 10bit D/A NTSC IAE SIGNAL SOURCE 40 IRE MODULATION BURST 2.5V CLK VECTOR SCOPE 0 –40 0.5V SYNC 620 TTL –5.2V D.G D.P. S.G. (CW) FC ECL Digital output current measurement circuit VDD VRT VIN VRB CLK OE GND VOL VDD VRT VIN VRB CLK OE GND VOH 2.5V 0.5V IOL 2.5V 0.5V + – IOH + – –7– CXD1175AM/AP Timing Chart 3 Vi (1) Vi (2) Vi (3) Vi (4) Analog input External clock Upper comparators block S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4) Upper data MD (0) MD (1) MD (2) MD (3) Lower reference voltage RV (0) RV (1) RV (2) RV (3) Lower comparators A block S (1) H (1) C (1) S (3) H (3) C (3) Lower data A LD (–1) LD (1) Lower comparators B block H (0) C (0) S (2) H (2) C (2) S (4) H (4) Lower data B LD (–2) LD (0) LD (2) Digital output Out (–2) Out (–1) Out (0) Out (1) Operation (See Block Diagram and Timing Chart) 1. The CXD1175AM/AP is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom). –8– CXD1175AM/AP 2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the respective GND’s. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6V and VRB = 0.6V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns. 6. OE pin By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained. 7. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. –9– CXD1175AM/AP Application Circuit +5V R11 1k R12 1k IC1 µPC254 Q4 +5V CLOCK IN HC04 CLK R13 500 +12V Q5 IC2 µPC254 +5V +12V R8 100 C9 47µ 13 C10 0.1µ C12 0.1µ 14 15 16 C8 ∗ 17 18 19 CXD1175AM/AP 12 11 10 9 8 7 6 5 4 3 2 1 D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) C6 47µ C5 0.1µ R3 Q2 500 C2 10µ Q1 R6 500 Q3 R7 500 V IN R1 120 C1 470µ C3 47µ R2 180 C4 0.1µ R4 1k R5 2k R10 75 R9 5k C13 10p C11 0.1µ C7 47µ 20 21 22 23 24 –12V –12V –12V ∗ : Ceramic Chip Condenser 0.1µF : Analog GND : Digital GND +5V Note) It is necessary that AVDD and DVDD pins the common source of power supply. The gain of analog input signal can be variable by adjustment of value of R3. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD1175AM/AP 8-bit 20MSPS ADC and DAC Evaluation Board The CXD1175AP/CXA1106P PCB is evaluation PCB for the 8-bit high speed and low power consumption CMOS A/D converter CXD1175AP and the 8-bit high speed bipolar D/A converter CXD1106P. This PCB features a high speed and low power consumption CMOS A/D converter, analog input buffer, clock buffer, latch and high speed bipolar D/A converter designed to fully enhance the performance of A/D and D/A converters. Block Diagram V OUT V REF CXD1175AP V IN ANALOG INPUT BUFFER/DRIVER 8 CLOCK BUFFER ANALOG CIRCUIT MOUNT PORTION OSC SW DATA LATCH DIGITAL CIRCUIT MOUNT PORTION ANALOG CIRCUIT MOUNT PORTION CXA1106P 8 Unnecessary during self-bias usage Characteristics • Resolution • Maximum conversion rate • Digital input level • Supply voltage Supply voltage Item +5V –5V Analog input AC input voltage Item Gain (VIN = 2Vp-p input) Offset voltage Clock input TTL compatible Pulse width TCW1 TCW0 Min. GND +5V –5V CLOCK 8bit 20MHz TTL level ±5.0V Typ. Max. 150 20 Unit mA Min. 0.5 0 Typ. Max. 2 5 Unit V 25ns (min.) 25ns (min.) – 11 – CXD1175AM/AP Analog Output (CXA1106) Item Analog output Min. 0.9 Typ. 1.0 (RL > 10kΩ) Max. 1.1 Unit V Output Format (CXD1175A) The table shows the output format of A/D converter. Input signal voltage VRT : : : : VRB Timing Chart Analog input Step 0 : 127 128 : 255 Digital output code MSB LSB 11 10 01 00 11 : 00 11 : 00 0 0 00 0 1 0 1 00 11 1 1 11 External clock Tpw1 AD clock Tdc Tpw0 tPD (AD) AD output tDD Latch output DA input ts DA clock th DA output tPD (DA) Item Clock high time Clock low time Clock delay Data delay AD Data delay (latch) Set up time Hold time Data delay DA Symbol TPW1 TPW0 Tdc Min. 25 25 Typ. Max. Unit ns ns 24 18 30 17 10 2 11 – 12 – ns ns ns ns ns ns tPD (AD) tDD tS th tPD (DA) Peripheral Circuit Board (Top View) DVSS DVDD AVSS C8 0.1µ Vief 1 24 23 0.1µ AVSS CLK 4 5 6 7 13 4 3 2 1 0.1µ CLK 9 10 AVDD 11 13 12 14 15 16 17 18 19 20 21 22 23 24 C14 0.1µ CLK 12 13 14 15 16 DVDD AVDD AVDD Q3 VRT R7 75 AVDD VIN AVSS AVSS VRBS VRB DVSS C7 0.1 C13 47µ/10 VRTS 7 6 5 4 3 2 1 Clear OSC OUT 0.1µ VSS 8 9 10 11 12 13 14 22µ/16 DVDD OSC SWITCH EXT/INT DVSS R11 75 7 6 5 4 3 2 1 VDD 14 1 EXTERNAL CLOCK INPUT (RIN = 75Ω) 0.1 8 VSS 7 8 74S174 (Latch) VSS Clear 14 15 VDD 14 NC 13 NC NC 11 D6 12 16 12 5 11 6 10 7 9 74S174 (Latch) 8 VSS 22 AVSS 2 3 AVdl VDD 10µ/16 VDD VSS C10 0.1 NC 8 CLK 9 10 (MSB) D7 Q5 VR5 5k AVtl Vsel OUTPUT GAIN ADJUST C7 0.1 DAC OUTPUT VRT ADJUST AVDD R9 510 CXA1106 (DAC) CXD1175A (ADC) DVDD 11 D7 (MSB) 10 D6 9 D5 8 D4 7 D3 6 D2 5 D1 4 D0 (LSB) 3 DVSS 2 OE 1 VR3 2k VR4 2k 21 NC D0 (LSB) 20 D1 19 D2 18 D3 17 D4 16 D5 15 VRB ADJUST Q4 R4 510 R10 510 Q1 to Q5 (C2785) C12 47µ/10 C2785 CXD1175AM/AP E C B –5V +5V GND AVDD DVDD 74S04 or 74HC04 (INV Buffer) – 13 – C5 0.1 C6 0.1 R8 2.2k AVSS INPUT BIAS ADJUST VIDEO INPUT INPUT GAIN ADJUST R5 390 Q2 C1 470µ/6.3 C2 22µ /16 Q1 (RIN = 75Ω) VR1 100 R1 51 R2 120 R3 680 R6 2.2k VR2 10k AVSS C11 47µ/10 CXD1175AM/AP List of Parts resistor R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 VR1 VR2 VR3 VR4 VR5 51Ω 120Ω 680Ω 510Ω 390Ω 2.2kΩ 75Ω 2.2kΩ 510Ω 510Ω 75Ω 100Ω 10kΩ 2kΩ 2kΩ 5kΩ transistor Q1 Q2 Q3 Q4 Q5 IC IC1 IC2 IC3 oscillator OSC others connector BNC071 SW AT1D2M3 2SC2785 2SC2785 2SC2785 2SC2785 2SC2785 74S174 74S174 74S04 capacitor C1 470µF/6.3V (chemical) C2 22µF/16V (chemical) C3 0.01µF C4 10µF/16V (tamtalate) C5 0.1µF C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C11 47µF/10V (chemical) C12 47µF/10V (chemical) C13 47µF/10V (chemical) C14 0.1µF Method of Adjustment 1. Vgain (VR1) Gain adjustment of the analog input. 2. Voffset (VR2) Offset adjustment of the analog input. 3. Vref (VR3, VR4) Adjustment of the A/D converter reference voltage. VRB is adjusted at VR3, and VRT at VR4. Reference voltage is given with self-bias for PCB shipment. 4. Analog output gain (VR5) Full-scale voltage of the D/A converter output is adjusted. – 14 – CXD1175AM/AP Points on the PCB Pattern Layout 1. Layout so that digital current does not flow to analog GND (part 1). (See Component Side on page 19 for part 1.) 2. Capacitor C6 (between AVSS and AVDD) and capacitor C14 (between DVSS and DVDD) are important factors to enhance the CXD1175A performance. Those capacitors should feature good high frequency characteristics over 0.1µF (ceramic capacitor). Layout as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) have a common voltage and a supply source. The DVSS of A/D converter (part 2) location as close to the voltage source is possible will give even better results. That is, a layout where the A/D converter is close to the voltage source is recommended. (See Component Side on page 19 for part 2.) 4. AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13) are provided in the CXD1175A, and a common voltage source should be used for them as for part 3. (See the paragraph for Latch Up Prevention.) (See Soldering Side on page 19 for part 3.) 5. The A/D converter samples analog signals at the falling edge of clock. Accordingly, clocks fed to the A/D converter should not be affected by jitter. 6. In this PCB, to evaluate A/D and D/A converters independently, an independent layout has been adopted for the analog GND of A/D and D/A converters, from the voltage generation source. For the user’s actual PCB even a common source poses no problems. For the CXA1106, as analog signals are output with the supply voltage as reference, take care not to let noise interfere with the analog VDD of D/A converter. – 15 – CXD1175AM/AP Notes on Operation 1. Reference voltage The self-bias function where VRT = 2.6V and VRB = 0.6V is available by shorting VRT and VRTS, VRB and VRBS in the CXD1175A. At the PCB, either self-bias or external reference voltage can be selected according to the way the jumper wire is connected. For shipment, the reference voltage is provided by the self-bias. Also, when reference voltage is to be provided from the exterior, adjust the dynamic range (VRT – VRB) to 1.8Vp-p or over. 2. Clock input There are two modes for the PCB clock input. 1) Through an external signal generator (external clock) 2) Using a crystal oscillator (internal clock) These two modes can be selected with a switch on the PCB. They are given from the external clock for shipment. 3. Peripheral through hole There is a number of through holes at the analog input, output and LOGIC areas. Those are used when additional circuits are to be mounted on the PCB circuit. 4 The two latch ICs (74S174) on the circuit diagram are not absolutely necessary for the A/D and D/A converter evaluation. That is, when the A/D converter output data is directly input to D/A converter input, normal operation is maintained. However, as A/D converter output data is hardly ever subject to D/A conversion without the digital signal processing, the PCB has been fitted with the 74S174 to show a layout example for digital signal processing IC. 5. Analog input buffer & driver block is designed to handle conventional video band signals. Accordingly, for tests involving frequencies higher than that, methods shown in the figure below are recommended. R7 75Ω 19 V IN 50Ω D1175A S.G. High frequency input measurement circuit – 16 – CXD1175AM/AP Latch Up Prevention The CXD1175A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 14 15 AVDD 18 11 13 DVDD C14 DIGITAL IC +5V +5V C6 CXD1175A AVSS 20 AVSS DVSS 21 DVSS 2 24 b. When analog and digital supplies are from a common source (i) DVDD 14 +5V C6 15 AVDD 18 11 13 DVDD C14 DIGITAL IC CXD1175A AVSS 20 21 AVSS DVSS DVSS 2 24 (ii) DVDD 14 15 AVDD 18 11 13 DVDD C14 DIGITAL IC +5V C6 CXD1175A AVSS AVSS 20 21 DVSS DVSS 2 24 – 17 – CXD1175AM/AP 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 14 15 AVDD +5V +5V C6 CXD1175A 18 11 13 DVDD DIGITAL IC AVSS AVSS 20 21 DVSS DVSS 2 24 b. When analog and digital supplies are from common source (i) DVDD AVDD 14 15 AVDD +5V C6 CXD1175A 18 11 13 DVDD DIGITAL IC AVSS AVSS 20 21 DVSS DVSS 2 24 (ii) DVDD AVDD 14 15 18 AVDD +5V CXD1175A 11 13 DVDD DIGITAL IC AVSS AVSS 20 21 DVSS DVSS 2 24 – 18 – CXD1175AM/AP Silk Side Component side 1 Soldering side – 19 – CXD1175AM/AP Package Outline CXD1175AM Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 24 13 + 0.4 1.85 – 0.15 0.15 + 0.3 5.3 – 0.1 7.9 ± 0.4 + 0.2 0.1 – 0.05 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 ± 0.12 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 ∗SOP024-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING COPPER ALLOY / 42ALLOY 0.3g CXD1175AP 24PIN DIP(PLASTIC) + 0.1 05 0.25 – 0. + 0.4 30.2 – 0.1 24 13 + 0.3 8.5 – 0.1 10.16 0° to 15° 1 2.54 12 0.5 MIN + 0.4 3.7 – 0.1 0.5 ± 0.1 1.2 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 3.0 MIN PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-24P-01 DIP024-P-0400 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 2.0g – 20 – 0.5 ± 0.2 1 12 6.9