SSEPAA5-02S

SSEPAA5-02S Low Capacitance ESD Protection Array Features ESD Protect for 2 high-speed I/O channels Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20μs) For High Speed Data Interfaces immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ±8kV contact discharge). Circuit Diagram 5 5V operating voltage Low capacitance : 2pF typical Fast turn-on and Low clamping voltage Array of surge rated diodes with internal equivalent TVS diode Small package saves board space Solid-state silicon-avalanche and active circuit triggering technology 3 2 4 Applications USB2.0 Power and Data lines protection Notebook and PC Computers Monitors and Flat Panel Displays IEEE 1394 Firewire Ports Video Graphics Cards SIM ports Description SSEPAA5-02S is a high performance design which includes surge rated diode arrays to protect high speed data interfaces. The SSEPAA5-02S has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. SSEPAA5-02S is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. SSEPAA5-02S may be used to meet the ESD 11/08/2007 Rev.1.00 Pin Configuration VDD 5 I/O 2 4 1 NC 2 GND 3 I/O 1 JEDEC SOT23-5L (Top View) www.SiliconStandard.com 1 SSEPAA5-02S SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER Peak Pulse Current (tp =8/20μs) Operating Supply Voltage (VDD-GND) ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) Lead Soldering Temperature Operating Temperature Storage Temperature DC Voltage at any I/O pin TSOL TOP TSTO VIO PARAMETER IPP VDC VESD RATING 13 6 24 16 260 (10 sec.) -55 to +125 -55 to +150 (GND – 0.5) to (VDD + 0.5) o o o UNITS A V kV C C C V ELECTRICAL CHARACTERISTICS PARAMETER Reverse Stand-Off Voltage Reverse Leakage Current Channel Leakage Current Reverse Breakdown Voltage Forward Voltage Clamping Voltage ESD Holding Voltage SYMBOL VRWM ILeak ICH_Leak VBV VF VCL Vhold CONDITIONS Pin 5 to pin 2, T=25 C VRWM = 5V, T=25 oC, Pin 5 to pin 2 VPin 5 = 5V, VPin 2 = 0V, T=25 oC IBV = 1mA, T=25 oC Pin 5 to Pin 2 IF = 15mA, T=25 oC Pin2 to Pin 5 IPP=5A, tp=8/20μs, T=25 oC Any Channel pin to Ground IEC 61000-4-2 +6kV, T=25 oC, Contact mode, Any Channel pin to Ground Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC, Any Channel pin to Ground Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Between Channel pins Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground www.SiliconStandard.com o MIN TYP MAX 5 5 1 UNITS V μA μA V V V V 6.1 0.7 7.8 13 9 1 8.5 Channel Input Capacitance Channel to Channel Input Capacitance Variation of Channel Input Capacitance CIN 2 3 pF CCROSS 0.08 0.15 pF △CIN 0.03 0.06 pF 11/08/2007 Rev.1.00 2 SSEPAA5-02S Typical Characteristics Pow er Derating Curve 110 100 % of Rated Pow er or IPP 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 Clamping Voltage (V) Clamping Voltage vs. Peak Pulse Current 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 90 I/O pin to GND pin Waveform Parameters: tr=8μs td=20μs 4 5 6 7 8 9 10 11 12 13 Ambient Temperature, TA (oC) Forw ard Voltage vs. Forw ard Current 4.0 3.5 Peak pulse Current (A) Typical Variation of CIN vs. VIN 4.0 3.5 Input Capacitance (pF) 3.0 2.5 2.0 1.5 1.0 0.5 13 VDD = 5V, GND = 0V, f = 1MHz, T=25 oC, Forward Voltage (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 I/O pin to GND pin Waveform Parameters: tr=8μs td=20μs 5 6 7 8 9 10 11 12 0.0 0 1 2 3 4 5 Peak pulse Current (A) Input Voltage (V) Insertion Loss S21 15 10 3.0 Typical Variation of CIN vs. Temp Input Capacitance (pF) 2.5 S21 (dB) VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz, 5 0 -5 2.0 1.5 -10 -15 1.0 20 40 Temperature (oC) 60 80 100 120 1e+6 1e+7 Frequency (Hz) 1e+8 1e+9 STOP 1000MHz START 0.3MHz Transmission Line Pulsing (TLP) Current (A) 20 18 16 14 12 10 8 6 4 2 0 0 Transmission Line Pulsing (TLP) Measurement V_pulse Pulse from a transmission line 100ns + TLP _V DUT TLP_I I/O to GND 2 4 6 8 10 12 14 Transmission Line Pulsing (TLP) Voltage (V) 11/08/2007 Rev.1.00 www.SiliconStandard.com 3 SSEPAA5-02S Applications Information A. Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. In Fig. 1, the diodes D1 and D2 are general used to protect data line from ESD stress pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the positive pulse ESD current (IESD1) will pass through the ESD current path1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30A in 1ns. Here d(IESD1)/dt can be approximated by ΔIESD1/Δt, or 30/(1x10-9). So just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed into the VDD rail may potentially damage any components that are attached to that rail. Moreover, it is common for the forward voltage drop of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. Of course, the discrete diode is also possible to be destroyed due to its power dissipation capability is exceeded. The SSEPAA5-02S has an integrated power-rail ESD clamped circuit between VDD and GND rails. It can successfully overcome previous disadvantages. During an ESD event, the positive ESD pulse current (IESD2) will be directed through the integrated power-rail ESD clamped circuit to GND rail (ESD current path2). The clamping voltage VCL on the data line is small and protected IC will not be damaged because power-rail ESD clamped circuit offer a low impedance path to discharge ESD pulse current. power -r ai l ESD cl amp i n g ci r cu i t SSEPAA5-02S L2 I ESD1 VDD r ail I ESD2 D1 Vp + _ L1 dat a line VESD + Pr o te cte d IC D2 V CL _ GND r ail ESD current path 1 (I ESD1) ESD current path 2 (I ESD2) Fig. 1 11/08/2007 Rev.1.00 Application of positive ESD pulse between data line and GND rail. www.SiliconStandard.com 4 SSEPAA5-02S B. Device Connection The SSEPAA5-02S is designed to protect two data lines and power rails from transient over-voltage (such as ESD stress pulse). The device connection of SSEPAA5-02S is shown in the Fig. 2. In Fig. 2, the two protected data lines are connected to the ESD protection pins (pin3 and pin4) of SSEPAA5-02S. The ground pin (pin2) of SSEPAA5-02S is a negative reference pin. This pin should be directly connected to the GND rail of PCB (Printed Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. In addition, the power pin (pin 5) of SSEPAA5-02S is a positive reference pin. This pin should directly connect to the VDD rail of PCB. When pin 5 of SSEPAA5-02S is connected to the VDD rail, the leakage current of ESD protection pin of SSEPAA5-02S becomes very small. Because the pin 5 of SSEPAA5-02S is directly connected to VDD rail, the VDD rail also can be protected by the power-rail ESD clamped circuit (not shown) of SSEPAA5-02S. SSEPAA5-02S can provide protection for 2 I/O signal lines simultaneously. If the number of I/O signal lines is less than 2, the unused I/O pins can be simply left as NC pins. In some cases, systems are not allowed to be reset or restart after the ESD stress directly applying at the I/O-port connector. Under this situation, in order to enhance the sustainable ESD Level, a 0.1μF chip capacitor can be added between the VDD and GND rails. The place of this chip capacitor should be as close as possible to the SSEPAA5-02S. VDD rail SSEPAA5-02S NC GND rail 1 5 *Optional 0 .1 μ F Ch ip Cap . 2 3 4 To I/O-p o r t Co n n e cto r I/O 1 I/O 1 data line I/O 2 To Pr o te cte d IC data line I/O 2 Fig. 2 Data lines and power rails connection of SSEPAA5-02S. 11/08/2007 Rev.1.00 www.SiliconStandard.com 5 SSEPAA5-02S C. Applications 1. Universal Serial Bus (USB) ESD Protection The SSEPAA5-02S can be used to protect the USB port on the monitors, computers, peripherals or portable systems. The ESD protection scheme for single USB ports is shown in Fig. 3. In the Fig.3,the voltage bus (VBUS) of USB ports are connected to the power pin (pin 5) of SSEPAA5-02S. Each data line (D+/D-) of USB port is connected to the ESD protection pin of SSEPAA5-02S. When ESD voltage pulse appears on the data line, the ESD pulse current will be conducted by SSEPAA5-02S away from the USB controller chip. In addition, the ESD pulse current also can be conducted by SSEPAA5-02S away from the USB controller chip when the ESD voltage pulse appears on the voltage bus (VBUS) of USB port. Therefore, the data lines (D+/D-) and voltage bus (VBUS) of two USB ports are complementally protected with an SSEPAA5-02S. V BUS S S E P AA 5-02S NC 1 2 5 USB Con tr o lle r 3 4 V BUS D+ CT CT RT RT USB Por t D_ GND GND Fig. 3 ESD Protection scheme for single USB ports by using SSEPAA5-02S. 11/08/2007 Rev.1.00 www.SiliconStandard.com 6 SSEPAA5-02S 2. Audio Interface ESD Protection For the audio interface, the Right/Left channels should be protected from the ESD stress. The SSEPAA5-02S can be used for the audio interface ESD protection. The ESD protection scheme for audio interface is shown in the Fig. 4. In the Fig. 4, the Right and Left channels of audio connector are connected to ESD protection pins (such as pin 3 and pin 4) of SSEPAA5-02S. For the power pin (pin 5) of SSEPAA5-02S, it should directly connect to the VDD power supply. As well, for the ground pin (pin 2) of SSEPAA5-02S, it should directly connect to the Ground plate. When ESD voltage pulse appears on the Right/Left channel of audio connector, the ESD pulse current will be discharged by SSEPAA5-02S. Therefore, the Right/Left channels of audio chip are complementally protected with an SSEPAA5-02S. NC 1 2 3 5 VDD SS EPAA 5-02S Au dio Ch ip 4 GND Au dio Conne ctor Right Channe l Le f t Channe l Fig. 4 ESD Protection scheme for audio interface by using SSEPAA5-02S. 11/08/2007 Rev.1.00 www.SiliconStandard.com 7 SSEPAA5-02S Mechanical Details SOT23-5L PACKAGE DIAGRAMS TOP VIEW PACKAGE DIMENSIONS SIDE VIEW END VIEW 11/08/2007 Rev.1.00 www.SiliconStandard.com 8 SSEPAA5-02S LAND LAYOUT C A Dimensions Index A F E D Millimeter 0.60 1.10 0.95 2.50 1.40 3.60 Inches 0.024 0.043 0.037 0.098 0.055 0.141 B C D E F B C Notes: This LAND LAYOUT is for reference purposes only. Please consult your manufacturing partners to ensure your company’s PCB design guidelines are met. MARKING CODE 5 4 Part Number SSEPAA5-02S Marking Code 101XY 101XY 1 2 3 101 = Device Code X = Date Code Y = Control Code 11/08/2007 Rev.1.00 www.SiliconStandard.com 9 SSEPAA5-02S Revision History Revision Revision 2006/8/28 Revision 2007/02/05 Original Release. 1. Change the clamping cell symbol for easy understanding. 2. Change the expression of CIN from @ VIN=0V to @ VIN=2.5V. 3. Add the TLP characterization. 4. Add the ESD holding voltage characterization under IEC 61000-4-2 +6kV contact mode at I/O channel to GND. 5. Update the clamping voltage to (typ=7.8V, max=9V). 6. Correct typos. Update the spec of VF & VCL. Update the Marking Code from 101X to 101XY. Modification Description Revision 2007/02/27 Revision 2007/05/15 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/08/2007 Rev.1.00 www.SiliconStandard.com 10