74VHC541

74VHC541 OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) s s s s s s s s s s HIGH SPEED: tPD = 3.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74VHC541MTR 74VHC541TTR DESCRIPTION The 74VHC541 is an advanced high-speed CMOS OCTAL BUS BUFFER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. The 3 STATE control gate operates as two input AND such that if either G1 or G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the 74VHC541 offers a pinout having inputs and outputs on opposite sides of the package. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 1: Pin Connection And IEC Logic Symbols November 2004 Rev. 4 1/12 74VHC541 Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1, 19 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 10 20 SYMBOL G1, G2 A1 to A8 Y1 to Y8 NAME AND FUNCTION Output Enable Inputs Data Inputs Data Outputs GND VCC Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUT G1 H X L L X : Don’t care Z : High impedance OUTPUT An X X H L Yn Z Z H L G2 X H L L Table 4: Absolute Maximum Ratings Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Unit V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 5: Recommended Operating Conditions Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 ± 0.3V) (VCC = 5.0 ± 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V °C ns/V 1) VIN from 30% to 70% of VCC 2/12 74VHC541 Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 5.5 0 to 5.5 5.5 IO=-50 µA IO=-50 µA IO=-50 µA IO=-4 mA IO=-8 mA IO=50 µA IO=50 µA IO=50 µA IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 ±0.25 ± 0.1 4 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 ± 2.5 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.55 0.55 ± 2.5 ±1 40 µA µA µA V V Max. -55 to 125°C Min. 1.5 0.7VCC 0.5 0.3VCC V V Max. Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH II ICC 3/12 74VHC541 Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 3.3(*) 3.3 5.0 tPZL tPZH Output Enable Time (*) (**) Value TA = 25°C Min. Typ. 5.0 7.5 3.5 5.0 Max. 7.0 10.5 5.0 7.0 10.5 14.0 7.2 9.2 15.4 8.8 1.5 1.0 -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 8.5 12.0 6.0 8.0 12.5 16.0 8.5 10.5 17.5 10.0 1.5 1.0 -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 8.5 12.0 6.0 8.0 12.5 16.0 8.5 10.5 17.5 10.0 1.5 1.0 ns ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 50 50 50 50 RL = 1KΩ RL = 1KΩ RL = 1KΩ RL = 1KΩ RL = 1KΩ RL = 1KΩ tPLH tPHL Propagation Delay Time 5.0(**) 3.3(*) 3.3(*) 5.0(**) 5.0(**) tPLZ tPHZ tOSLH tOSHL Output Disable Time Output to Output Skew time (note 1) 3.3 5.0 (*) (**) 6.8 9.3 4.7 6.2 11.2 6.0 3.3(*) 5.0(**) (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| Table 8: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C Min. CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Typ. 7 9 18 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Circuit) 4/12 74VHC541 Table 9: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 5.0 TA = 25°C Min. Typ. 0.6 -0.8 CL = 50 pF 3.5 -0.6 Max. 0.8 V Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 V 5.0 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. Figure 3: Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open VCC GND 5/12 74VHC541 Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) Figure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle) 6/12 74VHC541 SO-20 MECHANICAL DATA DIM. A A1 B C D E e H h L k ddd 10.00 0.25 0.4 0° mm. MIN. 2.35 0.1 0.33 0.23 12.60 7.4 1.27 10.65 0.75 1.27 8° 0.100 0.394 0.010 0.016 0° TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 8° 0.004 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0016022D 7/12 74VHC541 TSSOP20 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0087225C 8/12 74VHC541 Tape & Reel SO-20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 13.2 3.1 3.9 11.9 12.8 20.2 60 30.4 11 13.4 3.3 4.1 12.1 0.425 0.520 0.122 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 9/12 74VHC541 Tape & Reel TSSOP20 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.8 6.9 1.7 3.9 11.9 12.8 20.2 60 22.4 7 7.1 1.9 4.1 12.1 0.268 0.272 0.067 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.276 0.280 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 10/12 74VHC541 Table 10: Revision History Date 12-Nov-2004 Revision 4 Description of Changes Order Codes Revision - pag. 1. 11/12 74VHC541 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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