EMIF08-LCD04M16
Datasheet
8-line L-C IPAD EMI filter and ESD protection in micro QFN package
Features
•
High cut off frequency low-pass filter: FC = 400 MHz at -6 dB
•
High efficiency in EMI filtering: better than -35 dB from 900 MHz to 2 GHz
•
Very low PCB space consuming with plastic micro-package 3.3 x 1.35 mm
•
Very thin package: 0.55 mm max.
•
High efficiency in ESD (IEC 61000-4-2 level 4)
•
High reliability offered by monolithic integration
•
High reduction of parasitic elements through integration and μQFN packaging
•
ECOPACK2 compliant
Complies with the following standards
•
IEC 61000-4-2, level 4 on external pins:
–
±15 kV (air discharge)
–
±8 kV (contact discharge)
Applications
Where EMI filtering in ESD sensitive equipment is required:
•
Mobile POS
•
Human machine interface (HMI): STEVAL-PLC001V1
•
Home automation HMI
Product status
EMIF08-LCD04M16
Description
The EMIF08-LCD04M16 is an 8-line inductor capacitor (LC) EMI filter designed to
suppress EMI/RFI noise in all systems subjected to electromagnetic interferences
requiring a large bandwidth.
This filter includes an ESD protection circuitry, which prevents damage to the
application when subjected to ESD surges up 15 kV contact discharge.
DS6256 - Rev 3 - September 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
EMIF08-LCD04M16
Characteristics
1
Characteristics
Figure 1. Pin configuration
Pin 1
Output 1 Pin 16
Input 1
Output 2 Pin 15
Pin 2 Input 2
Pin 3
Input 3
Output 3 Pin 14
Pin 4
Input 4
Output 4 Pin 13
Pin 5
Input 5
Output 5 Pin 12
Pin 6
Input 6
Output 6 Pin 11
Pin 7
Input 7
Output 7 Pin 10
Pin 8
Input 8
Output 8 Pin 9
Exposed pad (GND)
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol
VPP
Tj
DS6256 - Rev 3
Parameter
Value
Unit
ESD IEC 61000-4-2, contact discharge:
±15
kV
Maximum junction temperature
125
°C
Top
Operating temperature range
- 40 to + 85
°C
Tstg
Storage temperature range
- 55 to + 150
°C
page 2/11
EMIF08-LCD04M16
Characteristics
Figure 2. Electrical characteristics (definitions)
I
IF
Symbol
VBR
IRM
VRM
VCL
Rd
IPP
RI/O
Cline
Parameter
Breakdown voltage
Leakage current at VRM
Stand-off voltage
Clamping voltage
VBR
VCL
VF
VRM
V
IRM
IR
Dynamic resistance
Peak pulse current
Series resistance between Input and Output
Input capacitance per line
IPP
Table 2. Electrical characteristics (Tamb = 25 °C)
Symbol
VBR
IR = 1 mA
IRM
VRM = 3 V per line
L
Inductance
R
Parasitic resistance of the inductance
FC
50 Ω source and 50 Ω load termination at -6 dB
Cline
DS6256 - Rev 3
Test conditions
VR = 3 V dc, VOSC = 30 mV, F = 1 MHz
Min.
Typ.
Max.
6
V
100
12
9
12.5
18
nA
nH
20
400
17
Unit
Ω
MHz
19
pF
page 3/11
EMIF08-LCD04M16
Characteristics (curves)
1.1
Characteristics (curves)
Figure 3. S21 attenuation measurements
Figure 4. Analog cross talk measurements
Figure 5. ESD response to IEC 61000-4-2 (+15 kV air
discharge)
Figure 6. ESD response to IEC 61000-4-2 (-15 kV air
discharge)
Figure 7. Line capacitance versus applied voltage
DS6256 - Rev 3
page 4/11
EMIF08-LCD04M16
Package information
2
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
2.1
Micro QFN-16L 3.5x1.35 mm package information
•
•
Epoxy meets UL94, V0
Lead-free package
Figure 8. Micro QFN-16L 3.5x1.35 mm package outline
DS6256 - Rev 3
page 5/11
EMIF08-LCD04M16
Micro QFN-16L 3.5x1.35 mm package information
Table 3. Micro QFN-16L 3.5x1.35 mm mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.45
0.50
0.55
0.018
0.020
0.022
A1
0.00
0.02
0.05
0.000
0.0008
0.002
b
0.15
0.20
0.25
0.006
0.008
0.10
D
D2
3.30
2.65
E
E2
2.80
0.25
0.40
0.104
k
0.20
L
0.15
0.110
0.114
0.053
0.50
0.010
0.40
0.016
0.020
0.016
0.008
0.25
Figure 9. Footprint (dimensions in mm)
DS6256 - Rev 3
2.90
1.35
e
Note:
0.13
0.35
0.006
0.010
0.014
Figure 10. Marking
Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking
be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
page 6/11
EMIF08-LCD04M16
Recommendation on PCB assembly
3
Recommendation on PCB assembly
3.1
Stencil opening design
1.
2.
General recommendation on stencil opening design
a.
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
General design rule
a.
Stencil thickness (T) = 75 ~ 125 μm
b.
c.
3.
Aspect ratio = W
T ≥ 1.5
Aspect area =
L × W
≥ 0.66
2T L + W
Reference design
a.
Stencil opening thickness: 100 μm
b.
Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c.
Stencil opening for leads: Opening to footprint ratio is 90%
Figure 11. Stencil opening dimensions
L
T
W
Figure 12. Recommended stencil window position
DS6256 - Rev 3
page 7/11
EMIF08-LCD04M16
Solder paste
3.2
Solder paste
1.
2.
3.
4.
3.3
Placement
1.
2.
3.
4.
5.
6.
3.4
Manual positioning is not recommended.
It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
Standard tolerance of ±0.05 mm is recommended.
3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste
and cause solder joints to short. Too low placement force can lead to insufficient contact between package
and solder paste that could cause open solder joints or badly centered packages.
To improve the package placement accuracy, a bottom side optical control should be performed with a high
resolution tool.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder
paste printing, pick and place and reflow soldering by using optimized tools.
PCB design preference
1.
2.
3.5
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
“No clean” solder paste is recommended.
Offers a high tack force to resist component movement during high speed.
Solder paste with fine particles: powder particle size is 20-45 μm.
To control the solder paste amount, the closed via is recommended instead of open vias.
The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is
recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
Reflow profile
Figure 13. ST ECOPACK recommended soldering reflow profile for PCB mounting
250
240-245 °C
Temperature (°C)
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
Note:
DS6256 - Rev 3
30
60
90
120
150
180
210
240
270
300
Minimize air convection currents in the reflow oven to avoid component movement.
page 8/11
EMIF08-LCD04M16
Ordering information
4
Ordering information
Figure 14. Ordering information scheme
Table 4. Ordering information
Part number
Marking
Package
Weight
Base qty.
Delivery mode
EMIF08-LCD04M16
JA(1)
Micro QFN
6.74 mg
3000
Tape and reel
1. The marking can be rotated by 90° to differentiate assembly location
DS6256 - Rev 3
page 9/11
EMIF08-LCD04M16
Revision history
Table 5. Document revision history
DS6256 - Rev 3
Date
Revision
Changes
20-May-2009
1
Initial release.
10-Nov-2009
2
Updated Features on page 1. Added Figure 2 on page 2.
14-Sep-2022
3
Added Figure 1. Pin configuration.
Minor text changes.
page 10/11
EMIF08-LCD04M16
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© 2022 STMicroelectronics – All rights reserved
DS6256 - Rev 3
page 11/11
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