EMIF08-1005M16

EMIF08-1005M16 Datasheet 8-line IPAD™ low capacitance EMI filter and ESD protection in QFN package Features • • 1 • • • • • • QFN 16L 3.3 mm x 1.5 mm (bottom view) Inpu t 1 100 Ω C = 22.5 pF Output 1 C = 22.5 pF Typical line capacitance = 45 pF typ .@ 0 V • EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering: – Greater than -34 dB attenuation at frequencies from 900 MHz to 1.8 GHz Cut-off frequency: 100 MHz Very low PCB space consuming: 3.3 mm x 1.5 mm Very thin package: 0.6 mm max. High reliability offered by monolithic integration RoHS package Complies with following standards: – IEC 61000-4-2 level 4 input and output pins 15 kV (air discharge) 8 kV (contact discharge) – MIL STD 883G - Method 3015-7 Class 3B (all pins) UL94 V0 Applications Product status EMIF08-1005M16 Where EMI filtering in ESD sensitive equipment is required: • LCD and camera for mobile phones • Computers and printers • Communication systems • MCU boards Description The EMIF08-1005M16 is an 8-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes an ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input or output pins. DS4994 - Rev 3 - February 2018 For further information contact your local STMicroelectronics sales office. www.st.com EMIF08-1005M16 Characteristics 1 Characteristics Figure 1. Pin configuration Pin 1 Output 1 Pin 16 Input 1 Output 2 Pin 15 Pin 2 Input 2 Pin 3 Input 3 Output 3 Pin 14 Pin 4 Input 4 Output 4 Pin 13 Pin 5 Input 5 Output 5 Pin 12 Pin 6 Input 6 Output 6 Pin 11 Pin 7 Input 7 Output 7 Pin 10 Pin 8 Input 8 Output 8 Pin 9 Exposed pad (GND) Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP Tj Tstg DS4994 - Rev 3 Parameter Value Unit ESD IEC 61000-4-2, air discharge 15 ESD IEC 61000-4-2 contact discharge 15 Maximum junction temperature range -40 to +125 °C Storage temperature range - 55 to + 150 °C kV page 2/13 EMIF08-1005M16 Characteristics Figure 2. Electrical characteristics (definitions) I IF Symbol VBR IRM Parameter Breakdown voltage Leakage current at VRM VRM VCL Stand-off voltage Rd Dynamic resistance IPP RI/O Cline Series resistance between Input and Output Input capacitance per line Clamping voltage VBR VCL VF VRM V IRM IR Peak pulse current IPP Table 2. Electrical characteristics (Tamb = 25 °C) Symbol DS4994 - Rev 3 Test conditions Min. Typ. Max. Unit VBR IR = 1 mA 6 8 10 v VF IF = 10 mA 0.5 1.0 1.5 v IRM VRM = 3 V per line 200 nA RI/O Tolerance ± 10% 90 100 110 Ω Cline VLINE = 0 V dc, VOSC = 30 mV, F = 1 MHz 38 45 52 pF page 3/13 EMIF08-1005M16 Characteristics (curves) 1.1 Characteristics (curves) Figure 3. S21 attenuation measurement Figure 4. Analog cross talk measurements 0.00 0.00 dB dB - 10.00 - 30.00 - 20.00 - 60.00 - 30.00 - 90.00 - 120.00 - 40.00 1.0M 3.0M 10.0M 3 0.0M 100.0M 300.0M f/Hz 1.0G 3.0G Figure 5. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (Vin) and on one output (Vout) DS4994 - Rev 3 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G f/Hz Figure 6. ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input (Vin) and on one output (Vout) page 4/13 EMIF08-1005M16 Characteristics (curves) Figure 7. Line capacitance versus reverse voltage applied 50.00 CLINE (pF) 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 VLINE (V) 5.00 0.00 0 DS4994 - Rev 3 1 2 3 4 5 page 5/13 EMIF08-1005M16 Package information 2 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 2.1 QFN 3.3x1.5-16L package information Figure 8. QFN 3.3x1.5-16L package outline D INDEX AREA (D/2 x E/2) E A1 A e b INDEX AREA (D/2 x E/2) EXPOSED PAD PIN # 1 ID L E2 K D2 Table 3. QFN 3.3x1.5-16L package mechanical data Dimensions Ref. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.50 0.55 0.60 0.020 0.022 0.024 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 3.20 3.30 3.40 0.126 0.130 0.134 D2 2.45 2.60 2.70 0.096 0.102 0.106 E 1.40 1.50 1.60 0.055 0.059 0.063 E2 0.20 0.35 0.45 0.008 0.014 0.018 e 0.40 K 0.20 L 0.20 DS4994 - Rev 3 0.016 0.008 0.30 0.40 0.008 0.012 0.016 page 6/13 EMIF08-1005M16 QFN 3.3x1.5-16L package information Figure 9. QFN 3.3x1.5-16L footprint (dimensions in mm) 0.40 Figure 10. Marking Dot : Pin 1 Identification XX = Marking WW= DataCode (week) Y=Data code(Year) P=Assembly plant 0.20 0.60 0.275 0.35 XX WW YP 2.60 Figure 11. Tape and reel outline Dot id enti fy in g Pin A1 loc atio n All dimensions in mm 5 .5 ± 0.1 12.00 ± 0.3 3.70 ± 0.1 0.80 ± 0.1 Ø 1.55 ± 0.05 4.00 ± 0.1 1.75 ± 0.1 2.00 ± 0.1 XX WW YP XX WW YP 1.70 ± 0.1 XX WW YP XX WW YP XX WW YP XX WW YP 4.00 ± 0.1 User dir ecti on of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. DS4994 - Rev 3 page 7/13 EMIF08-1005M16 Recommendation on PCB assembly 3 Recommendation on PCB assembly 3.1 Stencil opening design 1. 2. General recommendation on stencil opening design a. Stencil opening dimensions: L (Length), W (Width), T (Thickness). General design rule a. Stencil thickness (T) = 75 ~ 125 μm b. L  ×  W Aspect area = 2T L  + W ≥ 0.66 Reference design a. Stencil opening thickness: 100 μm b. Stencil opening for leads: Opening to footprint ratio is 90%. c. 3. W Aspect ratio = T ≥ 1.5 Figure 12. Recommended stencil window position L T DS4994 - Rev 3 W page 8/13 EMIF08-1005M16 Solder paste Figure 13. Recommended stencil opening dimensions 5µm 5µm 570 µ m 600 µ m 15 µm 0.40 0.20 0.60 190 µm 15 µm 0.275 0.35 200 µm 2600 µm 250 µ m 50 µm 350 µm 1820 µm Footprint 50 µm 390 µm 3.2 5. 6. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. “No clean” solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 μm. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of ±0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. 2. DS4994 - Rev 3 Footprint Placement 1. 2. 3. 4. 3.4 390 µm Stencil window Solder paste 1. 2. 3. 4. 3.3 2.60 To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away. page 9/13 EMIF08-1005M16 Reflow profile 3.5 Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting 250 240-245 °C Temperature (°C) -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: DS4994 - Rev 3 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. page 10/13 EMIF08-1005M16 Ordering information 4 Ordering information Table 4. Ordering information Part number Marking Package Weight Base qty. Delivery mode EMIF08-1005M16 H8(1) QFN 7.9 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to differentiate assembly location DS4994 - Rev 3 page 11/13 EMIF08-1005M16 Revision history Table 5. Document revision history DS4994 - Rev 3 Date Version 24-Oct-2006 1 04-Feb-2008 2 08-Feb-2018 3 Changes Initial release. Reformatted to current standards. Updated ECOPACK statement. Added Section 4: Recommendation on PCB assembly. Updated Table 1. Absolute maximum ratings (Tamb = 25 °C). page 12/13 EMIF08-1005M16 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS4994 - Rev 3 page 13/13