IPS4260LTR

IPS4260L Datasheet Quad low-side intelligent power switch Features • • • HTS S OP20 8 V to 50 V operating voltage range Four independent protected channels VCC undervoltage lock-out • High speed operation (tr, tf < 1 μs) • • • • • Programmable load current limitation level by external resistor Typical operating load current: 0.5 A (per channel) / 2 A (one channel) Thermally independent junction overtemperature protections Programmable non-dissipative short-circuit protection (cut-off) by external resistor Open load (off-state) and short-to-ground activated by external pull-down resistors Fast demagnetization of inductive loads with integrated catch diodes clamping turn-off transients Ground and VCC wire break protection • VCC overvoltage protection • • • • • Common open load diagnostic Common thermal shutdown and overload diagnostic Per channel thermal shutdown diagnostic Designed to meet IEC 61131-2 Miniaturized HTSSOP20 package • • Product status link IPS4260L Product label Application • • • • Programmable logic control Industrial PC peripheral input/output Numerical control machines General low-side switch applications Description The IPS4260L is a monolithic high speed (FSW up to 250 kHz) device, which can drive four independent capacitive, resistive or inductive loads with one side connected to supply voltage. The channels can be parallelized to reduce power dissipation. When connected to Vcc rail, four integrated catch diodes clamp the turn-off transients generated by inductive loads even with huge inductance; combined with proper external TVS connected to VCC or to GND the IC allows fast decay, too. Each channel is protected against overload or short circuit event: the intervention level can be set by an external resistor on ILIM pin . Built-in thermal shutdown protects the chip against overtemperature even in case of short-circuit. If enabled, the integrated cut-off protection features a non-dissipative protection in case of overload; it limits both the output average current value and, consequently, the device overheating. Cut-off delay/restart can be programmed by external resistors on CoD pin; it can be disabled by shorting CoD to GND. DS12305 - Rev 5 - July 2021 For further information contact your local STMicroelectronics sales office. www.st.com IPS4260L Two common diagnostic open drains pins (OL, for open load and FLT for cut-off and thermal shutdown) together with the four open drain on each INx pin (cut-off and thermal shutdown) feature an extensive diagnostic of the chip. DS12305 - Rev 5 page 2/29 IPS4260L Block diagram 1 Block diagram Figure 1. Block diagram VCC VZ UVLO VCLAMP IN1 LOAD1 IN2 LOAD2 GATE DRIVERS IN3 IN4 LOAD3 LOGIC INTERFACE LOAD4 OL CURRENT LIMITATION CUT-OFF FLT THERMAL JUNCTION ILIM ICOD OPEN LOAD SGND DS12305 - Rev 5 RCOD RILIM PGND page 3/29 IPS4260L Pin description 2 Pin description Figure 2. Pin connection (top view) PGND 1 20 PGND PGND 2 19 PGND VZ 3 18 VZ IN1 4 17 LOAD1 IN2 5 16 LOAD2 IN3 6 15 LOAD3 IN4 7 14 LOAD4 SGND 8 13 VCC 9 12 ILIM 10 11 CoD Table 1. Pin configuration Number 1, 2, 19, 20 Function PGND Integrated power switch ground Type Supply 3, 18 VZ Load clamp voltage pins. Pins 3 and 18 must be shorted on the application board and then connected directly to the supply rail, or by an external Zener or TVS diode to the supply rail or to PGND (see Section 2.3 VZ) 4 IN1 Channel 1 input / cut-off and thermal shutdown diagnostic Input/output open drain 5 IN2 Channel 2 input / cut-off and thermal shutdown diagnostic Input/output open drain 6 IN3 Channel 3 input / cut-off and thermal shutdown diagnostic Input/output open drain 7 IN4 Channel 4 input / cut-off and thermal shutdown diagnostic Input/output open drain 8, exposed pad SGND Logic interface block ground Output Supply 9 OL Cumulative power stage open load or short ground common diagnostic Output open drain 10 FLT Cut-off and thermal shutdown pin. Common diagnostic pin both for thermal shutdown and cut-off Output open drain 11 CoD Programmable cut-off intervention delay during overcurrent operation. It cannot be left floating: connect to PCB SGND ground plane to disable the cut-off function or connect a resistor between CoD and PCB ground plane to set the delay (see Section 6.3 Current limitation and cut-off) Input 12 ILIM Limitation current adjustment. It cannot be left floating: connect a resistor between ILIM and SGND to set the current limit threshold (see Section 6.3 Current limitation and cut-off) Input 13 VCC Supply voltage. Connect to the supply rail 14 DS12305 - Rev 5 Name LOAD4 Power stage, channel 4 Supply Input page 4/29 IPS4260L VCC Number 2.1 Name Function Type 15 LOAD3 Power stage, channel 3 Input 16 LOAD2 Power stage, channel 2 Input 17 LOAD1 Power stage, channel 1 Input VCC IC supply voltage. This pin has to be connected to the supply rail of the application. 2.2 PGND, SGND PGND stands for power ground and it is internally connected to the source of the integrated switches. SGND stands for signal ground and it is the reference level for the logic interface. SGND and PGND pins must be shorted on the application board. In order to reduce as much as possible the switching noises from PGND to SGND, the application board has to be designed with two different ground planes for SGND and PGND. The two ground planes have to be shorted by a dedicated net. 2.3 VZ These two pins (corresponding to the cathodes of the clamp diodes) must be shorted together on the application and connected directly to supply rail or, alternatively, connected by a Zener or TVS diode to supply rail or PGND. Connecting VZ pins directly to the supply rail implies that the inductive loads are demagnetized without fast decay option: in fact the VLOADx (voltage on LOADx pin) is forced to the forward voltage of the integrated clamp diodes. The connection by a Zener or TVS allows to drive loads requiring fast current decay (fast demagnetization). For the proper selection of the external Zener or TVS, please refer to Section 7.1 Fast current decay with TVS between VZ and supply rail and Section 7.2 Fast current decay with TVS between VZ and PGND Note: Leaving VZ pins floating, the integrated output voltage clamp is activated and the fast current decay capability is limited by the heatsink capability of the IC. See EAS in Table 2. Absolute maximum ratings. 2.4 IN1, IN2, IN3, IN4 These pins drive the power stage on pins LOAD1, LOAD2, LOAD3 and LOAD4. Besides an internal weak pull-down resistor (see Iinx in Table 7. Logic inputs), each IN1, IN2, IN3, IN4, is internally wired to an open drain transistor, used for diagnostic purposes, and must be driven through a series resistor. The open drain transistor is turned-on in case of thermal shutdown or cut-off protection of the relative channel (see Section 6.2 Overtemperature and Section 6.3 Current limitation and cut-off ). 2.5 LOAD1, LOAD2, LOAD3, LOAD4 Power stage load connection pins: integrated power transistor are in low-side configuration, so the load has to be connected between LOADx pin and supply rail. The power stage channels can be paralleled. 2.6 Open load in off-state OL pin is used for diagnostic purpose and it is internally wired to an open drain transistor. If the open load feature is enabled (see Section 6.4 Open load in off-state) the open drain transistor is activated when LOADx is in off state and the open load threshold (VOLoff) is triggered (see Table 8. Protection and diagnostic ). 2.7 FLT This pin is used for diagnostic purpose and it is internally wired to an open drain transistor. The open drain transistor is turned on in case of junction thermal shutdown or during the cut-off protection. DS12305 - Rev 5 page 5/29 IPS4260L ILIM 2.8 ILIM This pin cannot be left floating and can be used to program the limitation current value through an external resistor (RILIM) see Table 8. Protection and diagnostic. The resistor RILIM has to be connected between ILIM and SGND pins. When the IPS4260L ICs are used in the same application, their ILIM pins cannot be wired together: each IC must be connected to its own resistor ( see Section 6.3 Current limitation and cut-off ) 2.9 CoD This pin cannot be left floating and can be used to program the cut-off delay time tcoff (see Table 8. Protection and diagnostic) through an external resistor (RCoD). The resistor RCoD has to be connected between CoD and SGND pins. The cut-off function can be completely disabled by shorting CoD pin to SGND: in this condition the power stage channel remains ON in limitation condition, supplying the current to the load until the input is forced LOW or the thermal shutdown threshold is triggered (see Section 6.3 Current limitation and cut-off ) DS12305 - Rev 5 page 6/29 IPS4260L Absolute maximum ratings 3 Absolute maximum ratings Table 2. Absolute maximum ratings Note: Symbol Parameter Value Unit VCC Supply voltage -0.3 to 55 V VZ Internal clamp diode supply -0.3 to 55 V VLOADx Power stage (LOADx channel) voltage -0.3 to VDEMAG V VINx INx pin voltage -0.3 to 5.5 V IINx INx pin current -10 to +10 mA VCOD, VILIM CoD and ILIM pin voltage 5.5 V ICOD, IILIM CoD and ILIM pin current -1/+5 mA VOD Open drain fault pins (FLT and OL) voltage -0.3 to 5.5 V IOD Open drain fault pins (FLT and OL) current -10/10 mA ICC Maximum DC reverse current (from GND to VCC) -250 mA ILOADHx Power stage (LOADx channel) current Internally limited A -ILOADHx Reverse current on LOADx channel 5 A EAS Single pulse avalanche energy per channel not simultaneously @TAMB= 125 °C, ILOAD = 500 mA, VZ pins floating 0.9 J PTOT Power dissipation at TC = 25 °C Internally limited W TSTG Storage temperature range -55 to 150 °C TJ Junction temperature -40 to 150 °C Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 3. Thermal data Symbol Termal resistance RTH(JA) Junction to ambient RTH(J-C) Junction to case Conditions 2s2p (4L) board Natural convection(1) Cold plate (infinite headsink like)(2) Value Unit 43 °C/W 3 °C/W 1. JESD51-7. 2. JESD51-12.01 DS12305 - Rev 5 page 7/29 IPS4260L Electrical characteristics 4 Electrical characteristics (8 V < VCC < 50 V; -40 °C < TJ < 125 °C, unless otherwise specified) Table 4. Supply Symbol Parameter Test conditions Min. Typ. Max. Unit VUVON 50 V VCC Operating voltage range VUVON Undervoltage on threshold VCC increasing 7 8 V VUVOFF Undervoltage off threshold VCC decreasing 6.5 7.5 V VUVH Undervoltage hysteresis Supply current in off-state IS Supply current in on-state 0.2 0.5 VCC = 24 V(all INx OFF) 1 VCC = 50 V(all INx OFF) 1.2 VCC = 24 V all INx ON, LOADx open load [x = 1..4] 2 VCC = 50 V all INx ON, LOADx open load [x = 1..4] 2.4 V 1.6 mA mA 3 Table 5. Output stage Symbol Parameter Test conditions Min. RLOAD = 48 Ω, VCC = 24 V @ TJ = 25 °C RDS(on) On-state resistance VOUT(OFF) Off-state power stage voltage IOUT(OFF) Off-state power stage current VFCD Catch diodes forward voltage I forward = 500uA IRRM Catch diodes reverse current Vrrm= 55V Typ. 260 RLOAD = 48 Ω, VCC = 24 V @ TJ = 125 °C VIN = 0 V and ILOAD = 0 A Max. 560 VCC-2 VIN = 0 V, VLOAD = VCC = 24 V mΩ V 0.5 VIN = 0 V, VLOAD = VCC = 50 V μA 10 0.21 Unit 0.50 0.73 V 1 uA Min. Typ. Max. Unit Table 6. Switching (VCC = 24 V; RLOAD = 24 Ω, input rise time < 0.1 μs ) Symbol DS12305 - Rev 5 Parameter tr Rise time tf Fall time tPD(H-L) Propagation delay time INx to LOADx, low to high tPD(L-H) Propagation delay time INx to LOADx, high to low Test conditions 450 700 see fig 3 : trise and tfall 500 600 and fig 4 tPD(L-H) and tPD(H-L) 500 700 400 600 ns page 8/29 IPS4260L Electrical characteristics Figure 3. trise and tfall VLOADX 90% 10% tr tf t Figure 4. tPD(L-H) and tPD(H-L) VINx 50% t VLOADx 90% 10% t tPD(L-H) tPD(H-L) Table 7. Logic inputs Symbol Parameter Test conditions VIL Input low level voltage VIN decreasing VIH Input high level voltage VIN increasing VI(HYST) Input hysteresis voltage VOL DS12305 - Rev 5 Voltage drop on OL pin Min. Typ. Max. Unit 0.8 2.0 V 0.4 IOL = 5 mA VINx = 0 V, OUTx = open load, RPD between OUTx and GND 0.1 page 9/29 IPS4260L Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VFAULT Voltage drop on FAULT pin or INx pin IFLT = 5 mA VINx = 0 V, (TJX > TJSD or cut-off event) 0.1 V IINX All digital input/output pin current VIN = 5 V 70 μA Table 8. Protection and diagnostic Symbol Parameter Test conditions Typ. Max. Vclamp VCC clamp voltage ICC ≤ 10 mA 55 58 60 Vdemag Demagnetization voltage IOUT = 0.5 A; load ≥10 mH 55 58 60 Ipeak Current limitation activation threshold. ILOAD increasing from 0A to short circuit. ILIM Current limitation level tcoff Cut-off current delay time Unit V ILIM +20% 30 kΩ ≤ RILIM ˂ 120 kΩ A 60/RILIM[kΩ] ± 30% 0 ˂ RILIM ˂ 30 kΩ A 3 ± 30% Programmable by external resistor on "cut-off" pin (valid in the range from 60 kΩ to 240 kΩ). RCoD= 0 Ω cut-off disabled DS12305 - Rev 5 Min. RCoD[kΩ]/120 ± 15% ms The IC is protected against overheating by the thermal shutdown only. tres Power stage restart delay time tBKT Open load blanking time IVD Vcc wire break power stage current TJSD Junction temperature shutdown 160 °C TJHYST Junction temperature thermal hysteresis 20 °C VOLoff Open load (off-state) or short-to-ground detection threshold 31*tcoff± 15% 12.0 16.5 VINx = VCC =0 V; VLOADx = 24 V, Vz floating Vcc-4.5 Vcc-3.5 ms 21 μs 50 μA Vcc-2.5 V page 10/29 IPS4260L Power stage logic 5 Power stage logic Table 9. Power stage (LOADx pin) truth table Operation Normal Cut-off UVLO Open load/short-to-GND Overtemperature MCU_OUTx INx LOADx FLT OL L L H H H H H L H H L L H L H H L H L H L L H X X H H H X X L L L H L H H L H H L L H L H H L H L H MCU_OUTX VCC INX VZCL < 55V - VCC OPTO ISOLATION VDD FAST DECAY Figure 5. Application circuit (fast decay enabled by TVS between Vz and supply rail) LLOAD IPS4260L Logic Side Supply FLT VZ Internal circuit Controller Process Side Supply LOADx OL ILIM RILIM DS12305 - Rev 5 ICOD SGND PGND RCOD page 11/29 IPS4260L Power stage logic Figure 6. Application circuit (fast decay enabled by TVS between VZ and PGND). OPTO ISOLATION VDD MCU_OUTX VCC INX LLOAD IPS4260L Logic Side Supply FLT Controller Process Side Supply VZ Internal circuit LOADx OL ICOD SGND FAST DECAY VBR > Vcc ILIM PGND RCOD RILIM VZCL< 55V OPTO ISOLATION VDD MCU_OUTX VCC INX SLOW DECAY Figure 7. Application circuit ( fast decay disabled by Vz shorted to supply rail ) . LLOAD IPS4260L Logic Side Supply FLT Internal circuit Controller VZ Process Side Supply LOADx OL ILIM RILIM DS12305 - Rev 5 ICOD SGND PGND RCOD page 12/29 IPS4260L Protection and diagnostic 6 Protection and diagnostic The IC integrates several protections to ease the design of a robust application. 6.1 Undervoltage lock-out The device turns off if the supply voltage falls below the turn-off threshold (VUV(off)). Normal operation restarts after VCC exceeds the turn-on threshold (VUV(on)). Turn-on and turn-off thresholds are defined in Table 4. Supply. 6.2 Overtemperature The power stage of each channel is turned off as its internal junction temperature (TJ) exceeds the shutdown threshold (TJSD). Normal operation restarts when TJ comes back below the reset threshold (see Table 8. Protection and diagnostic). The internal fault signal is set when the channel is OFF due to thermal protection. The thermal fault is reported both on the FLT pin and on the INx pin of the corresponding LOADx in fault. Note that the FLT pin reports the logic OR of the four output channels faults. Figure 8. Thermal protection signalization behavior on FLT MCUx VINx TJ TJSD TJHYS ____ FLT 6.3 Current limitation and cut-off The load current flows through the integrated power stage and it is internally limited by the specific ILIM threshold that can be set by an external resistor (RILIM) placed between ILIM and SGND ground plane. The design rule for the RILIM resistor is: Equation 1: (1) ILIM = 60/RILIM[kΩ] The above design rule is valid in the range 30 kΩ ≤ RILIM ≤ 120 kΩ. For 0 ≤ RILIM < 30 kΩ, the current is internally limited up to 3 A (typical). For RILIM > 120 kΩ the current is anyway limited but the linearity is not guaranteed. DS12305 - Rev 5 page 13/29 IPS4260L Open load in off-state The IPS4260L implements the cut-off feature which limits the duration of the current limitation condition. The duration of the current limitation condition (Tcoff) can be set by a resistor (RCoD) placed between CoD and SGND ground plane. The design rule for RCoD is: Equation 2: (2) Tcoff = RCoD[kΩ]/120 The above design rule is valid in the range 60 kΩ ≤ RCoD ≤ 240 kΩ. As 0 < RCoD < 60 kΩ, Tcoff anyway decreases but the linearity of the above design rule is not guaranteed. As RCoD = 0 Ω (short-to-ground plane) the cut-off feature is disabled, by means the IC is protected by thermal shutdown only. Concerning RCoD > 240 kΩ, Tcoff increases but linearity of equation 2 is not guaranteed. In case ILIM threshold is triggered, the power stage remains in the current limitation condition (ILOADx = ILIM) at least for tcoff. When tcoff elapses, the power stage is turned off and restarted after the tres restart time. The fault condition is reported both on FLT pin and on the input pin (INx) corresponding to the channel in fault. The internal cut-off flag signal is latched at power stage switch-off and released after the time tres. The same behavior is reported on FLT pin and on the INx pins related to the LOADx in fault. If one of the four channels is in overload protection, the other channels (in operating conditions) work properly. The status of FLT is independent of the INx pin status, and is low during the whole cut-off time (tres). The same behavior has to be respected on fault signals on input pins. If CoD pin is shorted to SGND ground plane (cut-off feature disabled) then the output channel remains ON, in current limitation condition, until the related input becomes LOW or the thermal protection threshold is triggered. Figure 9. Cut-off signalization behavior on FLT MCUX (2) VINX (1) (1)= TCUT-OFF (2) = TRES ILOADX IPEAK ILIM Inductive load behavior FLT 6.4 Open load in off-state The IPS4260L provides the open load detection feature, which detects if the load is disconnected (wire break) from the LOADx pin when in OFF-state (INx = LOW). This feature can be activated by placing a proper resistor (RPD) between LOADx and PGND ground plane. DS12305 - Rev 5 page 14/29 IPS4260L GND wire break protection Figure 10. Open load off-state APPLICATION BOARD SUPPLY RAIL VCC IPS4260L + VOL-OFF . . . VZ IPU LOAD VCC LOADX Open load detection signal . . . RPD PGND GROUND PLANE The voltage on LOADx pin (VLOADx) is internally compared with the VOLOFF threshold: if the related INx pin is LOW and the VLOADX goes lower than VOLOFF then the open load condition is triggered. The fault condition is reported on the OL pin and the fault reset occurs when load is reconnected. If the channel is switched ON by the related INx pin, the fault condition is no longer detected. In OFF state, the IPS4260L achieves the open load detection feature by forcing the internally generated current IPU (= 20 μA) on the external pull-down resistor RPD. The following design rule has to be followed in order to set the proper value of RPD: Equation 3: Note: RPD < VOLOFF min IPU = VCC − 4.5 IPU (3) When the load is connected the open load detection threshold must not be triggered: Equation 4: Therefore: Equation 5: VLOADX = VCC * RPD RPD + RLOAD RPD > RLOAD * > VOLOFF max VOLOFF max VCC − VOLOFF max (4) (5) Note: if two or more channels are parallelized then RPD must be calculated according to the n*Ipu (e.g. in case of 4 channels in parallel the total Ipu becomes 80uA). 6.5 GND wire break protection GND wire break is intended as the disconnection event of the application board ground (where both SGND and PGND signals are connected) from the system ground of the external supply rail (see fig 11 GND wire break, where the shape between VZ and supply rail represents one of the application configurations: open circuit, short circuit or an external TVS). When this event happens, the supply voltage at Vcc pin decreases until Vuvoff is triggered and then all power stages are turned off independently of the input status. In case of inductive load, if the ground disconnection event happens while one or more channels are active: DS12305 - Rev 5 page 15/29 IPS4260L VCC wire break protection - in case of Vz pins floating, the residual current in the inductor flows through the integrated power switch, which is activated by active clamp as if the input had been deactivated. - in case of Vz pins connected to supply rail (by short circuit or by TVS), the residual current in the inductor flows through the catch diodes. Similarly, the catch diodes allows the proper ground disconnection protection even in case of Vz pins connected by a TVS to ground layer. Figure 11. GND wire break APPLICATION BOARD APPLICATION SUPPLY RAIL VCC IC VZ . . . LOAD VCC LOADX . . . PGND GROUND PLANE 6.6 VCC wire break protection VCC wire break is intended as the disconnection of the application board form rail supply (see Figure 13. VCC wire break , where the shape between VZ and supply rail represents one of the application configurations: open circuit, short circuit or an external TVS). When this condition is detected, all power stage channels are turned off independently of the input status. The maximum steady-state current measured through a channel in short to the supply voltage is not greater than IVD (see Table 7. Logic inputs). The same behavior is guaranteed when all channels are simultaneously in short to the supply voltage. In case of inductive load, if the Vcc is disconnected while one or more channels are active, the current flows through the power, which is activated by the active clamp as if the input had been deactivated. Figure 12. VCC wire break APPLICATION BOARD L+ APPLICATION SUPPLY RAIL VCC IC VZ . . . LOAD LOADX . . . PGND L- GROUND PLANE DS12305 - Rev 5 page 16/29 IPS4260L VCC wire break protection VCC wire break protection is guaranteed when VZ floats or when VZ is connected to GND by a proper TVS, while it is limited (see below) when VZ is shorted to VCC. If VZ is connected to VCC by a TVS (with clamping voltage = VCL), then VCC wire break protection is limited by the following design rule: VCL > VL+ - (VLOAD+VD+VUVLO). DS12305 - Rev 5 page 17/29 IPS4260L Active clamp 7 Active clamp Active clamp is also known as fast demagnetization of inductive loads or fast current decay. When a low-side driver turns off an inductance, an overvoltage on load is detected. If VZ pins are directly shorted to the supply rail (see fig 7 Application circuit ( fast decay disabled by Vz shorted to supply rail ) . ) then the fast current decay is disabled: the inductive load is demagnetized slowly and according to the forward voltage of the integrated clamp diodes (VFCD). The figure below shows the typical waveforms of the load voltage and current in case of slow demagnetization. Figure 13. VLOAD and ILOAD in case of slow demagnetization ILOADx time VLOADX VCC+VFCD VCC TDEMAG time VINX OFF ON ON time If VZ pins are left floating (see fig 14 Active clamp equivalent principle schematic. ) or connected by a Zener or TVS diode to supply rail (see fig 5 Application circuit (fast decay enabled by TVS between Vz and supply rail) ) or PGND (see fig 6 Application circuit (fast decay enabled by TVS between VZ and PGND). then the fast decay is activated. When VZ pins are left floating the integrated clamping circuit protects the IC despite overvoltages: the conduction state of the integrated switches is modulated in order to keep the LOADx pin voltage < Vdemag until the energy in the load has been dissipated. The demagnetization energy is dissipated in the IC and it is limited by the internal heatsink capability, see EAS in Table 2. Absolute maximum ratings . Figure 14. Active clamp equivalent principle schematic. APPLICATION BOARD SUPPLY RAIL VCC IPS4260L . . . VZ IPU LOAD VCC LOADX . . . Active Clamp Circuitry RPD PGND GROUND PLANE DS12305 - Rev 5 page 18/29 IPS4260L Fast current decay with TVS between VZ and supply rail 7.1 Fast current decay with TVS between VZ and supply rail Being VCLZ the clamping voltage of the external TVS, when the inductive load is turned off the LOADx pin is pulled up to VCC+VCLZ. In order to avoid any damage to the IPS4260L, the external diode must be selected such that VCLZ < (VDEMAG(MIN) – VCC). Furthermore, the external diode must be selected such that it is able to dissipate the power due to the demagnetization currents flowing from the active channels. Figure 15. VLOAD and ILOAD in case of fast demagnetization (fast decay) ILOADx VLOADX time VCC+VZCL VCC TDEMAG time VINX ON OFF ON time 7.2 Fast current decay with TVS between VZ and PGND Being VCLZ the clamping voltage of the external TVS, when the inductive load is turned off the LOADx pin is clamped by the lower voltage between VCLZ and VDEMAG(MIN). In order to avoid any leakage currrent on the external TVS has to be selected such that its VBR results > VCC, while in order to avoid any damage to the IPS4260L the VCLZ of the external TVS must be selected such that VCLZ < VDEMAG(MIN). Further, the external diode must be selected such that it is able to dissipate the power due to the demagnetization currents flowing from the active channels. DS12305 - Rev 5 page 19/29 IPS4260L 8 8.1 HTSSOP20 package information Figure 16. HTSSOP20 package outline GAUGE PLANE 7292297_C Table 10. HTSSOP20 mechanical data mm Dim. Min. inch Typ. Max. A 1.2 A1 0.15 A2 0.8 b Typ. Max. 0.047 0.004 0.006 0.039 0.041 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 D1 4.1 4.2 4.3 0.161 0.165 0.169 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.5 0.169 0.173 0.177 E2 2.9 3.0 3.1 0.114 0.118 0.122 e 0.65 K 0° L 0.45 DS12305 - Rev 5 1 Min. 0.60 0.0256 8° 0° 0.75 0.018 8° 0.024 0.030 page 20/29 IPS4260L Packaging information 9 Packaging information 9.1 HTSSOP20 packaging information Figure 17. Carrier Tape for HTSSOP20 20L DS12305 - Rev 5 page 21/29 IPS4260L HTSSOP20 packaging information Figure 18. HTSSOP20 Shipping Tube DS12305 - Rev 5 page 22/29 IPS4260L Ordering information 10 Ordering information Table 11. Ordering information Order code IPS4260L IPS4260LTR DS12305 - Rev 5 Package HTSSOP20 Packing Tube Tape and reel page 23/29 IPS4260L Revision history Table 12. Document revision history DS12305 - Rev 5 Date Revision Changes 02-Oct-2017 1 Initial release. 20-Sep-2019 2 Modified Table 3. Thermal data, Features update () , Minor text updates inside Description , Rephrased Section 2.3 VZ , Rephrased Section 2.6 Open load in off-state, Updated Typ. in Table 5. Output stage, Updated Max. in Table 6. Switching (VCC = 24 V; RLOAD = 24 Ω, input rise time < 0.1 μs ), Tcoff and IVD updated in Table 8. Protection and diagnostic , Rephrased Section 6.2 Overtemperature, Updated Equation 3: Equation 4: Equation 5: Added fig 18 HTSSOP20 Shipping Tube . 06-Apr-2020 3 Modified Table 4. Supply, Table 5. Output stage, Table 8. Protection and diagnostic, minor text updates inside the document. 29-Jun-2020 4 Correct thermal data values in Table 3 30-Jul-2021 5 Updated section Section 6.4 Open load in off-state page 24/29 IPS4260L Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 PGND, SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 VZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 IN1, IN2, IN3, IN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 LOAD1, LOAD2, LOAD3, LOAD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 Open load in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.7 FLT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.8 ILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.9 CoD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Power stage logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6 Protection and diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 7 8 6.1 Undervoltage lock-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Current limitation and cut-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Open load in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 GND wire break protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 VCC wire break protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Active clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7.1 Fast current decay with TVS between VZ and supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 Fast current decay with TVS between VZ and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.1 9 Packaging information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 9.1 10 HTSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 HTSSOP20 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 DS12305 - Rev 5 page 25/29 IPS4260L Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DS12305 - Rev 5 page 26/29 IPS4260L List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching (VCC = 24 V; RLOAD = 24 Ω, input rise time < 0.1 μs ) . Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . Power stage (LOADx pin) truth table. . . . . . . . . . . . . . . . . . . . HTSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12305 - Rev 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 7 . 7 . 8 . 8 . 8 . 9 10 11 20 23 24 page 27/29 IPS4260L List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. DS12305 - Rev 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . trise and tfall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tPD(L-H) and tPD(H-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit (fast decay enabled by TVS between Vz and supply rail) Application circuit (fast decay enabled by TVS between VZ and PGND). . . Application circuit ( fast decay disabled by Vz shorted to supply rail ) . . . . . Thermal protection signalization behavior on FLT . . . . . . . . . . . . . . . . . . Cut-off signalization behavior on FLT . . . . . . . . . . . . . . . . . . . . . . . . . . Open load off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND wire break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC wire break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLOAD and ILOAD in case of slow demagnetization. . . . . . . . . . . . . . . . . . Active clamp equivalent principle schematic. . . . . . . . . . . . . . . . . . . . . . VLOAD and ILOAD in case of fast demagnetization (fast decay) . . . . . . . . . HTSSOP20 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Tape for HTSSOP20 20L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HTSSOP20 Shipping Tube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 9 . 9 11 12 12 13 14 15 16 16 18 18 19 20 21 22 page 28/29 IPS4260L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS12305 - Rev 5 page 29/29