L6615
High/low-side load share controller
Datasheet - production data
SO8
Features
• Compliant with SSI specifications
• High/low-side current sensing
• Fully compatible with remote output voltage
sensing
• Full differential low offset current sense
• 2.7 V to 22 V VCC operating range
• 32 kΩ share sense amplifier input impedance
• Hysteretic UVLO
Applications
• Distributed power systems
• High density DC-DC converters
DC converters in parallel is required. The device
performs both high-side and low-side current
sensing, in this manner the sense current resistor
can be placed either in series to the power supply
output or on the ground return. The L6615 drives
the share bus to a voltage proportional to the
output current of the master, which is the highest
among the output currents delivered by the
paralleled power supplies. The share bus
dynamics is independent from the power supply
output voltage and is clamped by the device
supply voltage (VCC) only. The output voltage of
the other paralleled power supplies (slaves) is
trimmed by the ADJ pin so that they can support
their amount of load current. The slave power
supplies work as current-controlled sources.
Thanks to the sharing of the output currents, the
thermal stress of the different modules can be
equalized and provides more reliability. Moreover,
the paralleled supply architecture allows
redundancy to be achieved. The failure of one of
the modules can be tolerated until the capability
of the remaining power supplies is enough to
provide the required load current.
• (N+1) redundant systems, N up to 20
Table 1. Device summary
• SMPS for (web) servers
Order code
Description
L6615D
This is information on a product in full production.
Packaging
Tube
SO8
This controller IC is specifically designed to
achieve load sharing of paralleled and
independent power supply modules in distributed
power systems, by adding only few external
components. Current sharing is achieved through
a single wire connection (share bus) common to
the paralleled modules. Load sharing is a
technique used in all systems in which the load
requires low voltage, high-current and/or
redundancy: for this reason a modular power
system with two or more power supplies or DCAugust 2013
Package
L6615D013TR
DocID8881 Rev 5
Tape and reel
1/26
www.st.com
26
Contents
L6615
Contents
1
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
Current sense section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Share drive amplifier (SDA), error amplifier and adjustable amplifier . . . 12
5.3
Designing with the L6615 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4
Current sense methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5
Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6
Low voltage buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7
Offset trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
DocID8881 Rev 5
L6615
1
Typical application diagram
Typical application diagram
Figure 1. Application diagram
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Pin connection
2
L6615
Pin connection
Figure 2. Pin connection (top view)
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Table 2. Pin description
N.
Pin
1
GND
Ground.
2
CS-
Input of current sense amplifier; it is connected to the negative side of the
sense resistor through a resistor (RG2).
3
CS+
Input of current sense amplifier. A resistor RG1, with the same value as
RG2, is placed between this pin and the positive side of the sense resistor:
its value defines the transconductance gain between ICGA and VSENSE.
ADJ
Output of adjust amplifier; it is connected to both the loads (through a
resistor RADJ) and to the positive remote sense pin of the power system.
This pin is an open collector diverting (from the feedback path) a current
proportional to the difference between the current supplied to the load by
the relevant power supply and the current supplied by the master.
4
4/26
Function
5
Output of the current sharing (transconductance) error amplifier and input
COMP of ADJ amplifier. Typically, a compensation network is placed between this
pin and ground. The maximum voltage is internally clamped to 1.5 V (typ.).
6
SH
Share bus pin. During the power supply slave operation, this pin acts as
positive input from share bus. During the power supply master operation, it
drives the share bus to a voltage proportional to the load current. The share
bus connects the SH pins of all the paralleled modules. A capacitor
between this pin and GND could be useful to reduce the noise present on
the share bus.
7
CGA
Current gain adjust pin; current sense amplifier output. A resistor
connected between this pin and ground defines the maximum voltage on
the share bus and sets the gain of the current sharing system.
8
VCC
Supply voltage of the IC.
DocID8881 Rev 5
L6615
Electrical data
3
Electrical data
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Pin
VCC
8
ICS+, ICS-
Value
Unit
Self limited
V
10
mA
-0.3 to VCC
V
Error amplifier output
-0.3 to 1.5
V
Differential input voltage (VCS+ from 0 V to 22 V)
-0.7 to 0.7
V
0.45
W
Junction temperature range
-40 to +125
°C
Storage temperature
-55 to +150
°C
Supply voltage(1) (ICC < 50 mA)
Sense pin current
VCS-, VCS+,
VSH, VADJ,
VCGA
2, 3, 6, 4, 7
VCOMP
5
(VCS+) - (VCS-)
Ptot
Total power dissipation @ Tamb = 70 °C SO8
Tj
Tstg
1.
Parameter
Maximum package power dissipation limits must be observed.
Note:
All voltages are referred to pin1. Current is positive when it is in the specified terminal, it is
negative when it is out of it.
3.2
Thermal data
Table 4. Thermal data
Symbol
Rthj-amb
Parameter
Thermal resistance junction-to-ambient
DocID8881 Rev 5
SO8
Unit
120
°C/W
5/26
Electrical characteristics
4
L6615
Electrical characteristics
(Tj = - 40 to 85 °C, Vcc = 12 V, VADJ = 12 V, CCOMP = 5 nF to GND, RCGA = 16 kΩ, unless
otherwise specified; VSENSE = IL * RSENSE, RG1 = RG2 = 200 Ω)
Table 5. Electrical characteristics
Symbol
Parameter
Test condition s
Min.
Typ.
Max.
Unit
22
V
5
6
mA
2.45
2.60
2.75
V
2.35
2.5
2.65
V
Vcc
Vcc
Operating range
Icc
Quiescent current VSH = 1 V, VSENSE = 0 V
VCC, ON
Turn-on voltage
VCC,OFF
Turn-off voltage
VH
2.7
VSH = 0.2 V, VSENSE = 0 V
Hysteresis
Vz
100
mV
V
ICC = 20 mA
24
26
-2
0.0
Current sense amplifier
VOS
Input offset
voltage
0.1 V ≤ VSH ≤ 10.0 V
VCGA
Out high voltage
VSENSE = 0.25 V
ICGAS
Short-circuit
current
VCGA = 0 V, VSENSE = 0.45 V
IB(CS-)
Input bias current
VSENSE = 0 V, VCS+ = +12 V
(high-side
sensing)
1.0
μA
IB(CS+)
Input bias current
V
= 0 V, VCS+= 0 V
(low-side sensing) SENSE
-1.0
μA
VCC
V
CMR
VTHCS+
SWH
Common mode
dynamics range
VCS-, VCS+
2
VCC- 2.2
-1.5
mV
V
-2.0
0
mV
Switchover
threshold low-side
VCS+
to high-side
sensing
1.6
V
Switchover
hysteresis
0.16
V
Share drive amplifier
6/26
HVSH
SH high output
voltage
VSENSE = 250 mV, ISH = -1 mA
LVSH
SH low output
voltage
VCGA = 0 mV, R SH = 200 Ω
Vcc- 2.2
V
45
mV
(+)
High-side sensing
mirror accuracy(1)
±1
±5
%
(-)
Low-side sensing
mirror accuracy(1)
±1
±5
%
DocID8881 Rev 5
L6615
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
VSH, l oad
ISC
SR
Parameter
Test condition s
Min.
Typ.
Max.
Unit
20
mV
Load regulation
-1.0 mA ≤ ISDA(OUT) ≤ -4 mA
Short-circuit
current
VSH = 0 V, VSENSE = 25 mV
-20
-13.5
-8
mA
VSENSE = -10 mV to 90 mV step,
RSH = 200 to GND
0.8
1.5
2.2
V/μs
VSENSE = 90 mV to -10 mV step,
RSH = 200 to GND
2
3
4
V/μs
22.4
32
41.6
KΩ
3
4
5
ms
30
50
70
mV
Slew rate
Share sense amplifier
Ri
Input impedance
Error amplifier
Gm
Transconductance
Vos
Input offset
voltage
VCGA = 1 V
IOH
Source current
VCOMP = 1.5 V, VSH ≥ 300 mV,
VSENSE = -10 mV
-150
-350
-400
μA
IOL
Sink current
VCOMP = 1.5 V,
VSENSE = -10 mV 200 Ω resistor
SH to GND
100
200
300
μA
VCOMP(L)
Low voltage
0.05
0.15
0.25
V
VZ
C lamp Zener
voltage
IZ = 1 mA
1.5
V
ADJ amplifier
IADJ
ADJ output
current
VT
Threshold voltage IADJ = 10 A
RA
Emitter resistor
Guaranteed by design
VADJ(MIN)
Low saturation
voltage
VSH = 1 V, VSENSE = 0 V
6.5
10
13
0.7
mA
V
140
Ω
IADJ = 5 mA
1
V
IADJ = 1 mA
0.4
V
60
100
1. Mirror accuracy is defined as follows (see Equation 1), and it represents the accuracy of the transfer
between the voltage sensed and the voltage imposed on the share bus.
Equation 1
V SH
----------------------------------------- – 1 ⋅ 100
R CGA
VSENSE ⋅ --------------RG
DocID8881 Rev 5
7/26
Electrical characteristics
L6615
Figure 3. Block diagram
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Figure 4. Turn-on and turn-off voltage
Figure 5. Max. CGA current
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L6615
Electrical characteristics
Figure 6. Supply current vs. supply voltage
Figure 7. High-side/low-side sensing
switchover threshold
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Figure 8. Supply current
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Figure 9. Max. share bus voltage at no load
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Figure 10. Share bus input impedance
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Application information
5
L6615
Application information
The power supply systems are often designed by converters in parallel so to improve the
performance and reliability.
To ensure a uniform distribution of stresses, the total load current should be shared
appropriately among the converters.
A typical application, relative to a series of N paralleled modules (PS#1 to PS#N), is showed
in Figure 12. Each of them exhibits 4 terminals: two about the power outputs (+OUT, -OUT)
and two about the remote sense signals (+OUT_S, -OUT_S).
The sense resistors RSENSE (for the current sensing) and the OR-ing diodes (to avoid that
the failure of one module shorts the load out) are placed on the power lines.
The L6615 allows an automatic master-slave current sharing architecture to be attained:
one L6615 is associated to each power supply and all the ICs are linked each other through
the share bus (referred to the common ground). This kind of system configuration is
preferred to the systems in which a single current sharing controller is used, because of its
robustness, reliability and flexibility.
To configure a load share controller, few passive components are used. A brief device
explanation, together with the formulas useful to set these external components, follows.
Figure 12. Typical high-side connection
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10/26
DocID8881 Rev 5
L6615
5.1
Application information
Current sense section
A sense resistor is typically used to generate the voltage drop, proportional to the load
current, measured by the CSA (current sense amplifier), whose input pins (pins #2 and #3)
are connected to RSENSE through two identical resistors (RG1 and RG2) (see Figure 12).
The CSA consists of 2 sections (see Figure 13 and 14), one responsible for the high-side
sensing, the other for low-side sensing. An internal comparator activates the relevant
section in accordance with the voltage present at CS+ pin: if this voltage is higher than 1.6 V
(typ.), the high-side sensing section is activated (Figure 13) otherwise the low-side sensing
is activated (Figure 14). RG1= RG2= RG are considered for simplicity.
As the voltage drop IOUT*RSENSE is present at the input of the sense amplifier section, its
output forces the controlled current mirror to:
- sink current from the CS+ pin in case of high-side sensing (neglecting input bias current,
no current flows through CS- pin);
- source current from the CS- pin in case of low-side sensing (neglecting input bias current,
no current flows through CS- pin).
The local feedback imposes the same voltage at the current sense input pins, so under
closed loop condition VSENSE = VRG. The current ICS
Equation 1
I OUT ⋅ R SENSE
I CS = -------------------------------------RG
(ICS+ in case of high-side, ICS- in case of low-side) is then internally mirrored and sent to
the CGA pin causing a drop across the R CGA external resistor. Two internal buffers
transfer VCGA signal to the share pin so:
Equation 2
V SNS
V SH = -------------- ⋅ R CGA
RG
Only the L6615 VCC limits the upper voltage at the CGA and SH pin, regardless the
voltage present at the current sense pins.
In noisy applications, two capacitors of small value (e.g. 1 nF) connected between
current sense pins and ground could be useful to clean the signal at the input of the
current sense amplifier.
For low voltage buses see , Section 5.6: Low voltage buses.
DocID8881 Rev 5
11/26
Application information
L6615
Figure 13. Current sense (high-side)
Figure 14. Current sense (low-side)
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Share drive amplifier (SDA), error amplifier and adjustable
amplifier
The gain between the output of CSA (CGA pin) and output of SDA (SH pin) is 1 (typ.) so,
with regard to the master power supply, VCGA = VSH, the voltage on the share bus is
imposed by the master.
In the slave converters, being VCGA(SLAVE) < VCGA(MASTER), the diode at the output of SDA
(see block diagram) isolates the output of this amplifier from the share bus.
The share sense amplifier (SSA) reads the bus voltage transferring the signal to the noninverting input of the error amplifier where it is compared with CGA voltage.
Whenever a controller acts as the master in the system, the voltage difference between the
E/A inputs is zero. In this condition, to guarantee a low output, a 40 mV offset, in series with
the inverting input, is inserted.
Instead in the slave converters, the input voltage difference is proportional to the difference
between the master load current and the relevant slave load current.
The transconductance E/A converts the ΔV at its inputs in a current equal to
Equation 3
I OUT = G M ⋅ ΔV
IOUT flows through the compensation network connected between COMP pin and ground.
The E/A output voltage drives the adjustable amplifier to sink current from the ADJ pin,
which is in turn connected to the output voltage through a small resistor along the sense
path. The current, sunk by ADJ pin, is deviated from feedback path of the slave power
supply, causing an increase of its duty cycle.
In steady-state the current, sunk by the ADJ pin, is proportional to the value of the error
amplifier output.
12/26
DocID8881 Rev 5
L6615
5.3
Application information
Designing with the L6615
The first design step is usually the choice of the sense resistor whose maximum value is
limited by the power dissipation; this constraint must be traded-off against the precision of
the L6615 current sensing. In fact, a small sense resistance value lowers the power
dissipation but reduces the signal available at the inputs of the L6615 current sense
amplifier.
Once RSENSE is fixed then the RG and RGCA values are chosen in accordance with the
application specifications: usually these specs define the share bus voltage (VSH(MAX)) and
the number of paralleled power supplies.
Their value must comply with the constraints imposed by the L6615:
Figure 15. Simplified feedback block diagram
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maximum share bus voltage is internally limited up to 2.2 V below the L6615 VCC
voltage (pin#8);
–
VSH(MAX) represents an upper limit but the designer should select the full scale
share bus voltage keeping in mind that each Volt on the share bus increases the
master controller's supply current by approximately 45 μA for each slave unit
connected in parallel; this total current, provided by the master share drive
amplifier, must be lower than its minimum output capability (8 mA) so:
Equation 4
R i ( MIN )
V SH ( MAX ) < ------------------- ⋅ 8mA
N
DocID8881 Rev 5
13/26
Application information
L6615
This condition isn’t met in normal applications, as the user can easily see by using sensible
values for N (number of paralleled power supplies) and VSH(MAX). For example, VSH(MAX) =
8 V, solving for N, NMAX = 20 is obtained;
–
maximum share drive amplifier current capability (ICGA(MAX) = 2 mA);
–
for safety reasons the following relation must be met:
Equation 5
1 V OUT
R G > --- ⋅ ---------------- – 40
2 10mA
in this way no fault causes ICS+ (or ICS-) to overcome its absolute maximum ratings.
At full load, ΔVSENSE(MAX) = IOUT(MAX) · RSENSE(MAX) is the maximum voltage drop across
the resistor RSENSE (typically few hundreds mV).
IOUT(MAX) is the maximum current carried by each of the paralleled power supplies; in nonredundant systems composed by N power supplies, each of them works at its nominal
current, so:
Equation 6
I LOAD
I OUT ( MAX ) = --------------N
This relationship is also true in N+M redundant system, even if in normal conditions each
power supply provides ILOAD/(N+M).
For example, in a system composed by two paralleled power supplies 100% redundant
(N=M=1), each module is sized to sustain the entire load current (in normal operation it
carries one half only): for this reason, the sense resistor must be sized considering the
whole load current.
The temperature variation of the sense resistor (hence its resistance value) has to be taken
into account, so RSENSE(MAX) is the value at maximum operating temperature to avoid
saturating the share bus. Once VSENSE(MAX) is fixed, the ratio RCGA/RG (gain from the
sensing section to the share bus) can be calculated:
Equation 7
R CGA
V SH ( MAX )
--------------- = -----------------------------------RG
V SENSE ( MAX )
where VSH(MAX) is defined by the application. A small capacitor in parallel to RCGA is useful
to reduce the noise.
The effect of current sharing feedback loop is to force the voltages of the slave CGA pins to
be equal to VSH (that is to reduce the voltage difference at the inputs of the L6615 error
amplifier). To simplify, 2 paralleled power supplies, under a closed loop condition(Figure 15),
are considered:
Equation 8
R SNS ( 1 )
R SNS ( 2 )
I OUT ( 1 ) ⋅ --------------------- ⋅ R CGA ( 1 ) = IOUT ( 2 ) ⋅ --------------------- ⋅ R CGA ( 2 )
RG (1 )
RG ( 2 )
14/26
DocID8881 Rev 5
L6615
Application information
Ideally all the external components match so:
Equation 9
I LOAD
I OUT ( 1 ) = IOUT ( 2 ) = --------------2
Any mismatch has an impact on the sharing precision: in particular the maximum difference
between the output currents (sharing error) is given by the sum of the mismatches among
the relevant values.
Figure 16. ADJ network
Figure 17. ADJ network for an "off-the-shelf"
power supply
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The tolerance required by the power supply output voltage (VOUT ± VO) has to be known in
order to set the RADJ value; the maximum difference between master and slave output
voltage is 2* VO and this amount represents the voltage that the L6615 must be able to
correct.
Two different approaches are feasible, depending on whether the SMPS (whose output
current must be shared) has to be completely designed or it is an "off-the-shelf" component
and the current sharing section must be only designed.
The former: the adjustment resistor (RADJ) can be considered as a fraction of the high
resistor of the feedback divider RH (Figure 16). Typically the first step consists of fixing the
current flowing, under steady-state condition, through the feedback divider IFB; by choosing
the value for R2:
Equation 10
V REF
IFB = -------------R2
where:
DocID8881 Rev 5
15/26
Application information
L6615
Equation 11
V OUT
R H = R 1 + R ADJ = -------------- – 1 ⋅ R 2
V REF
RADJ has to be lower than (or equal to) one tenth of R1, considering that, in the worst
conditions, it is:
Equation 12
ΔV OUT
I ADJ ( max ) = -----------------R ADJ
This value must not exceed the one indicated in Section 4: Electrical characteristics. This is
very easy to meet, as the user can easily see by using ΔVOUT and R2 sensible values.
The latter (Figure 17): the feedback divider has already been designed by the SMPS
manufacturer and cannot be modified. The RADJ design lets the L6615 correct the maximum
spread without significantly shifting the SMPS regulation point. A minimum RADJ value can
be found by:
Equation 13
ΔV OUT
R ADJ ( MIN ) = -------------------------IADJ ( MAX )
where IADJ(MAX) is 8 mA.
The adjustment network saturation must be avoided especially for low voltage output buses;
the design must satisfy the following relationship:
Equation 14
VOUT – R ADJ ⋅ ( IADJ + I FB ) > V ADJ ( MIN )
where VADJ(MIN) can be found in Section 4: Electrical characteristics for different IADJ
values. The last point is the design of the compensation network ZC(s) connected between
the COMP pin and ground.
The current sharing system introduces another outer loop besides the power supply
feedback loop. To avoid the interaction between them, the bandwidth of the sharing loop has
to be designed at least one order of magnitude lower than the bandwidth of the power
supply loop. For the total system, the loop gain is:
Equation 15
R CGA
R ADJ
1
G LOOP ( s ) = R SENSE ⋅ --------------- ⋅ G M ⋅ Z C ( s ) ⋅ -------------- ⋅ A PWR ( s ) ⋅ -----------------RG
RA
R LOAD
where
–
APWR(s) is the transfer function of PWM controller and power stage (Figure 15)
–
RLOAD is the equivalent load resistance
Typically the compensation network is built by the R-C series. A resistor in series with CC is
required to boost the phase margin of the load share loop. Zero is placed at the load share
loop crossover frequency, fC(SH).
16/26
DocID8881 Rev 5
L6615
Application information
If fC(SH) is the share loop crossover frequency, then:
Equation 16
R CGA ⋅ G M R ADJ R SENSE
1
C C = ------------------------------- ⋅ ---------------------------- ⋅ -------------- ⋅ --------------------- ⋅ APWR ( f
C ( SH ) )
RG
RA
R LOAD
2 ⋅ π ⋅ f C ( SH )
1
R C = -------------------------------------------2 ⋅ π ⋅ fC ( SH ) ⋅ C C
5.4
Current sense methods
There are several methods to sense the power supply output current; the simplest method is
to use a power resistor (Figure 18 a) but when the load current increases, an expensive
resistor could be required to support the inherent power dissipation, imposing the use of
several paralleled resistors.
Other methods to sense the output current are showed in Figure 18 b and Figure 18 c:
1.
RDS(on): a power MOS is placed in series to the output and its channel resistance
(RDS(on)) is used as sense resistor (Figure 18 b). The L6615 sense pins are connected,
through RG resistors, to the drain and to the source of the MOS. Besides, providing the
sense resistor, the FET is used as "OR-ing" element: driving properly its gate, the
power supply output could be isolated from the load (the body diode is reversed biased
so it doesn't conduct). This is useful whenever features as hot-swap or hot-plug are
required; compared with the well-known solution using OR-ing diode, the OR-ing FET
greatly reduces the power dissipation, in particular:
Equation 17
2
P( DIODE ) = V F ⋅ IOUT + R SENSE ⋅ I OUT
2
P( MOS ) = R DS ( ON ) ⋅ I OUT
where VF is the forward drop across the diode.
2.
Current transformer: in case of very high load currents, a transformer allows a smaller
current, obtained through a scaling factor equal to the transformer turn ratio, to be
sensed. In this way, the sense resistor power dissipation requirements can be less
tight: the drawback is the additional cost of the transformer. In Figure 18 c, the
simplified output stage of a power supply in forward configuration is showed: through
two current transformers, the load current is reproduced in the sensing circuit scaled by
a factor N. RSENSE reads a ripple (at the switching frequency) superimposed on the
average current value. This ripple doesn't affect the correct behavior of the current
sharing system because its loop gain is designed with a low bandwidth (at least 2
orders of magnitude lower than the switching frequency), which cuts this high
frequency.
DocID8881 Rev 5
17/26
Application information
L6615
Figure 18. Current sense methods
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5.5
Application ideas
Figure 19 shows a single section of a system in which DC-DC modules are in parallel. This
solution can be used whenever the load requires high-current at low voltage; the converter
is designed for a step down configuration using a synchronous rectification controller (for
example the L6910 [1] or the L6911 [2] ST device).
The L6615 reads the drop across the RDS(on) of the OR-ing FET and the LM293 drives its
gate, pulling it down whenever a fault condition (e.g. short on the low-side) appears.
A charge pump could be necessary to be sure that the OR-ing FET VGS is higher than
VGS(TH) (depending on the input and output voltage).
Figure 19. 0.9 to 5 V DC-DC converter with current sharing and hot-plug output
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18/26
DocID8881 Rev 5
L6615
Application information
Figure 20. Distributed power system for +48 V bus
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In this application, a circuit is inserted to protect the square current limit in case of
overcurrent (R1- Q1). The voltage on CGA pin is directly proportional to the current carried
by the relevant section, therefore the CGA resistor can be set to keep the CGA voltage
lower than VREF+0.7 as long as the output current is in the right range. As soon as this value
is overcome, the bipolar pushes current in the feedback path, reducing the duty cycle and
the output voltage accordingly.
Current sharing can be required in AC-DC applications like distributed power system (DPS)
for telecom applications. If the output voltage is higher than the absolute maximum ratings
of the current sense pins (CS+ and CS-), high-side sensing can not be performed unless
adding other components; the current sense is performed on the ground return.
To maintain high-side sensing, two resistor dividers (between the edge of RSENSE and
ground) could be introduced to translate the sense signal into the L6615 input pin common
mode range.
In Figure 15 and Figure 20 two AC-DC converters supply the same load through a +48 V
bus; these converters usually exhibit also a +12 V auxiliary output useful to supply the
L6615 whose ADJ pin works on the +48 V feedback section (COMP pin and CGA pin
connections are not showed) in Figure 20.
5.6
Low voltage buses
The L6615 has a double sense structure, designed to perform both high-side and low-side
sensing: the first solution is usually considered more convenient. Actually, low-side sensing
means to split the ground return as many times as the paralleled power supplies are: on
each of these paths, the sense resistor has to be placed by introducing a drop between the
power supply ground and the common load negative reference.
The voltage at CS+ pin is read by an internal comparator and compared with a reference
corresponding to the switchover threshold VTHcs+ whose value is typically 1.6 V. If such
value is overcome, then the comparator triggers the high-side amplifier (HSA); being the
DocID8881 Rev 5
19/26
Application information
L6615
threshold provided by hysteresis, then the low-side amplifier (LSA) is triggered as VCS+ is
lower than 1.44 V (typ.).
Hence VTHcs+ defines the threshold between the operating range of LSA, (referring to
Figure 13 and Figure 14) and the operating range of HSA. Usually LSA operates when the
sense resistor is placed on the ground return, between the negative load terminal and the
negative power supply output (Figure 14), while the HSA operates when the sense resistor
is placed between the power supply positive output and the load.
The high-side sensing can be performed for applications whose output voltage is close to
VTHcs+ threshold (or even lower) exploiting the low sense internal structure (LSA).
For example, an application where VOUT = 1.2 V and the sense resistor placed high-side;
the voltage at CS+:
Equation 18
V CS + = VOUT – ΔV SENSE
is lower than 1.6 V so the internal comparator triggers on the LSA structure and the pin CSsources the current ICS (see Section 5.4: Current sense methods). The IC works properly
because the dynamics of LSA spreads down to zero: in this case, ADJ network design must
be taken into account.
Another example, an application with VOUT = 1.5 V where, because of the drop across
RSNS, the voltage at CS+ pin could be very close to the threshold: if such voltage is
overcome (startup, load regulation, overvoltage), then the HSA structure is activated; as
nominal conditions are restored, the hysteresis keeps HSA active (unless VCS+ falls under
the lower threshold).
5.7
Offset trimming
The current sharing accuracy strongly depends on the unbalance between the relevant
parameters of the paralleled sections. Each percentage point on the relevant parameter
tolerance introduces a maximum error equal to the double of the tolerance. The L6615
introduces an inherent error to current sharing due to the 40 mV offset at the negative input
of the error amplifier; this offset guarantees the low value of the master COMP pin.
If all other parameters match, the offset introduces a percentage error equal to 4% divided
by the voltage on the share bus:
Equation 19
40mA
I SLAVE = IMASTER ⋅ 1 – ----------------
V SH
Being VSH directly proportional to the load current and fixed the ratio RCGA/RG, higher the
currents involved in the sharing, lower the error.
Another error is introduced by the current sense amplifier due to its input offset whose
amplitude can be ±2 mV: being typically the drop across RSNS about one hundred mV at full
load, the offset could lead to an error of some percentage point.
20/26
DocID8881 Rev 5
L6615
Application information
Whenever the application requires very high-current sharing accuracy, these offsets could
be corrected through a triggering process, introducing a trimmer (RK) between current
sense input pins.
Referring to Figure 21, in case of high-side sensing, the equations are:
V OUT – V M
VM
---------------------------- = ----------------------------RG
( 1 – δ ) ⋅ RK
V OUT + V SENSE – V P
VP
-------------------------------------------------------- – --------------- = I G
RG
δ ⋅ RK
V P = VM + VO
where VO is the current sense amplifier input offset. Solving the IG, we get:
V SENSE δ ⋅ R K + R G
2⋅δ–1
IG = --------------------- – ------------------------------- ⋅ VO + V OUT ⋅ --------------------------------------------------------δ ⋅ R K ⋅ R KG
RG
δ ⋅ RK ⋅ ( 1 – ) + RG
Ideally IG should be equal to the first term only: this current is sunk by CS+ pin, internally
mirrored with 1:1 ratio and sent to CGA pin.
Imposing that the sum of two last terms is zero, the value of δ deleting the effect of the offset
is:
2
δ OPT
2
2
2
2
1 2 ⋅ V OUT ⋅ R G – 4 ⋅ V OUT ⋅ R G + V O ⋅ R K + 4 ⋅ V O ⋅ R G ⋅ R K
= --- – -----------------------------------------------------------------------------------------------------------------------------------------------------------------------2 ⋅ VO ⋅ R K
2
Figure 21. Offset trimming
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21/26
Application information
L6615
Because of the tolerance of the output voltage, the effect of the offset on CGA pin cannot be
deleted completely on the whole output voltage range. If the trimming operation is
performed at VOUT(MIN), the maximum residual voltage on CGA pin is present at VOUT(MAX)
and its value is:
Equation 20
1 – 2 ⋅ δOPT
R CGA ⋅ ( VOUT ( MAX ) – V OUT ( MIN ) ) ⋅ ---------------------------------------------------------------------------δ OPT ⋅ ( R K ⋅ δ OPT – R K – R G )
To simplify the procedure, the following step-by-step process can be followed:
22/26
–
a trimmer has to be placed between sense pins of each section: the value of the
trimmer resistance must be at least one order of magnitude higher than RG and it
has to be set at one half of its range (δ = 0.5);
–
once the application is running at a load defined by the designer based on the
required sharing accuracy, the master section has to be located;
–
on the slave sections, the trimmer has to be fixed to equalize the output currents.
DocID8881 Rev 5
L6615
6
Reference
Reference
[1] L6910 - “Adjustable step down controller with synchronous rectification” (datasheet)
[2] L6911 - “5 bit programmable step down controller with synchronous rectification”
(datasheet)
DocID8881 Rev 5
23/26
Package mechanical data
7
L6615
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 22. SO8 mechanical data
mm
Dim.
Min.
Typ.
A
Max.
1.75
A1
0.10
0.25
A2
1.25
b
0.28
0.48
c
0.17
0.23
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
8°
ccc
0.10
Figure 23. SO8 package drawings
0016023_Rev_G
24/26
DocID8881 Rev 5
L6615
8
Revision history
Revision history
Table 6. Document revision history
Date
Revision
14-Jan-2008
4
28-Aug-2013
5
Changes
Updated Table 1: Device summary.
Changed min./max.VOS values from 1.5/1.5 to -2/2 mV in Table 5:
Electrical characteristics.
Minor text changes.
DocID8881 Rev 5
25/26
L6615
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