LD39150DT25-R

LD39150 Ultra low drop BiCMOS voltage regulator Datasheet - production data  Temperature range: -40 to 125 °C  Fast dynamic response to line and load changes  Stable with ceramic capacitor  Available in PPAK, DPAK and DFN6 (3x3 mm) DPAK PPAK Applications  Microprocessor power supply  DSPs power supply  Post regulators for switching suppliers DFN6 (3 x 3 mm)  High efficiency linear regulator Description Features  1.5 A guaranteed output current  Ultra low dropout voltage (200 mV typ. @ 1.5 A load, 40 mV typ. @ 300 mA load)  Very low quiescent current (1 mA typ. @ 1.5 A load, 1 µA max @ 25 °C in off mode)  Logic-controlled electronic shutdown  Current and thermal internal limit  1.5% output voltage tolerance @ 25 °C The LD39150 is a fast ultra low drop linear regulator which operates from 2.5 V to 6 V input supply. A wide range of output options are available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is developed on a BiCMOS process which allows low quiescent current operation independently of output load current.  Fixed and ADJ output voltages: 1.8 V, 2.5 V, 3.3 V, ADJ Table 1. Device summary Order codes Output voltages DPAK (tape and reel) PPAK (tape and reel) DFN LD39150DT18-R 1.8 V LD39150DT25-R 2.5 V LD39150DT33-R 3.3 V LD39150PT-R August 2017 This is information on a product in full production. LD39150PU-R DocID13159 Rev 5 ADJ from 1.22 to 5.0 V 1/26 www.st.com Contents LD39150 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 9 10 2/26 7.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 PPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2 DPAK package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 DFN6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 DPAK and PPAK packaging information . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 DFN6 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID13159 Rev 5 LD39150 1 Diagram Diagram Figure 1. Block diagram (*) Not present on ADJ versions. DocID13159 Rev 5 3/26 26 Pin configuration 2 LD39150 Pin configuration Figure 2. Pin connections (top view for DPAK and PPAK, bottom view for DFN) 6 1 5 TAB 4 5 4 3 2 1 TAB 2 3 3 2 TAB 1 CS24160 CS24140 CS26660 PPAK DFN6 (3 x 3 mm) DPAK Table 2. Pin description Pin n° SYMBOL DFN 5 NOTE PPAK DPAK 5 VSENSE/N.C. For fixed versions: to be connected with LDO output voltage pins for DFN package and not connected on PPAK ADJ For adjustable version: Error amplifier input pin for VO from 1.22 to 5.0 V 3 2 1 VI LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a distance of not more than 0.5’’ from input pin. 4 4 3 VO LDO output voltage pins, with minimum CO = 2.2 µF needed for stability (also refer to CO vs ESR stability chart) 2 1 1 3 2 6 TAB Exp. Pad 4/26 TAB VINH Inhibit input voltage: ON MODE when VINH  2 V, OFF MODE when VINH  0.3 V (Do not leave floating, not internally pulled down/up) GND Common ground N.C. Not connected GND Electrically connected to GND Connect to GND (it is not a power GND) DocID13159 Rev 5 LD39150 3 Typical application circuits Typical application circuits (CI and CO capacitors must be placed as close as possible to the IC pins) Figure 3. LD39150 fixed version with inhibit Note: Inhibit pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3 V. Figure 4. LD39150 adjustable version VO = VREF (1 + R1/R2) Note: Set R2 as close as possible to 4.7 k DocID13159 Rev 5 5/26 26 Typical application circuits LD39150 Figure 5. LD39150 DPAK Figure 6. Timing diagram 6/26 DocID13159 Rev 5 LD39150 4 Maximum ratings Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit -0.3 to 6.5 V INHIBIT input voltage -0.3 to VI +0.3 (6.5 V max) V DC output voltage -0.3 to VI +0.3 (6.5 V max) V VADJ ADJ pin voltage -0.3 to VI +0.3 (6.5 V max) V IO Output current Internally limited mA PD Power dissipation Internally limited mW VI VINH VO Parameter DC input voltage TSTG Storage temperature range -50 to 150 °C TOP Operating junction temperature range -40 to 125 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Symbol Parameter RthJA Thermal resistance junction-ambient RthJC Thermal resistance junction-case PPAK DPAK DFN (1) Unit 100 100 40 °C/W 8 8 10 °C/W 1. With PCB ground plane heatsink. DocID13159 Rev 5 7/26 26 Electrical characteristics 5 LD39150 Electrical characteristics TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = 2 V, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter VI Operating input voltage VO Output voltage tolerance VREF Reference voltage VO Output voltage LINE regulation VO/ILOAD Output voltage LOAD regulation VDROP IQ Dropout voltage (VI - VO) Parameter Min. Typ. Max. Unit 2.5 6 V VI = VO+1V, ILOAD = 10mA to 1.5A -1.5 1.5 VI = VO+1V to 6V, TJ = -40 to 125°C ILOAD = 10mA to 1.5A -3 3 % of VO(NOM) 1.22 V VI = VO+1V to 6V 0.04 % VI = VO+1V to 6V, TJ = -40 to 125°C 0.1 ILOAD = 10mA to 1.5A 0.06 ILOAD = 10mA to 1.5A, TJ = -40 to 125°C 0.2 0.4 ILOAD = 300mA, TJ=-40 to 125°C 40 80 ILOAD = 1.5A, TJ = -40 to 125°C 200 400 1 2.5 0.2 Quiescent current: ON MODE ILOAD = 10mA to 1.5A, VINH = 2V TJ = -40 to 125°C Quiescent current: OFF MODE VINH = 0.3V 1 VINH = 0.3V, TJ = -40 to 125°C 5 % %/A mV mA µA Short-circuit protection ISC Short-circuit protection RL = 0 3 Inhibit threshold LOW Inhibit threshold HIGH VI = 2.5 to 6V OFF TJ = -40 to 125°C TD-OFF Current limit ILOAD = 1.5A, VO = 3.3V 15 TD-ON Current limit ILOAD = 1.5A, VO = 3.3V 15 Inhibit input current (1) VI = 6V, VINH = 0 to 6V 0.1 A Inhibit input VINH IINH 0.3 2 V µs 1 µA AC parameters SVR eN TSHDN Supply voltage rejection VI = 4.5  1V, VO = 3.3V, ILOAD = 10mA, Output noise voltage BW = 10Hz to 100kHz, CO = 2.2µF, VO = 2.5V f = 120Hz 65 f = 1kHz 55 Thermal shutdown OFF 170 Hysteresis 10 1. Guaranteed by design 8/26 100 DocID13159 Rev 5 dB µVRMS °C LD39150 6 Typical performance characteristics Typical performance characteristics TJ = 25 °C, VI = VO + 1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = VI, unless otherwise specified. Figure 7. Output voltage vs temperature Figure 8. Dropout voltage vs temperature Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs supply voltage Figure 11. Quiescent current vs temperature Figure 12. Quiescent current vs temperature DocID13159 Rev 5 9/26 26 Typical performance characteristics LD39150 Figure 13. Short circuit current vs temperature Figure 14. Output voltage vs input voltage Figure 15. Stability region vs CO & ESR (at 100 kHz) Figure 16. Stability region vs CO & low ESR (at 100 kHz) Figure 17. Load transient Figure 18. Line transient VI = 3.5V, IO = 10mA to 1.5A, CI = 1µF, CO = 2.2µF 10/26 VI = 3.5V to 5.5V, ILOAD = 10mA, CO = 2.2µF DocID13159 Rev 5 LD39150 Application notes 7 Application notes 7.1 External capacitors The LD39150 requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 15 and Figure 16). The input/output capacitors must be located less than 1cm from the relative pins and connected directly to the input/output ground pins using traces which have no other currents flowing through them. 7.2 Input capacitor An input capacitor whose minimum value is 1 µF is required with the LD39150 (amount of capacitance can be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin of the device and returned to a clean analog ground. Any good quality ceramic, tantalum or film capacitors can be used for this capacitor. 7.3 Output capacitor It is possible to use ceramic or tantalum capacitors but the output capacitor must meet the requirement for minimum amount of capacitance and ESR (equivalent series resistance) value. A minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the regulator. Anyway, other CO values can be used according to the (Figure 15 and Figure 16) showing the allowable ESR range as a function of the output capacitance. This curve represents the stability region over the full temperature and IO range. 7.4 Thermal note The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Also, capacitors tolerance and variation with temperature must be kept in consideration in order to assure the minimum amount of capacitance at all times. 7.5 Inhibit input operation The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically reducing the current consumption down to less than 1 µA. When the inhibit feature is not used, this pin must be tied to VI to keep the regulator output ON at all times. To assure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section (VIH VIL). The inhibit pin must not be left floating because it is not internally pulled down/up. DocID13159 Rev 5 11/26 26 Package information 8 LD39150 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 12/26 DocID13159 Rev 5 LD39150 8.1 Package information PPAK package information Figure 19. PPAK outline 0078180_F DocID13159 Rev 5 13/26 26 Package information LD39150 Table 6. PPAK mechanical data mm Dim. Min. Max. A 2.2 2.4 A1 0.9 1.1 A2 0.03 0.23 B 0.4 0.6 B2 5.2 5.4 C 0.45 0.6 C2 0.48 0.6 D 6 6.2 D1 E 5.1 6.4 6.6 E1 4.7 e 1.27 G 4.9 5.25 G1 2.38 2.7 H 9.35 10.1 L2 0.8 L4 0.6 L5 1 2.8 R 0.20 0° DocID13159 Rev 5 1 1 L6 V2 14/26 Typ. 8° LD39150 8.2 Package information DPAK package information Figure 20. DPAK (TO-252) type A outline 0068772_K_type_A DocID13159 Rev 5 15/26 26 Package information LD39150 Table 7. DPAK (TO-252) type A mechanical data mm Dim. Min. Typ. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 E 5.10 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R V2 16/26 Max. 0.20 0° 8° DocID13159 Rev 5 LD39150 Package information Figure 21. DPAK footprint (a) Footprint_REV_K a. All dimensions are in millimeters DocID13159 Rev 5 17/26 26 Package information 8.3 LD39150 DFN6 package information Figure 22. DFN6 (3 x 3 mm) outline 18/26 DocID13159 Rev 5 LD39150 Package information Table 8. DFN6 (3 x 3 mm) mechanical data mm Dim. Min. A 0.80 A1 0 Typ. Max. 1 0.02 A3 0.05 0.20 b 0.23 D 2.90 D2 2.23 E 2.90 E2 1.50 0.45 3 3.10 2.50 3 3.10 1.75 0.95 L 0.30 0.40 DocID13159 Rev 5 0.50 19/26 26 Package information LD39150 Figure 23. DFN6 footprint (dimensions in mm) 20/26 DocID13159 Rev 5 LD39150 Packaging information 9 Packaging information 9.1 DPAK and PPAK packaging information Figure 24. Tape for PPAK and DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DocID13159 Rev 5 21/26 26 Packaging information LD39150 Figure 25. Reel for PPAK and DPAK (TO-252) T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius G measured at hub Tape slot in core for tape start 25 mm min. width AM08851v2 Table 9. PPAK and DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 22/26 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID13159 Rev 5 18.4 22.4 LD39150 9.2 Packaging information DFN6 packaging information Figure 26. Tape for DFN6 DocID13159 Rev 5 23/26 26 Packaging information LD39150 Figure 27. Reel for DFN6 Table 10. DFN6 tape and reel mechanical data mm Dim. 24/26 Min. Typ. Max. A0 3.20 3.30 3.40 B0 3.20 3.30 3.40 K0 1 1.10 1.20 DocID13159 Rev 5 LD39150 10 Revision history Revision history Table 11. Document revision history Date Revision Changes 26-Jan-2007 1 Initial release. 12-Jan-2009 2 Removed: package DFN8 (4 x 4 mm) and added package DFN6 (3 x 3 mm). 29-Jan-2013 3 Updated: Table 1 on page 1. 14-Jan-2014 4 Document name changed from LD39150XX to LD39150. Updated Section 8: Package mechanical data. Added Section 9: Packaging mechanical data Minor text changes in title, in features and description in cover page. 30-Aug-2017 5 Removed the following order codes from Table 1: Device summary: LD39150PT18-R, LD39150PT25-R, LD39150PT33-R, LD39150PU18R, LD39150PU25R, and LD39150PU33R DocID13159 Rev 5 25/26 26 LD39150 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 26/26 DocID13159 Rev 5