M74HCT373RM13TR

M74HCT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 19ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 DESCRIPTION The M74HCT373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with sub-micron silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic ) (s t c u d o r DIP PACKAGE TUBE t e l o s b O TSSOP u d o r P e ORDER CODES DIP SOP TSSOP ) s ( ct SOP M74HCT373B1R M74HCT373M1R T&R M74HCT373RM13TR M74HCT373TTR level) and when OE is in high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. P e t e l o s b O PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HCT373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 Q0 to Q7 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs LE GND VCC NAME AND FUNCTION Latch Enable Input Ground (0V) Positive Supply Voltage ) s ( ct TRUTH TABLE du INPUTS OUTPUTS OE LE D H L L L X L H H X X L H s b O X: Don’t Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. ) (s LOGIC DIAGRAM t c u d o r P e t e l o s b O 2/11 t e l o P e ro Q Z NO CHANGE (*) L H M74HCT373 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA 500(*) mW VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ) s ( t -65 to +150 300 c u d °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC e t e l Parameter Supply Voltage o s b VI Input Voltage VO Output Voltage Top Operating Temperature tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) s ( t c O ) o r P Value Unit 4.5 to 5.5 V 0 to VCC V 0 to VCC V -55 to 125 °C 0 to 500 ns u d o r P e t e l o s b O 3/11 M74HCT373 DC SPECIFICATIONS Test Condition Symbol VIH Parameter High Level Input Voltage VIL Low Level Input Voltage VOH VOL II IOZ ICC ∆ ICC TA = 25°C VCC (V) Min. 4.5 to 5.5 4.5 to 5.5 High Level Output Voltage 4.5 Low Level Output Voltage 4.5 Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Additional Worst Case Supply Current s b O 4/11 Max. -40 to 85°C -55 to 125°C Min. Min. Max. 2.0 0.8 4.4 4.5 4.4 4.4 IO=-6.0 mA 4.18 4.31 4.13 4.10 0.0 0.1 IO=6.0 mA 0.17 0.26 VI = VCC or GND ± 0.1 5.5 VI = VIH or VIL VO = VCC or GND 5.5 VI = VCC or GND 5.5 Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 ) (s 0.1 V (s) ct u d o 0.33 V 0.1 0.40 V V ±1 ±1 µA ± 0.5 ±5 ± 10 µA 4 40 80 µA 2.0 2.9 3.0 mA r P e t e l o s b O Max. 0.8 IO=-20 µA IO=20 µA Unit 2.0 0.8 5.5 d o r t e l o Typ. 2.0 t c u P e Value M74HCT373 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (LE - Q) tPLH tPHL Propagation Delay Time (D - Q) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time tW(H) Minimum Pulse Width (LE) Minimum Set-up ts Time Minimum Hold th Time VCC (V) CL (pF) 4.5 4.5 4.5 4.5 Value TA = 25°C 7 12 15 18 50 20 30 38 45 150 24 37 46 56 50 19 30 38 45 150 23 36 45 50 20 30 38 24 37 46 20 30 RL = 1 KΩ 150 50 4.5 50 4.5 50 4.5 50 RL = 1 KΩ ol 4 ) (s s b O ro P e CIN Input Capacitance CPD Power Dissipation Capacitance (note 1) o s b let Max. Unit Max. ns ns ) s ( ct ns 54 45 du ns 56 45 ns 15 o r P 19 22 ns 10 13 15 ns 5 5 8 ns ete 8 ct du VCC (V) Min. 50 Test Condition Parameter Min. Max. CAPACITIVE CHARACTERISTICS Symbol -55 to 125°C Typ. 4.5 Min. -40 to 85°C 38 Value TA = 25°C Min. Typ. Max. 5 10 66 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 32 + 34 x n (pF) O 5/11 M74HCT373 TEST CIRCUIT ) s ( ct u d o TEST tPLH, tPHL tPZL, tPLZ e t e ol tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) s b O Pr SWITCH Open VCC GND WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) ) (s t c u d o r P e t e l o s b O 6/11 M74HCT373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 7/11 M74HCT373 Plastic DIP-20 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.254 B 1.39 TYP MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D ) s ( ct 25.4 E 8.5 e 2.54 e3 22.86 u d o 0.335 7.1 I 3.93 s ( t c 1.34 e t e ol bs O ) 3.3 Z Pr 0.100 F L 1.000 0.900 0.280 0.155 0.130 0.053 u d o r P e t e l o s b O P001J 8/11 M74HCT373 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. a1 2.65 MAX. 0.1 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 0.019 ) s ( ct 0.012 0.020 c1 u d o 45° (typ.) D 12.60 13.00 0.496 E 10.00 10.65 0.393 e 1.27 e3 11.43 F 7.40 7.60 L 0.50 1.27 M ) (s S e t e ol s b O 0.75 Pr 0.512 0.419 0.050 0.450 0.291 0.300 0.020 0.050 0.029 8° (max.) t c u d o r P e t e l o s b O PO13L 9/11 M74HCT373 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 6.4 6.5 6.6 0.252 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 1 e bs 0.65 BSC K 0° L 0.45 let o s b 0.60 s ( t c 0.75 du ro P e A2 A1 b 0.260 0.252 0.260 0.173 0.176 0.0256 BSC 0° 8° 0.018 0.024 O K e 0.030 L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/11 0.0089 0.256 u d o r P e A O ) 8° 0.012 t e l o 0.169 ) s ( ct M74HCT373 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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