ST72F60E1M1

ST7260xx Low speed USB 8-bit MCU family with up to 8K Flash and serial communications interface Features ■ ■ ■ Memories – 4 or 8 Kbytes program memory: high density Flash (HDFlash), or FastROM with readout and write protection – In-application programming (IAP) and incircuit programming (ICP) – 384 bytes RAM memory (128-byte stack) Clock, reset and supply management – Run, Wait, Slow and Halt CPU modes – 12 or 24 MHz oscillator – RAM Retention mode – Optional low voltage detector (LVD) ■ O ) u d o O r P e let e t le o r P 2 timers – Programmable Watchdog – 16-bit Timer with 2 Input Captures, 2 Output Compares, PWM output and clock input ■ Communications interface – Asynchronous serial communications interface (SCI) ■ Instruction set – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction ■ Development tools – Versatile development tools including , software library, hardware emulator, programming boards, HID and DFU software layer Up to 19 I/O ports – Up to 8 high sink I/Os (10 mA at 1.3 V) Table 1. c u d o s b USB (Universal Serial Bus) interface – DMA for low speed applications compliant with USB 1.5 Mbs (version 2.0) and HID specifications (version 1.0) – Integrated 3.3 V voltage regulator and transceivers – Supports USB DFU class specification – Suspend and Resume operations – 3 Endpoints with programmable In/Out configuration o s b ) s t( – 2 very high sink true open drain I/Os (25 mA at 1.5 V) – Up to 8 lines with interrupt capability s ( t c ■ QFN40 (6x6) SO24 Device summary Features ST7260K2 ST7260K1 ST7260E2 ST7260E1 Flash program memory bytes 8K 4K 8K 4K RAM (stack) - bytes Peripherals 384 (128) Watchdog timer, 16-bit timer, USB, SCI Operating supply CPU frequency 4.0 V to 5.5 V 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator) Operating temperature Packages February 2009 0 °C to +70 °C QFN40 (6x6) Rev 3 SO24 1/139 www.st.com 139 Contents ST7260xx Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ) s t( c u d 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 e t le 5.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 o s b 5.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 O ) 5.7.1 6 s b O 2/139 s ( t c Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 u d o r P e Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 t e l o 7 o r P 6.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.5 Stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.2 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ST7260xx Contents 7.3 8 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.0.1 9 Interrupt register (ITRFRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.4 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ) s t( c u d o r P I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 e t le 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 o s b 10.2.1 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2.2 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.2.3 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 O ) s ( t c u d o Data register (PxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.2.6 Data direction register (PxDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 r P e t e l o 11 s b O 12 10.2.5 Miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3.1 Software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3.2 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.4 Using Halt mode with the WDG (option) . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.3.6 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3/139 Contents ST7260xx 12.4 13 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.4.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.4.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ) s t( Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . 71 c u d 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.3 o r P 13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.2.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.2.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 e t le o s b Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 O ) 13.3.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.3.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 s ( t c u d o 14 4/139 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.3.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 r P e USB interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 t e l o s b O 13.3.4 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.1 DMA address register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.2 Interrupt/DMA register (IDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.4.3 PID register (PIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.4.4 Interrupt status register (ISTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.4.5 Interrupt mask register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.4.6 Control register (CTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.4.7 Device address register (DADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.4.8 Endpoint n register A (EPnRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ST7260xx Contents 14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5 15 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15.1 15.2 16 ) s t( ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 c u d 15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 e t le o r P o s b O ) Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 s ( t c Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1 s b O e t e ol Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 u d o 16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Pr 16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113 16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.6 16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5/139 Contents ST7260xx 16.7 16.8 16.9 17 16.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 118 16.7.2 Designing hardened software to avoid noise problems . . . . . . . . . . . . 118 16.7.3 Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 119 16.7.4 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 119 16.7.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ) s t( I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 c u d Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 o r P 16.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 16.9.2 USB - universal bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.9.3 SCI - serial communications interface . . . . . . . . . . . . . . . . . . . . . . . . . 128 e t le o s b Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17.1 17.1.1 18 O ) Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 s ( t c Device configuration and ordering information . . . . . . . . . . . . . . . . . 131 u d o 18.1 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 18.2 Device ordering information and transfer of customer code . . . . . . . . . . 132 r P e t e l o 18.3 s b O 19 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.1 PA2 limitation with OCMP1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 19.3 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 20 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6/139 ST7260xx 1 Description Description The ST7260xx devices are members of the ST7 microcontroller family designed for USB applications running from 4.0 to 5.5 V. Different package options offer up to 19 I/O pins. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code. The on-chip peripherals include a low speed USB interface and an asynchronous SCI interface. For power economy, the microcontroller can switch dynamically into, Slow, Wait, Active Halt or Halt mode when the application is in idle or stand-by state. ) s t( c u d Typical applications include consumer, home, office and industrial products. e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O 7/139 Block diagram 2 ST7260xx Block diagram Figure 1. General block diagram INTERNAL CLOCK OSC/3 OSCIN OSCILLATOR OSCOUT OSC/4 or OSC/2 for USB1) VDD VSS 8-BIT CORE ALU O ) PROGRAM MEMORY (8 Kbytes) s ( t c VDDA u d o VSSA r P e t e l o bs O 8/139 1) 12 o r P PORT B e t le o s b LVD VPP/TEST ADDRESS AND DATA BUS CONTROL USB DMA c u d 16-bit TIMER WATCHDOG RESET ) s t( PORT A POWER SUPPLY PA[7:0] (8 bits) PB[7:0] (8 bits) PORT C SCI (UART) PC[2:0] (3 bits) USB SIE USBDP USBDM USBVCC RAM (384 bytes) or 24 MHz OSCIN frequency required to generate 6 MHz USB clock. ST7260xx Pin description NC NC NC NC NC NC NC NC PA2(25 mA)/ICCCLK 40-lead QFN package pinout PA1(25 mA)/ICCDATA 40 39 38 37 36 35 34 33 32 31 PA0/MCO 1 30 PA3/EXTCLK VSSA 2 29 PA4/ICAP1/IT1 USBDP 3 28 PA5/ICAP2/IT2 USBDM 27 PA6/OCMP1/IT3 5 26 PA7/OCMP2/IT4 VDDA 6 25 PB0(10 mA) VDD 7 24 PB1(10 mA) 23 PB2(10 mA) r P e Ob so let 15 16 17 18 19 20 IT6/PB5(10 mA) 14 VPP/TEST 13 IT7/PB6(10 mA) u d o USBOE/PC2 ) s ( ct -O 12 IT8/PB7(10 mA) 10 11 Note: NC=Do not connect bs 9 NC VSS NC OSCIN ol 8 RESET OSCOUT Figure 3. o r P 4 e t e ) s t( c u d USBVCC RDI/PC0 Figure 2. TDO/PC1 3 Pin description 22 PB3(10 mA) 21 PB4(10 mA)/IT5 24-pin SO package pinout VDD OSCOUT OSCIN 1 24 2 23 3 22 VSS 4 21 TDO/PC1 RDI/PC0 RESET/ IT7/PB6(10mA) 5 20 VPP/TEST PB3(10 mA) USBVcc USBDM USBDP VSSA PA0/MCO 6 19 PA1(25 mA)/ICCDATA 7 18 8 17 PA2(25 mA)/ICCCLK PA3/EXTCLK 9 16 PA4/ICAP1/IT1 10 15 PB2(10 mA) 11 14 USBOE/PB1(10 mA) 12 13 PA5/ICAP2/IT2 PA7/OCMP2/IT4 PB0(10 mA) 9/139 Pin description ST7260xx RESET (see Note 1): Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog is triggered or the VDD is low. It can be used to reset external peripherals. OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. VDD/VSS (see Note 2): Main power supply and ground voltages. VDDA/VSSA (see Note 2): Power supply and ground voltages for analog peripherals. Alternate functions: Several pins of the I/O ports assume software programmable alternate functions as shown in the pin description. Note: 1 Note 1: Adding two 100 nF decoupling capacitors on the Reset pin (respectively connected to VDD and VSS) will significantly improve product electromagnetic susceptibility performance. 2 To enhance the reliability of operation, it is recommended that VDDA and VDD be connected together on the application board. This also applies to VSSA and VSS. 3 The USBOE alternate function is mapped on Port C2 in QFN40 devices. In SO24 devices it is mapped on Port B1. 4 The timer OCMP1 alternate function is mapped on Port A6 in QFN40 pin devices. In SO24 devices it is not available. ) s t( c u d e t le o r P o s b Legend / abbreviations for Figure 2, Figure 3 and Table 2, Table 3: Type: I = input, O = output, S = supply O ) In/Output level: CT = CMOS 0.3 VDD / 0.7 VDD with input trigger Output level: s ( t c 10 mA = 10 mA high sink (Fn N-buffer only) 25 mA = 25 mA very high sink (on N-buffer only) u d o Port and control configuration: ● Input: ● Output: e t e ol Pr float = floating, wpu = weak pull-up, int = interrupt OD = open drain, PP = push-pull, T = True open drain The RESET configuration of each pin is shown in bold. This configuration is kept as long as the device is under reset state. s b O 10/139 ST7260xx Pin description ) Device pin description (QFN40) X int VSSA 3 USBDP I/O USB bidirectional data (data +) 4 USBDM I/O USB bidirectional data (data -) 5 USBVCC O USB power supply 6 VDDA S Analog supply voltage 7 VDD S Power supply voltage (4V - 5.5V) 8 OSCOUT O Oscillator output 9 OSCIN I Oscillator input 10 VSS S 11 PC2/USBOE I/O CT 12 PC1/TDO I/O CT 13 PC0/RDI I/O CT 14 RESET I/O 15 NC 16 NC 17 PB7/IT8 18 e t e ol S Pr VPP/TEST Main Clock Output Analog ground ) s t( c u d e t le o r P Digital ground ) s ( ct u d o -- Port A0 Alternate function 2 20 X Main function (after reset) PA0/MCO 19 CT PP Output OD Input 1 PB6/IT7 I/O Port / control float Output Pin name Input Pin n° Type Level wpu Table 2. so X b O X X X X Port C2 USB Output Enable X Port C1 SCI Transmit Data Output X Port C0 SCI Receive Data Input X Reset Not connected -- Not connected I/O CT 10 mA X X X Port B7 I/O CT 10 mA X X X Port B6 S Programming supply PB5/IT6 I/O CT 10 mA X X X Port B5 PB4/IT5 I/O CT 10 mA X X X Port B4 22 PB3 I/O CT 10 mA X X Port B3 23 PB2 I/O CT 10 mA X X Port B2 24 PB1 I/O CT 10 mA X X Port B1 25 PB0 I/O CT 10 mA X X Port B0 26 PA7/OCMP2/IT4 I/O CT X X X Port A7 Timer Output Compare 2 27 PA6/OCMP1/IT3 I/O CT X X X Port A6 Timer Output Compare 1 28 PA5/ICAP2/IT2 I/O CT X X X Port A5 Timer Input Capture 2 29 PA4/ICAP1/IT1 I/O CT X X X Port A4 Timer Input Capture 1 s b O 21 11/139 Pin description Device pin description (QFN40) (continued) Port / control CT Alternate function PA3/EXTCLK I/O 31 PA2/ICCCLK I/O 32 NC -- Do not connect 33 NC -- Do not connect 34 NC -- Do not connect 35 NC -- Do not connect 36 NC -- Do not connect 37 NC -- Do not connect 38 NC -- Do not connect 39 NC -- 40 PA1/ICCDATA 25 mA X T 25 mA s ( t c u d o s b O 12/139 Timer External Clock Port A2 ICC Clock e t le o r P Do not connect X T o s b O ) t e l o Port A3 ) s t( c u d I/O CT r P e X Main function (after reset) 30 CT X PP OD Output int Input float Output Pin name Input Pin n° Type Level wpu Table 2. ST7260xx Port A1 ICC Data ST7260xx Device pin description (SO24) Port / control PP OD Output int float Input Main function (after reset) Alternate function 1 VDD S Power supply voltage (4 V - 5.5 V) 2 OSCOUT O Oscillator output 3 OSCIN I Oscillator input 4 VSS S Digital ground 5 PC1/TDO I/O 6 PC0/RDI 7 X X Port C1 I/O CT X X Port C0 RESET I/O X 8 PB6/IT7 I/O CT 10 mA 9 VPP/TEST 10 PB3 I/O CT 10 mA X 11 PB2 I/O CT 10 mA 12 PB1/USBOE I/O CT 10 mA 13 PB0 14 PA7/OCMP2/IT4 15 PA5/ICAP2/IT2 e t e l CT ) (s t c u od I/O CT 10 mA Pr e t le X so X S o s b O Output Pin name Input Pin n° Type Level wpu Table 3. Pin description X Ob X ) s t( o r P c u d SCI Transmit Data Output SCI Receive Data Input Reset Port B6 Programming supply X Port B3 X X Port B2 X X Port B1 X X Port B0 USB Output Enable I/O CT X X X Port A7 Timer Output Compare 2 I/O CT X X X Port A5 Timer Input Capture 2 X X Port A4 Timer Input Capture 1 X Port A3 Timer External Clock 16 PA4/ICAP1/IT1 I/O CT X 17 PA3/EXTCLK I/O CT X 18 PA2/ICCCLK I/O CT 25 mA X T Port A2 ICC Clock 19 PA1/ICCDATA I/O CT 25 mA X T Port A1 ICC Data 20 PA0/MCO I/O Port A0 Main Clock Output 21 VSSA 22 USBDP I/O USB bidirectional data (data +) 23 USBDM I/O USB bidirectional data (data -) 24 USBVCC O USB power supply S CT X X Analog ground 13/139 Register & memory map 4 ST7260xx Register & memory map As shown in Figure 4, the MCU is capable of addressing 8 Kbytes of memories and I/O registers. The available memory locations consist of up to 384 bytes of RAM including 64 bytes of register locations, and up to 8 Kbytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Note: ) s t( Important: memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device. Figure 4. c u d Memory map o r P 0040h 0000h HW registers (See Table 5) 003Fh 0040h e t le so RAM (384 Bytes) 01BFh 01C0h )- Ob 7FFFh 8000h Stack (128 Bytes) 017Fh 0180h 16-bit addressing RAM s ( t c Reserved 00FFh 0100h Short addressing RAM (192 bytes) 01BFh u d o Program memory (4 / 8 KBytes) r P e FFDFh FFE0h t e l o FFFFh bs O 14/139 Interrupt & reset vectors (See Table 4) E000h 8 KBytes F000h FFDFh 4 KBytes ST7260xx Table 4. Register & memory map . Interrupt vector map Vector address Description FFE0h-FFEDh FFEEh-FFEFh FFF0h-FFF1h FFF2h-FFF3h FFF4h-FFF5h FFF6h-FFF7h FFF8h-FFF9h FFFAh-FFFBh FFFCh-FFFDh FFFEh-FFFFh Reserved area USB interrupt vector SCI interrupt vector Reserved area TIMER interrupt vector IT1 to IT8 interrupt vector USB end suspend mode interrupt vector Flash start programming interrupt vector TRAP (software) interrupt vector RESET vector Table 5. Remarks Exit from Halt mode I- bit I- bit Internal interrupt Internal interrupt No No I- bit I- bit I- bit I- bit None None Internal interrupt External interrupt External interrupts Internal interrupt CPU interrupt No Yes Yes Yes No Yes Hardware register memory map R/W R/W Port B Data Register Port B Data Direction Register 00h 00h R/W R/W Port C Data Register Port C Data Direction Register 1111 x000b 1111 x000b R/W R/W Register name 0000h 0001h Port A PADR PADDR Port A Data Register Port A Data Direction Register 0002h 0003h Port B PBDR PBDDR 0004h 0005h Port C PCDR PCDDR 0009h MISC r P e t e l o 000Ah to 000Bh bs 000Ch 000Dh to 0010h WDG e t le o s b O ) s ( t c u d o o r P 00h 00h Register label ITC c u d Remarks Block 0008h ) s t( Reset status Address 0006h to 0007h O Masked by Reserved (2 bytes) ITIFRE Interrupt Register 00h R/W MISCR Miscellaneous Register 00h R/W 7Fh R/W Reserved (2 bytes) WDGCR Watchdog Control Register Reserved (4 bytes) 15/139 Register & memory map Table 5. Address 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h ST7260xx Hardware register memory map (continued) Block Register label Register name Reset status Remarks TIM TCR2 TCR1 TCSR TIC1HR TIC1LR TOC1HR TOC1LR TCHR TCLR TACHR TACLR TIC2HR TIC2LR TOC2HR TOC2LR Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture High Register 1 Timer Input Capture Low Register 1 Timer Output Compare High Register 1 Timer Output Compare Low Register 1 Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture High Register 2 Timer Input Capture Low Register 2 Timer Output Compare High Register 2 Timer Output Compare Low Register 2 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only R/W Read only R/W Read only Read only R/W R/W SCISR SCIDR SCIBRR SCICR1 SCICR2 SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 C0h xxh 00h x000 0000b 00h Read only R/W R/W R/W R/W USB PID Register USB DMA address Register USB Interrupt/DMA Register USB Interrupt Status Register USB Interrupt Mask Register USB Control Register USB Device Address Register USB Endpoint 0 Register A USB Endpoint 0 Register B USB Endpoint 1 Register A USB Endpoint 1 Register B USB Endpoint 2 Register A USB Endpoint 2 Register B x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb Read only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h R/W SCI USBPIDR USBDMAR USBIDR USBISTR USBIMR USBCTLR USBDADDR USBEP0RA USBEP0RB USBEP1RA USBEP1RB USBEP2RA USBEP2RB u d o r P e USB s b O 0032h 0036h 0038h to 003Fh 16/139 o s b O ) s ( t c t e l o 0037h e t le ) s t( c u d o r P Reserved (5 Bytes) Flash FCSR Flash Control /Status Register Reserved (8 bytes) ST7260xx Flash program memory 5 Flash program memory 5.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-bybyte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming). The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 5.2 ) s t( c u d Main features ● 3 Flash programming modes: o r P – Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. – ICP (in-circuit programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. – IAP (in-application programming). In this mode, all sectors, except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. e t le o s b O ) ● ICT (in-circuit testing) for downloading and executing user application test patterns in RAM ● Readout protection ● Register Access Security System (RASS) to prevent accidental programming or erasing s ( t c u d o 5.3 r P Structure e t e ol s b O The Flash memory is organized in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (seeTable 6). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). Table 6. Sectors available in Flash devices Flash size (bytes) Available sectors 4K Sector 0 8K Sectors 0, 1 >8K Sectors 0, 1, 2 17/139 Flash program memory 5.3.1 ST7260xx Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased. Readout protection is enabled and removed through the FMP_R bit in the option byte. Figure 5. Memory map and sector address 8K 32K 16K Flash memory size c u d 7FFFh 8 Kbytes DFFFh 4 Kbytes l o s FFFFh ) s ( ct u d o s b O 18/139 b O - 24 Kbytes e t e 4 Kbytes EFFFh t e l o o r P Sector 2 BFFFh r P e ) s t( Sector 1 Sector 0 ST7260xx 5.4 Flash program memory ICC interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 6). These pins are: – RESET: device reset – VSS: device power supply ground – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/VPP: programming voltage – OSC1 (or OSCIN): main clock input for external source (optional) – VDD: application board power supply (see Figure 6, Note 3). Figure 6. Typical ICC interface c u d Programming tool ICC connector Optional (see note 4) ol 9 7 5 10 8 6 bs -O 3 1 4 2 o r P Application board ICC connector HE10 connector type Application reset source See note 2 10kΩ ICCDATA RESET ST7 ICCCLK VSS See note 1 ICCSEL/VPP r P e OSC1 VDD u d o OSC2 ) s ( ct Application power supply e t e ICC cable (See note 3) ) s t( Application I/O s b O t e l o 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (PUSH-pull output or pull-up resistor 1K or a reset management IC with open drain output and pull-up resistor >1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. 4. Pin 9 has to be connected to the OSC1 (OSCIN) pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case. 19/139 Flash program memory 5.5 ST7260xx ICP (in-circuit programming) To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 6). For more details on the pin locations, refer to the device pinout description. 5.6 ) s t( c u d IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). o r P This mode is fully controlled by user software. This allows it to be adapted to the user application, (such as user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored). For example, it is possible to download code from the SCI, or USB interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. e t le o s b 5.7 O Related documentation ) s ( t c u d o r P e t e ol For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 5.7.1 Flash control/status register (FCSR) This register is reserved for use by programming tool software. It controls the Flash programming and erasing operations. bs O 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 7. Flash control/status register address and reset value Address (Hex) 0037h 20/139 Reset value:0000 0000 (00h) FCSR Register label 7 6 5 4 3 2 1 0 FCSR reset value 0 0 0 0 0 0 0 0 ST7260xx Central processing unit (CPU) 6 Central processing unit (CPU) 6.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation. 6.2 6.3 Main features ● 63 basic instructions ● Fast 8-bit by 8-bit multiply ● 17 main addressing modes ● Two 8-bit index registers ● 16-bit stack pointer ● Low power modes ● Maskable hardware interrupts ● Non-maskable software interrupt ) s t( c u d e t le o r P o s b CPU registers O ) The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. s ( t c Figure 7. CPU registers du ro let so Ob P e 7 0 Accumulator Reset value = XXh 7 0 X index register Reset value = XXh 7 0 Y index register Reset value = XXh 15 PCH 8 7 PCL 0 Program counter Reset value = reset vector @ FFFEh-FFFFh 7 0 1 1 1 H I N Z C Reset value = 1 1 1 X 1 X X X 15 8 7 Condition code register 0 Stack pointer Reset value = stack higher address X = undefined value 21/139 Central processing unit (CPU) 6.3.1 ST7260xx Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 Index registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). 6.3.3 ) s t( Program counter (PC) c u d The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 6.3.4 e t le Condition code register (CC) o r P The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. o s b s ( t c CC 7 6 du 1 1 o r P Table 8. e t e ol 22/139 4 5 1 Reset value: 111x1xxx 4 3 2 1 0 H I N Z C R/W R/W R/W R/W R/W CC register description BIt Name s b O O ) Function Half carry H This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. ST7260xx Central processing unit (CPU) Table 8. CC register description BIt Name 3 I Function Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine ) s t( c u d 2 N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1. This bit is accessed by the JRMI and JRPL instructions. e t le 1 Z o r P o s b Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. O ) s ( t c Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions. u d o r P e 0 t e l o C s b O 23/139 Central processing unit (CPU) 6.3.5 ST7260xx Stack pointer register (SP) SP Reset value: 01 7Fh 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 1 0 6 5 4 3 2 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). ) s t( Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. c u d The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD instruction. Note: o r P When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. e t le o s b The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. O ) s ( t c ● When an interrupt is received, the SP is decremented and the context is pushed on the stack. ● On return from interrupt, the SP is incremented and the context is popped from the stack. u d o r P e A subroutine call occupies two locations and an interrupt five locations in the stack area. let Figure 8. so Ob Stack manipulation example Call subroutine Push Y Interrupt event Pop Y RET or RSP IRET @ 0100h SP SP CC A CC A X X X PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL Stack Higher Address = 017Fh Stack Lower Address = 0100h 24/139 SP PCH SP @ 01FFh Y CC A SP SP ST7260xx Reset and clock management 7 Reset and clock management 7.1 Reset The Reset procedure is used to provide an orderly software start-up or to exit low power modes. Three reset modes are provided: a low voltage (LVD) reset, a watchdog reset and an external reset at the RESET pin. A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point. ) s t( An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active. Caution: 7.2 c u d When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior Low voltage detector (LVD) e t le o r P o s b Low voltage reset circuitry generates a reset when VDD is: ● below VIT+ when VDD is rising, ● below VIT- when VDD is falling. O ) During low voltage reset, the RESET pin is held low, thus permitting the MCU to reset other devices. s ( t c u d o It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. 7.2.1 r P e Watchdog reset t e l o When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices in the same way as the low voltage reset (Figure 9). s b O 7.2.2 External reset The external reset is an active low input signal applied to the RESET pin of the MCU. As shown in Figure 12, the RESET signal must stay low for a minimum of one and a half CPU clock cycles. An internal Schmitt trigger at the RESET pin is provided to improve noise immunity. 25/139 Reset and clock management Figure 9. ST7260xx Low voltage detector functional diagram RESET LOW VOLTAGE DETECTOR VDD INTERNAL RESET FROM WATCHDOG RESET ) s t( Figure 10. Low voltage reset signal output VIT+ VIT- e t le VDD o s b RESET Note: o r P Hysteresis (VIT+-VIT-) = Vhys O ) s ( t c Figure 11. Temporization timing diagram after an internal reset u d o r P e VDD t e l o bs O 26/139 VIT+ Temporization (4096 CPU clock cycles) Addresses $FFFE c u d ST7260xx Reset and clock management Figure 12. Reset timing diagram tDDR VDD OSCIN tOXOV fCPU FFFE PC RESET 4096 CPU CLOCK CYCLES DELAY e t le WATCHDOG RESET ) s t( FFFF c u d o r P o s b Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+, VIT- and Vhys 7.3 Clock system 7.3.1 General description O ) s ( t c u d o The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the external oscillator frequency (fOSC), which is divided by 3 (and by 2 or 4 for USB, depending on the external clock used). The internal clock is further divided by 2 by setting the SMS bit in the Miscellaneous Register. Using the OSC24/12 bit in the option byte, a 12 MHz or a 24 MHz external clock can be used to provide an internal frequency of either 2, 4 or 8 MHz while maintaining a 6 MHz for the USB (refer to Figure 15). r P e s b O t e l o The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for fosc. The circuit shown in Figure 14 is recommended when using a crystal, and Table 9 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. 27/139 Reset and clock management Table 9. ST7260xx Recommended values for 24 MHz crystal resonator Symbol Values RSMAX(1) 20 Ω 25 Ω 70 Ω COSCIN 56pF 47pF 22pF COSCOUT 56pF 47pF 22pF RP 1-10 MΩ 1-10 MΩ 1-10 MΩ 1. RSMAX is the equivalent serial resistor of the crystal (see crystal specification). 7.3.2 External clock ) s t( An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 13. The tOXOV specifications do not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of tOXOV (see Section 16.5: Clock and timing characteristics). c u d Figure 13. External clock source connections e t le o s b OSCIN (s) -O t c u OSCOUT NC EXTERNAL CLOCK d o r Figure 14. Crystal/ceramic resonator P e t e l o s b O 28/139 OSCOUT OSCIN RP COSCIN COSCOUT o r P ST7260xx Reset and clock management Figure 15. Clock block diagram 8, 4 or 2 MHz CPU and peripherals) 0 %2 %3 1 SMS 1 24 or 12 MHz Crystal %2 6 MHz (USB) %2 %2 0 OSC24/12 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O 29/139 Interrupts 8 ST7260xx Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 10: Interrupt mapping and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 16. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). When an interrupt has to be serviced: ) s t( ● Normal processing is suspended at the end of the current instruction execution. ● The PC, X, A and CC registers are saved onto the stack. ● The I bit of the CC register is set to prevent additional interrupts. c u d The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to Table 10: Interrupt mapping for vector addresses). e t le o r P The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: o s b As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. O ) Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. s ( t c In the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see Table 10: Interrupt mapping). u d o Non-maskable software interrupts r P e This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 16. t e l o Interrupts and low power mode bs O All interrupts allow the processor to leave the Wait low power mode. Only external and specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from HALT“ column in Table 10: Interrupt mapping). External interrupts The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE register and if the I bit of the CCR is reset. 30/139 ST7260xx Interrupts Peripheral interrupts Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ● The I bit of the CC register is cleared. ● The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by one of the two following operations: Note: ● Writing “0” to the corresponding bit in the status register. ● Accessing the status register while the flag is set followed by a read or write of an associated register. The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequence is executed. 2 All interrupts allow the processor to leave the Wait low power mode. 3 Exit from Halt mode may only be triggered by an External Interrupt on one of the ITi ports (PA4-PA7 and PB4-PB7), an end suspend mode Interrupt coming from USB peripheral, or a reset. e t le Figure 16. Interrupt processing flowchart o s b FROM RESET O ) s ( t c u d o e t e ol s b O ) s t( 1 Pr BIT I SET N N INTERRUPT Y FETCH NEXT INSTRUCTION IRET Y EXECUTE INSTRUCTION o r P Y N c u d STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT 31/139 Interrupts Table 10. N° ST7260xx Interrupt mapping Source block Description RESET Reset TRAP Software Interrupt FLASH Flash Start Programming Interrupt USB End Suspend Mode Register label Priority order N/A Highest Priority Exit from Halt address yes FFFEh-FFFFh no FFFCh-FFFDh yes FFFAh-FFFBh ISTR Vector FFF8h-FFF9h yes 1 ITi External Interrupts ITRFRE FFF6h-FFF7h 2 TIMER Timer Peripheral Interrupts TIMSR FFF4h-FFF5h 3 Reserved 4 SCI SCI Peripheral Interrupts SCISR 5 USB USB Peripheral Interrupts ISTR 8.0.1 Interrupt register (ITRFRE) 7 6 5 IT8E IT7E IT6E R/W R/W ) s ( ct Table 11. Bit Lowest Priority e t le so ITRFRE R/W ) s t( FFF2h-FFF3h 4 b O IT5E R/W c u d no FFF0h-FFF1h o r P FFEEh-FFEFh Reset value: 0000 0000 (00h) 3 2 1 0 IT4E IT3E IT2E IT1E R/W R/W R/W R/W ITRFRE register description du Name Function ro Interrupt enable control bits If an ITiE bit is set, the corresponding interrupt is generated when: ITiE – a rising edge occurs on the pin PA4/IT1 or PA5/IT2 or PB4/IT5 or PB5/IT6 7:0 (i=1 to or 8) – a falling edge occurs on the pin PA6/IT3 or PA7/IT4 or PB6/IT7 or PB7/IT8 No interrupt is generated elsewhere.. P e t e l o s b O Table 12. Address (Hex.) Register label 0008h 32/139 Interrupt register map and reset values ITRFRE reset value 7 6 5 4 3 2 1 0 IT8E 0 IT7E 0 IT6E 0 IT5E 0 IT4E 0 IT3E 0 IT2E 0 IT1E 0 ST7260xx Power saving modes 9 Power saving modes 9.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET, the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. ) s t( 9.2 c u d Halt mode o r P The MCU consumes the least amount of power in Halt mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. e t le o s b When entering Halt mode, the I bit in the Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active. O ) The MCU can exit Halt mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. s ( t c u d o After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. r P e t e l o s b O 33/139 Power saving modes ST7260xx Figure 17. Halt mode flowchart HALT INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT OFF OFF OFF CLEARED ) s t( N RESET c u d N EXTERNAL INTERRUPT* Y Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT e t le o s b ) s ( ct u d o Note: 9.3 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT r P e Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. t Slow mode e l o s b O 9.4 -O o r P ON ON ON SET In Slow mode, the oscillator frequency can be divided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During Wait mode, the I bit of the CC register is forced to 0 to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. 34/139 ST7260xx Power saving modes The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 18. Related documentation ● AN 980: ST7 keypad decoding techniques, implementing wake-up on keystroke ● AN1014: How to minimize the ST7 power consumption ● AN1605: Using an active RC to wakeup the ST7LITE0 from power saving mode Figure 18. Wait mode flowchart ) s t( WFI INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK ON ON OFF CLEARED I-BIT e t le o s b N c u d o r P RESET N -O INTERRUPT ) s ( ct u d o r P e t e l o s b O Note: Y Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT ON ON ON SET IF RESET 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped. 35/139 I/O ports ST7260xx 10 I/O ports 10.1 Introduction The I/O ports offer different functional modes: ● Transfer of data through digital inputs and outputs and for specific pins ● Alternate signal input/output for the on-chip peripherals ● External interrupt generation An I/O port consists of up to 8 pins. Each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 10.2 ) s t( c u d Functional description Each port is associated to 2 main registers: ● Data register (DR) ● Data direction register (DDR) e t le o r P Each I/O pin may be programmed using the corresponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. Table 13. I/O pin functions O ) DDR t(s 0 uc 1 d o r Input modes o s b Mode Input Output The input configuration is selected by clearing the corresponding DDR register bit. P e In this case, reading the DR register returns the digital value applied to the external I/O pin. t e l o Note: s b O 1 All the inputs are triggered by a Schmitt trigger. 2 When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output. Interrupt function When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external Interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the ITRFRE interrupt register. Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically ORed. For this reason if one of the interrupt pins is tied low, the other ones are masked. Output mode The pin is configured in output mode by setting the corresponding DDR register bit (see Table 13). 36/139 ST7260xx I/O ports In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Therefore, the previously saved value is restored when the DR register is read. Note: The interrupt function is disabled in this mode. Alternate function When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register. Note: ) s t( 1 Input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2 When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Caution: The alternate function must not be activated as long as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. 10.2.1 Port A c u d Table 14. e t le o s b Port A0, A3, A4, A5, A6, A7 description O ) I/O Port A PA0 s b O ol ete s ( t c Input(1) du with pull-up o r P PA3 PA4 o r P with pull-up with pull-up Alternate function Output Signal Condition push-pull MCO (Main Clock Output) MCO = 1 (MISCR) push-pull Timer EXTCLK CC1 =1 CC0 = 1 (Timer CR2) Timer ICAP1 push-pull IT1 Schmitt triggered input IT1E = 1 (ITIFRE) Timer ICAP2 PA5 PA6(2) PA7 with pull-up with pull-up with pull-up push-pull push-pull push-pull IT2 Schmitt triggered input IT2E = 1 (ITIFRE) Timer OCMP1 OC1E = 1 IT3 Schmitt triggered input IT3E = 1 (ITIFRE) Timer OCMP2 OC2E = 1 IT4 Schmitt triggered input IT4E = 1 (ITIFRE) 1. Reset state 2. Not available on SO24 37/139 I/O ports ST7260xx Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 configuration ALTERNATE ENABLE VDD ALTERNATE 1 OUTPUT 0 P-BUFFER VDD DR PULL-UP DATA BUS LATCH ALTERNATE ENABLE DDR LATCH PAD DDR SEL ) s t( N-BUFFER Table 15. ALTERNATE ENABLE 0 ALTERNATE INPUT e t le o s b I/O Input(1) Very High Current open drain PA2 without pull-up Very High Current open drain t e l o 38/139 Output without pull-up ) s ( ct u d o r P e s b O -O PA1 1. Reset state VSS o r P CMOS SCHMITT TRIGGER PA1, PA2 description Port A c u d DIODES 1 DR SEL Alternate function Signal Condition ST7260xx I/O ports Figure 20. PA1, PA2 configuration ALTERNATE ENABLE ALTERNATE 1 OUTPUT 0 DR LATCH DDR LATCH DATA BUS PAD ) s t( DDR SEL c u d N-BUFFER DR SEL 1 ALTERNATE ENABLE VSS 0 e t le CMOS SCHMITT TRIGGER 10.2.2 o s b Port B O ) Table 16. Port B description s ( t c I/O Port B Ob so du Input(1) ro PB0 Output without pull-up push-pull PB1 without pull-up push-pull PB2 without pull-up push-pull PB3 without pull-up push-pull PB4 without pull-up push-pull P e let PB5 PB6 o r P without pull-up without pull-up push-pull push-pull Alternate function Signal Condition USBOE (USB output enable)(2) USBOE =1 (MISCR) IT5 Schmitt triggered input IT4E = 1 (ITIFRE) IT6 Schmitt triggered input IT5E = 1 (ITIFRE) IT7 Schmitt triggered input IT6E = 1 (ITIFRE) 39/139 I/O ports ST7260xx Table 16. Port B description (continued) I/O Port B Alternate function Input(1) PB7 Output without pull-up Signal push-pull Condition IT8 Schmitt triggered input IT7E = 1 (ITIFRE) 1. Reset state 2. On SO24 only Figure 21. Port B configuration ) s t( ALTERNATE ENABLE ALTERNATE OUTPUT VDD 1 0 P-BUFFER DR LATCH o r P ALTERNATE ENABLE DDR e t le LATCH DATA BUS o s b DDR SEL DR SEL u d o ALTERNATE INPUT 10.2.3 Table 17. O ALTERNATE ENABLE DIGITAL ENABLE VSS Port C description I/O Port C Input(1) Alternate function Output Signal Condition PC0 with pull-up push-pull RDI (SCI input) PC1 with pull-up push-pull TDO (SCI output) SCI enable PC2(2) with pull-up push-pull USBOE (USB output enable) USBOE =1 (MISCR) 1. Reset state 2. Not available on SO24 40/139 0 N-BUFFER r P e Port C t e l o bs s ( t c PAD DIODES O ) 1 c u d VDD ST7260xx I/O ports Figure 22. Port C configuration ALTERNATE ENABLE VDD ALTERNATE 1 OUTPUT 0 P-BUFFER DR VDD PULL-UP LATCH ALTERNATE ENABLE DATA BUS DDR PAD LATCH DDR SEL ) s t( N-BUFFER c u d DIODES 1 DR SEL ALTERNATE ENABLE VSS 0 ALTERNATE INPUT CMOS SCHMITT TRIGGER 10.2.4 Register description 10.2.5 Data register (PxDR) PADR PBDR PCDR 6 P e R/W t e l o Table 18. s b O O ) Reset value: 0000 0000 (00h) Reset value: 0000 0000 (00h) Reset value: 1111 x000 (Fxh) 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W ro D7 o s b s ( t c du 7 e t le o r P PxDR register description Bit Name Function 7:0 Data bits The DR register has a specific behavior according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input. Reading the DR register returns either the DR register latch D[7:0] content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). – When using open-drain I/Os in output configuration, the value read in DR is the digital value applied to the I/O pin. – For Port C, unused bits (7-3) are not accessible 41/139 I/O ports 10.2.6 ST7260xx Data direction register (PxDDR) PADDR PBDDR PCDDR Reset value: 0000 0000 (00h) Reset value: 0000 0000 (00h) Reset value: 1111 x000 (Fxh) 7 6 5 4 3 2 1 0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 R/W R/W R/W R/W R/W R/W R/W R/W Table 19. Bit 7:0 PxDDR register description Name Data Direction bits The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode For Port C, unused bits (7-3) are not accessible c u d DD [7:0] Table 20. 0000h PADR reset value 0001h PADDR reset value 0002h PBDR reset value 42/139 o s b 6 -O 5 4 3 2 1 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 DD7 0 DD6 0 DD5 0 DD4 0 DD3 0 DD2 0 DD1 0 DD0 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 PBDDR reset value DD7 0 DD6 0 DD5 0 DD4 0 DD3 0 DD2 0 DD1 0 DD0 0 0004h PCDR reset value D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0005h PCDDR reset value DD7 0 DD6 0 DD5 0 DD4 0 DD3 0 DD2 0 DD1 0 DD0 0 (s) t c u d o r P e 10.2.7 7 D7 0 0003h s b O e t le o r P I/O port register map and reset values Address (Hex.) Register label t e l o ) s t( Function 0006h Reserved 0007h Reserved Related documentation ● AN 970: SPI Communication between ST7 and EEPROM ● AN1048: Software LCD driver ST7260xx 11 Miscellaneous register Miscellaneous register MISCR 7 6 5 4 3 2 1 0 - - - - - SMS USBOE MCO R/W R/W R/W Table 21. Bit Reset value: 0000 0000 (00h) MISCR register description Name 7:3 2 ) s t( Function Reserved c u d Slow mode select This bit is set by software and only cleared by hardware after a reset. If this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to Figure 15 on page 29). The SMS bit has no effect on the USB frequency. 0: Divide-by-2 disabled and CPU clock frequency is standard 1: Divide-by-2 enabled and CPU clock frequency is halved SMS e t le o r P o s b USB enable USB If this bit is set, the port PC2 (PB1 on SO24) outputs the USB output enable signal (at OE 1 “1” when the ST7 USB is transmitting data). Unused bits 7-4 are set. O ) Main clock out selection This bit enables the MCO alternate function on the PA0 I/O port. It is set and cleared MCO by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) s ( t c 0 Table 22. u d o Miscellaneous register map and reset values r P e Address (Hex.) Register label let o s b 0009h MISCR reset value 7 6 5 4 3 2 1 0 SMS 0 USB OE 0 MCO 0 O 43/139 Watchdog timer (WDG) ST7260xx 12 Watchdog timer (WDG) 12.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 12.2 ) s t( 12.3 Main features c u d ● Programmable free-running counter (64 increments of 49,152 CPU cycles) ● Programmable reset ● Reset (if watchdog activated) when the T6 bit reaches zero ● Optional reset on HALT instruction (configurable by option byte) ● Hardware Watchdog selectable by option byte. e t le o r P o s b Functional description O ) The counter value stored in the CR register (bits T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. s ( t c If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for a period of tDOG (see Table 62: Control timings on page 114). u d o r P e The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 23: Watchdog timing (fCPU = 8 MHz) on page 45): t e l o bs O 44/139 ● The WDGA bit is set (watchdog enabled) ● The T6 bit is set to prevent generating an immediate reset ● The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. ST7260xx Watchdog timer (WDG) Figure 23. Watchdog block diagram RESET WATCHDOG CONTROL REGISTER (CR) WDGA T5 T6 T4 T1 T2 T3 T0 7-BIT DOWNCOUNTER Table 23. Watchdog timing (fCPU = 8 MHz) 12.3.1 Max FFh Min C0h )- e t le so CR register initial value Note: c u d CLOCK DIVIDER ÷49152 fCPU Ob ) s t( o r P WDG timeout period (ms) 393.216 6.144 s ( t c 1 Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. 2 The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). u d o r P e Software watchdog option t e l o If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. bs O 12.3.2 The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). Hardware watchdog option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. 45/139 Watchdog timer (WDG) 12.3.3 ST7260xx Low power modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 12.3.4 Using Halt mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. ) s t( In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. c u d o r P If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). e t le Recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. o s b O ) ● s ( t c r P e ● t e l o s b O 12.3.5 ● u d o For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant with the value 0x8E. As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). Interrupts None. 46/139 ST7260xx 12.3.6 Watchdog timer (WDG) Control register (WDGCR) WDGCR Reset value: 0111 1111 (7Fh) 7 6 5 4 3 WDGA T[6:0] R/W R/W Table 24. Bit 2 1 0 WDGCR register description Name Function ) s t( 7 Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. WDGA 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 6:0 7-bit counter (MSB to LSB) T[6:0] These bits contain the value of the Watchdog counter. A reset is produced when it rolls over from 40h to 3Fh (T6 is cleared). c u d Table 25. e t le o s b o r P Watchdog timer register map and reset values Address (Hex.) Register label WDGCR reset value 000Ch 7 6 5 4 3 2 1 0 WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 s ( t c O ) u d o r P e t e l o s b O 47/139 Watchdog timer (WDG) ST7260xx 12.4 16-bit timer 12.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. ) s t( Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. c u d This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 12.4.2 Main features ● Programmable prescaler: fCPU divided by 2, 4 or 8 ● Overflow status flag and maskable interrupt ● External clock input (must be at least four times slower than the CPU clock speed) with the choice of active edge ● 1 or 2 output compare functions each with: o s b let O O ) – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt s ( t c u d o r P e ● o s b e t le o r P 1 or 2 input capture functions each with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ● Pulse width modulation mode (PWM) ● One pulse mode ● Reduced power mode ● 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a) The timer block diagram is shown in Figure 24. a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to Section 3: Pin description. When reading an input signal on a non-bonded pin, the value will always be ‘1’. 48/139 ST7260xx 12.4.3 Watchdog timer (WDG) Functional description Counter The main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. ● ● Counter Register (CR) – Counter High Register (CHR) is the most significant byte (MSB) – Counter Low Register (CLR) is the least significant byte (LSB) Alternate Counter Register (ACR) ) s t( – Alternate Counter High Register (ACHR) is the most significant byte (MSB) – Alternate Counter Low Register (ACLR) is the least significant byte (LSB) c u d These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence). o r P Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM mode. e t le o s b The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 32. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. O ) s ( t c u d o r P e t e l o s b O 49/139 Watchdog timer (WDG) ST7260xx Figure 24. Timer block diagram ST7 internal bus fCPU MCU-peripheral interface 8 low 8 8 low 8 low 8 high 8 high EXEDG 8 high 8 high 8 low 8-bit buffer low 8 high 16 1/2 1/4 1/8 EXTCLK pin Output Compare register 2 Output Compare register 1 Counter register Input Capture register 1 uc 2 d o r Alternate Counter register ) s t( Input Capture register 16 16 P e et 16 CC[1:0] Timer internal bus l o s 16 Overflow Detect circuit Ob Output Compare circuit )- 6 s ( t c du ro ICF1 OCF1 TOF ICF2 OCF2 TIMD P e t e l o s b O 0 16 Edge Detect circuit 1 ICAP1 pin Edge Detect circuit 2 ICAP2 pin Latch 1 OCMP1 pin Latch 2 OCMP2 0 (Control/Status register) CSR pin ICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1OLVL1 OC1E OC2E OPM PWM CC1 (Control register 1) CR1 CC0 IEDG2EXEDG (Control register 2) CR2 (See note 1) Timer interrupt 1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 10: Interrupt mapping on page 32). 50/139 ST7260xx Watchdog timer (WDG) 16-bit read sequence The 16-bit read sequence (from either the Counter register or the Alternate Counter register) is illustrated in the following Figure 25. Figure 25. 16-bit read sequence Beginning of the sequence At t0 LSB is buffered Read MSB Other instructions At t0 +Δt Read LSB ) s t( Returns the buffered LSB value at t0 c u d Sequence completed The user must first read the MSB, afterwhich the LSB value is automatically buffered. o r P This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. e t le After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LSB of the count value at the time of the read. o s b Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: O ) ● The TOF bit of the SR register is set. ● A timer interrupt is generated if: s ( t c – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. u d o If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. r P e Clearing the overflow interrupt request is done in two steps: let 1. so Note: Ob 2. Reading the SR register while the TOF bit is set. An access (read or write) to the CLR register. The TOF bit is not cleared by access to the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by Wait mode. In Halt mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a reset). 51/139 Watchdog timer (WDG) ST7260xx External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 26. Counter timing diagram, internal clock divided by 2 ) s t( CPU clock c u d Internal reset Timer clock Counter register FFFD FFFE FFFF 0000 e t le Timer Overflow Flag (TOF) o r P 0001 0002 0003 o s b Figure 27. Counter timing diagram, internal clock divided by 4 O ) CPU clock s ( t c Internal reset du ete l o s Ob o r P Timer clock Counter register FFFC FFFD 0000 0001 Timer Overflow Flag (TOF) Figure 28. Counter timing diagram, internal clock divided by 8 CPU clock Internal reset Timer clock Counter register FFFC FFFD 0000 Timer Overflow Flag (TOF) Note: 52/139 The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. ST7260xx Watchdog timer (WDG) Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 30). Table 26. Input capture byte distribution Register MS byte LS byte ICiR ICiHR ICiLR ) s t( The ICiR registers are read-only registers. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). c u d Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure e t le o r P To use the input capture function select the following in the CR2 register: ● Select the timer clock (CC[1:0]) (see Table 32). ● Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). o s b O ) Select the following in the CR1 register: ● Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin ● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). s ( t c u d o r P e When an input capture occurs: ● t e l o ● O bs ● ICFi bit is set. The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 30). A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set 2. An access (read or write) to the ICiLR register 53/139 Watchdog timer (WDG) Note: ST7260xx 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3 The two input capture functions can be used together even if the timer also uses the two output compare functions. 4 In One pulse mode and PWM mode only Input Capture 2 can be used. 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 ) s t( c u d The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). Figure 29. Input capture block diagram ICAP1 pin Edge Detect circuit 2 ICAP2 pin ) s ( ct 16-bit (Control register 1) CR1 so Edge Detect circuit 1 IC2R register e t le o r P b O - IC1R register ICIE IEDG1 (Status register) SR ICF1 0 ICF2 u d o CC1 r P e t e l o Figure 30. Input capture timing diagram Timer clock Counter register FF01 FF02 FF03 ICAPi pin ICAPi flag ICAPi register Note: The rising edge is the active edge. 54/139 0 (Control register 2) CR2 16-bit free running counter s b O 0 FF03 CC0 IEDG2 ST7260xx Watchdog timer (WDG) Output compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: – Assigns pins with a programmable value if the OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled ) s t( Two 16-bit registers Output Compare register 1 (OC1R) and Output Compare register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. Table 27. c u d Output compare byte distribution Register MS byte OCiR OCiHR e t e o r P LS byte OCiLR l o s These registers are readable and witable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. b O - Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure ) s ( ct To use the Output Compare function, select the following in the CR2 register: ● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. ● Select the timer clock (CC[1:0]) (see Table 32). u d o r P e And select the following in the CR1 register: ● let ● Ob so Select the OLVLi bit to applied to the OCMPi pins after the match occurs. Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: ● OCFi bit is set ● The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset) ● A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: Δ OCiR = Δt * fCPU PRESC Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 32) 55/139 Watchdog timer (WDG) ST7260xx If the timer clock is an external clock, the formula is: Δ OCiR = Δt * fEXT Where: Δt fEXT = Output compare period (in seconds) = External timer clock frequency (in hertz) Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. ) s t( The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Note: c u d ● Write to the OCiHR register (further compares are inhibited). ● Read the SR register (first step of the clearance of the OCFi bit, which may be already set). ● Write to the OCiLR register (enables the output compare function and clears the OCFi bit). e t le o r P 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 32 on page 57 for an example with fCPU/2 and Figure 33 on page 57 for an example with fCPU/4). This behavior is the same in OPM or PWM mode. 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5 The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. o s b O ) s ( t c u d o r P e t e l o s b O Forced output compare capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. The FOLVLi bits have no effect in both one pulse mode and PWM mode. 56/139 ST7260xx Watchdog timer (WDG) Figure 31. Output compare block diagram 16-bit free running counter OC1E OC2E CC1 CC0 (Control Register 2) CR2 16-bit (Control Register 1) CR1 Output compare 16-bit circuit OCIE FOLV2FOLV1 OLVL2 Latch 1 OLVL1 16-bit Latch 2 OCMP1 Pin OC1R register OCF1 OCF2 OC2R register 0 0 c u d o r P Figure 32. Output compare timing diagram, fTIMER = fCPU/2 e t le o s b Timer clock Counter register -O Output Compare register i (OCRi) ) s ( ct 2ECF 2ED0 ) s t( 0 (Status register) SR Internal CPU clock OCMP2 Pin 2ED1 2ED2 2ED3 2ED4 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi = 1) u d o Figure 33. Output compare timing diagram, fTIMER = fCPU/4 r P e s b O t e l o Internal CPU clock Timer clock Counter register Output Compare register i (OCRi) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 Output Compare flag i (OCFi) OCMPi pin (OLVLi = 1) 57/139 Watchdog timer (WDG) ST7260xx One pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula below). 2. Select the following in the CR1 register: 3. ) s t( – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). c u d Select the following in the CR2 register: e t le o r P – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 32). o s b O ) Figure 34. One pulse mode cycle s ( t c u d o ete l o s Ob Pr When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 58/139 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. ST7260xx Watchdog timer (WDG) The OC1R register value required for a specific timing application can be calculated using the following formula: t f OCiR value = * CPU -5 PRESC Where: t = Pulse period (in seconds) fCPU = CPU clock frequnency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 32) If the timer clock is an external clock the formula is: ) s t( OCiR = t * fEXT - 5 c u d Where: t fEXT = Pulse period (in seconds) = External timer clock frequency (in hertz) e t le o r P When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 35). Note: o s b 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5 O ) s ( t c u d o r P e When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. s b O t e l o Figure 35. One Pulse mode timing example(1) Counter 2ED3 01F8 IC1R 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 Compare1 1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 59/139 Watchdog timer (WDG) ST7260xx Figure 36. Pulse width modulation mode timing example with two output compare functions(1)(2) 2ED0 2ED1 2ED2 Counter 34E2 FFFC FFFD FFFE OLVL2 OCMP1 34E2 OLVL1 compare2 compare1 FFFC OLVL2 compare2 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 ) s t( 2. On timers with only one Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length. c u d Pulse width modulation mode o r P Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. e t le o s b In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). O ) Procedure s ( t c To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula below. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column. r P e 3. t e l o s b O 60/139 4. u d o Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register. – Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 32). ST7260xx Watchdog timer (WDG) Figure 37. Pulse width modulation cycle When counter = OC1R OCMP1 = OLVL1 OCMP1 = OLVL2 When counter = OC2R counter is reset to FFFCh ICF1 bit is set ) s t( If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin. c u d o r P The OC1R register value required for a specific timing application can be calculated using the following formula: e t le t f OCiR value = * CPU o s b -5 PRESC Where: O ) t = Signal or pulse period (in seconds) fCPU = CPU clock frequnency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 32) s ( t c If the timer clock is an external clock the formula is: u d o r P e OCiR = t * fEXT - 5 Where: t e l o O bs Note: t fEXT = Signal or pulse period (in seconds) = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 36). 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4 In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 61/139 Watchdog timer (WDG) 12.4.4 ST7260xx Low power modes Table 28. Effect of low power modes on 16-bit timer Mode 12.4.5 Description Wait No effect on 16-bit timer. Timer interrupts cause the device to exit from Wait mode. Halt 16-bit timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with Exit from Halt mode capability or from the counter reset value when the MCU is woken up by a reset. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with Exit from Halt mode capability, the ICFi bit is set, and the counter value present when exiting from Halt mode is captured into the ICiR register. ) s t( c u d Interrupts Table 29. o r P 16-bit timer interrupt control/wake-up capability Interrupt event Input Capture 1 event/counter reset in PWM mode O ) Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 s ( t c r P e Exit from Halt Yes No ICIE ICF2 u d o Exit from Wait o s b ICF1 Input Capture 2 event Timer Overflow event e t le Event flag Enable control bit (1) TOF OCIE TOIE 1. The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). t e l o s b O 62/139 ST7260xx 12.4.6 Watchdog timer (WDG) Summary of timer modes Table 30. Summary of timer modes Timer resources Mode Input capture 1 Input capture 2 Output compare 1 Output compare 2 Yes Yes Yes Yes Input Capture (1 and/or 2) Output Compare (1 and/or 2) Not recommended(1) One Pulse mode No PWM mode Not recommended(3) 2. See note 5 in One pulse mode on page 58. No P e et 3. See note 4 in Pulse width modulation mode on page 60. 16-bit timer registers uc d o r 1. See note 4 in One pulse mode on page 58. 12.4.7 ) s t( Partially(2) No l o s Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. Control Register 1 (CR1) 6 ) s ( ct 5 4 3 2 1 0 OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 R/W R/W R/W R/W R/W R/W R/W CR1 du 7 ro ICIE P e R/W t e l o M Table 31. s b O Bit b O - Reset value: 0000 0000 (00h) CR1 register description Name Function ICIE Input Capture Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. 6 OCIE Output Compare Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. 5 TOIE Timer Overflow Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 7 63/139 Watchdog timer (WDG) Table 31. Bit ST7260xx CR1 register description (continued) Name Function 4 Forced Output compare 2 This bit is set and cleared by software. FOLV2 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. 3 Forced Output compare 1 This bit is set and cleared by software. FOLV1 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. 2 Output Level 2 This bit is copied to the OCMP2 pin whenever a successful comparison occurs with OLVL2 the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width modulation mode. ) s t( c u d e t le 1 IEDG1 0 Output Level 1 OLVL1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. o s b u d o CR2 Pr 7 OC1E e t e l R/W Ob M Table 32. Bit 7 6 64/139 O ) s ( t c Control Register 2 (CR2) so o r P Input Edge 1 This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Name Reset value: 0000 0000 (00h) 6 5 4 OC2E OPM PWM R/W R/W R/W 3 2 1 0 CC[1:0] IEDG2 EXEDG R/W R/W R/W CR2 register description Function OCIE Output Compare 1 Pin Enable This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. OC2E Output Compare 2 Pin Enable This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. ST7260xx Watchdog timer (WDG) Table 32. Bit 5 4 CR2 register description (continued) Name Function OPM One Pulse Mode 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. PWM Pulse Width Modulation 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. ) s t( Clock Control The timer clock mode depends on these bits. 00: Timer clock = fCPU/4 01: Timer clock = fCPU/2 CC[1:0] 10: Timer clock = fCPU/8 11: Timer clock = external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. c u d 3:2 e t le o r P o s b 1 Input Edge 2 This bit determines which type of level transition on the ICAP2 pin will trigger the IEDG2 capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0 External Clock Edge This bit determines which type of level transition on the external clock pin EXTCLK EXEDG will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. O ) s ( t c u d o r P e Control/Status Register (CSR) t e l o CSR bs O 7 6 5 4 3 2 ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved RO RO RO RO RO R/W - M Table 33. Bit Name 7 Reset value: xxxx x0xx (xxh) 1 0 CSR register description Function Input Capture Flag 1 0: No Input Capture (reset value). ICF1 1: An Input Capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. 65/139 Watchdog timer (WDG) Table 33. ST7260xx CSR register description (continued) Bit Name Function Output Compare Flag 1 0: No match (reset value). OCF1 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. 6 Timer Overflow Flag 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. 5 TOF 4 Input Capture Flag 2 0: No input capture (reset value). ICF2 1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. 3 Output Compare Flag 2 0: No match (reset value). OCF2 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. 2 Timer Disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce TIMD power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled. 1: Timer prescaler, counter and outputs disabled. ) s t( c u d e t le o r P o s b O ) s ( t c 1:0 - u d o Reserved, must be kept cleared. r P e Input capture 1 high register (IC1HR) t e l o This is an 8-bit register that contains the high part of the counter value (transferred by the input capture 1 event). s b O IC1HR 7 6 5 4 3 2 1 MSB RO 66/139 Reset value: undefined 0 LSB RO RO RO RO RO RO RO ST7260xx Watchdog timer (WDG) Input capture 1 low register (IC1LR) This is an 8-bit register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR Reset value: undefined 7 6 5 4 3 2 1 MSB 0 RO LSB RO RO RO RO RO RO Output compare 1 high register (OC1HR) RO ) s t( This is an 8-bit register that contains the high part of the value to be compared to the CHR register. c u d OC1HR o r P Reset value: 1000 0000 (80h) 7 6 5 4 3 e t le MSB R/W R/W R/W so R/W b O - R/W 2 R/W 1 0 LSB R/W R/W Output compare 1 low register (OC1LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC1LR du 7 6 o r P MSB R/W e t e ol ) s ( ct R/W 5 Reset value: 0000 0000 (00h) 4 3 2 1 0 LSB R/W R/W R/W R/W R/W R/W Output compare 2 high register (OC2HR) s b O This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OC2HR 7 Reset value: 1000 0000 (80h) 6 5 4 3 2 1 MSB R/W 0 LSB R/W R/W R/W R/W R/W R/W R/W 67/139 Watchdog timer (WDG) ST7260xx Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR Reset value: 0000 0000 (00h) 7 6 5 4 3 2 1 MSB 0 R/W LSB R/W R/W R/W R/W R/W R/W Counter high register (CHR) R/W This is an 8-bit register that contains the high part of the counter value. CHR ) s t( c u d Reset value: 1111 1111 (FFh) 7 6 5 4 3 MSB RO RO RO RO e t le RO o r P 2 RO 1 0 LSB RO RO o s b Counter low register (CLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. O ) CLR du 7 6 o r P MSB RO e t e ol s ( t c RO 5 Reset value: 1111 1100 (FCh) 4 3 2 1 0 LSB RO RO RO RO RO RO Alternate counter high register (ACHR) bs O This is an 8-bit register that contains the high part of the counter value. ACHR 7 Reset value: 1111 1111 (FFh) 6 5 4 3 2 1 MSB RO 68/139 0 LSB RO RO RO RO RO RO RO ST7260xx Watchdog timer (WDG) Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. ACLR Reset value: 1111 1100 (FCh) 7 6 5 4 3 2 1 MSB 0 RO LSB RO RO RO RO RO RO RO ) s t( Input capture 2 high register (IC2HR) c u d This is an 8-bit register that contains the high part of the counter value (transferred by the Input Capture 2 event). 1C2HR o r P Reset value: undefined 7 6 5 4 ol MSB RO RO RO e t e 3 bs RO RO 2 1 0 LSB RO RO RO O ) Input capture 2 low register (IC2LR) This is an 8-bit register that contains the low part of the counter value (transferred by the Input Capture 2 event). s ( t c du 1C2LR 7 o r P 6 5 Reset value: undefined 4 3 2 1 MSB e t e l RO RO 0 LSB RO RO RO RO RO RO o s b O 69/139 Watchdog timer (WDG) Table 34. ST7260xx 16-bit timer register map and reset values Address (Hex.) Register label 7 6 5 4 3 2 1 0 11 CR1 Reset value ICIE 0 OCIE 0 TOIE 0 FOLV2 0 FOLV1 0 OLVL2 0 IEDG1 0 OLVL1 0 12 CR2 Reset value OC1E 0 OC2E 0 OPM 0 PWM 0 CC1 0 CC0 0 IEDG2 0 EXEDG 0 13 CSR Reset value ICF1 x OCF1 x TOF x ICF2 x OCF2 x TIMD 0 x x 14 IC1HR Reset value MSB x x x x x x x LSB x 15 IC1LR Reset value MSB x x x x x x 16 OC1HR Reset value MSB 1 0 0 0 0 17 OC1LR Reset value MSB 0 0 0 0 18 CHR Reset value MSB 1 1 1 19 CLR Reset value MSB 1 1 1 1A ACHR Reset value MSB 1 1 1B ACLR Reset value MSB 1 1C IC2HR Reset value 1D IC2LR Reset value 1E 1F 70/139 x LSB x 0 LSB 0 0 0 LSB 0 1 1 1 LSB 1 1 1 1 0 LSB 0 1 1 1 1 1 LSB 1 1 1 1 1 1 0 LSB 0 x x x x x x LSB x MSB x x x x x x x LSB x OC2HR Reset value MSB 1 0 0 0 0 0 0 LSB 0 OC2LR Reset value MSB 0 0 0 0 0 0 0 LSB 0 MSB x e t le o s b O ) s ( t c u d o r P e t e l o s b O c u d ) s t( 1 0 o r P 0 ST7260xx Serial communications interface (SCI) 13 Serial communications interface (SCI) 13.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 13.2 Main features ) s t( ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● Independently programmable transmit and receive baud rates up to 250K baud. ● Programmable data word length (8 or 9 bits) ● Receive buffer full, Transmit buffer empty and End of Transmission flags ● Two receiver wake-up modes: – Address bit (MSB) – Idle line c u d e t le o s b ● Muting function for multiprocessor configurations ● Separate enable bits for Transmitter and Receiver ● Four error detection flags: t e l o ● ● O ) s ( t c – Overrun error – Noise error – Frame error – Parity error u d o r P e ● s b O o r P Six interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected – Parity error Parity control: – Transmits parity bit – Checks parity of received data byte Reduced power consumption mode 71/139 Serial communications interface (SCI) 13.2.1 ST7260xx General description The interface is externally connected to another device by two pins (see Figure 39): ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level. ● RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ● A Stop bit indicating that the frame is complete. ) s t( c u d This interface uses two types of baud rate generator: ● A conventional type for commonly-used baud rates. e t le o s b O ) s ( t c u d o r P e t e l o s b O 72/139 o r P ST7260xx Serial communications interface (SCI) Figure 38. SCI block diagram Write Read (DATA REGISTER) DR Received Data Register (RDR) Transmit Data Register (TDR) TDO Received Shift Register Transmit Shift Register RDI CR1 R8 TRANSMIT WAKE UP CONTROL UNIT T8 SCID ILIE TE SCI INTERRUPT CONTROL ) s ( ct TRANSMITTER CLOCK du fCPU ro P e /16 RECEIVER CLOCK SR NF FE PE b O - TRANSMITTER RATE CONTROL /PR t e l o s b O 13.2.2 l o s TDRE TC RDRF IDLE OR c u d ro P e et RE RWU SBK ) s t( PIE RECEIVER CONTROL CR2 TIE TCIE RIE M WAKE PCE PS BRR SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER RATE CONTROL BAUD RATE GENERATOR Functional description The block diagram of the Serial Control Interface, is shown in Figure 38. It contains 6 dedicated registers: ● Two control registers (SCICR1 & SCICR2) ● A status register (SCISR) ● A baud rate register (SCIBRR) Refer to the register descriptions in Section 13.3 for the definitions of each bit. 73/139 Serial communications interface (SCI) ST7260xx Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 38). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. ) s t( Transmission and reception are driven by their own baud rate generator. c u d Figure 39. Word length programming 9-bit Word length (M bit is set) e t le Data Frame Start Bit Bit2 Bit1 Bit0 Bit3 o r P Possible Parity Bit Bit4 Idle Frame Bit5 Bit6 o s b Bit7 Bit8 Start Bit O ) Extra ’1’ Break Frame s ( t c 8-bit Word length (M bit is reset) ro du P e Start Bit Bit0 t e l o s b O Possible Parity Bit Data Frame Bit1 Bit2 Bit3 Bit4 Next Data Frame Next Stop Start Bit Bit Bit5 Bit6 Bit7 Start Bit Next Data Frame Stop Bit Next Start Bit Idle Frame Start Bit Break Frame Extra Start Bit ’1’ Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 38). 74/139 ST7260xx Serial communications interface (SCI) Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIETPR registers. ● Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. ● Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SCISR register 2. A write to the SCIDR register ) s t( The TDRE bit is set by hardware and it indicates: ● The TDR register is empty. ● The data transfer is beginning. ● The next data can be written in the SCIDR register without overwriting the previous data. c u d o r P This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. e t le o s b When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. O ) When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. s ( t c When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. u d o r P e Clearing the TC bit is performed by the following software sequence: 1. t e l o 2. Note: s b O An access to the SCISR register A write to the SCIDR register The TDRE and TC bits are cleared by the same software sequence. Break characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 39). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. 75/139 Serial communications interface (SCI) Note: ST7260xx Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR. Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 38). ) s t( Procedure c u d ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIERPR registers. ● Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: e t le o r P ● The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. ● The error flags can be set if a frame error, noise or an overrun error has been detected during reception. o s b O ) Clearing the RDRF bit is performed by the following software sequence done by: s ( t c 1. An access to the SCISR register 2. A read to the SCIDR register u d o The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. r P e Break Character t e l o When a break character is received, the SCI handles it as a framing error. Idle Character bs O When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the RDR register as long as the RDRF bit is not cleared. When a overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation. 76/139 ST7260xx Serial communications interface (SCI) Noise error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. When noise is detected in a frame: ● The NF flag is set at the rising edge of the RDRF bit. ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. ) s t( c u d The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation. o r P During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received. e t le o s b Note: If the application Start Bit is not long enough to match the above requirements, then the NF Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received. s ( t c See also Noise error causes. Framing Error O ) u d o A framing error is detected when: r P e ● ● t e l o The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. A break is received. When the framing error is detected: s b O ● The FE bit is set by hardware ● Data is transferred from the Shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. 77/139 Serial communications interface (SCI) ST7260xx Baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Tx = fCPU Rx = fCPU (16*PR)*RR (16*PR)*TR with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) ) s t( RR = 1, 2, 4, 8, 16, 32, 64,128 c u d (see SCR[2:0] bits) All these bits are in the SCIBRR register. o r P Example: If fCPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 38400 baud. Note: e t le The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. o s b Receiver muting and wake-up feature O ) In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. s ( t c The non addressed devices may be placed in sleep mode by means of the muting function. u d o Setting the RWU bit by software puts the SCI in sleep mode: r P e All the reception status bits can not be set. All the receive interrupts are inhibited. t e l o A muted receiver may be awakened by one of the following two ways: ● bs O ● by Idle Line detection if the WAKE bit is reset, by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Caution: 78/139 In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the read operation (RWU=1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit will be set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode. ST7260xx Serial communications interface (SCI) Parity control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 35. Table 35. Frame formats M bit PCE bit SCI frame 0 0 | SB | 8 bit data | STB | 0 1 | SB | 7-bit data | PB | STB | 1 0 | SB | 9-bit data | STB | 1 1 | SB | 8-bit data PB | STB | c u d Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit Note: ) s t( o r P In case of wake up by an address mark, the MSB bit of the data is taken into account and not the parity bit e t le Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. o s b Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. O ) Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1). s ( t c Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. u d o Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. r P e t e l o SCI clock tolerance bs O During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs & 36 µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal 79/139 Serial communications interface (SCI) ST7260xx clock occurs just before the pin value changes, the samples would then be out of sync by ~4 µs. This means the entire bit length must be at least 40 µs (36µs for the 10th sample + 4 µs for synchronization with the internal sampling clock). Clock deviation causes The causes which contribute to the total deviation are: ● DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). ● DQUANT: Error due to the baud rate quantisation of the receiver. ● DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. ● DTCL: Deviation due to the transmission line (generally due to the transceivers) ) s t( c u d All the deviations of the system should be added and compared to the SCI clock tolerance: o r P DTRA + DQUANT + DREC + DTCL < 3.75% Noise error causes e t le See also description of Noise error in Receiver on page 76. o s b Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: Note: 1 2 O ) A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”. s ( t c u d o During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a “1”. r P e Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. t e l o Data bits bs O 80/139 The noise flag (NF) is set during normal data bit reception if the following condition occurs: ● During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. ST7260xx Serial communications interface (SCI) Figure 40. Bit sampling in reception mode RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 13.2.3 ) s t( c u d Low power modes Table 36. Effect of low power modes on SCI Mode 13.2.4 Description e t le o r P Wait No effect on SCI. SCI interrupts cause the device to exit from Wait mode. Halt SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. o s b O ) Interrupts s ( t c The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). Pr Table 37. ol ete O bs u d o SCI interrupt control/wake-up capability Interrupt event Transmit data register empty Transmission complete Received data ready to be read Event flag Enable control bit Exit from Wait Exit from Halt TDRE TIE Yes No TC TCIE Yes No Yes No Yes No RDRF RIE Overrun error detected Idle line detected Parity error OR IDLE ILIE Yes No PE PIE Yes No 81/139 Serial communications interface (SCI) ST7260xx 13.3 Register description 13.3.1 Status register (SCISR) Reset value: 1100 0000 (C0h) SCISR 7 6 5 4 3 2 1 0 TDRE TC RDRF IDLE OR NF FE PE R R R R R R R R Table 38. Bit SCISR register description Name ) s t( Function c u d 7 Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register TDRE followed by a write to the SCIDR register). 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register. Note: Data will not be transferred to the shift register unless the TDRE bit is cleared. e t le o r P o s b 6 TC Transmission Complete This bit is set by hardware when transmission of a frame containing data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete 1: Transmission is complete Note: TC is not set after the transmission of a Preamble or a Break. O ) s ( t c u d o r P e t e l o 5 s b O 4 82/139 Received Data Ready Flag This bit is set by hardware when the content of the RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 RDRF register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: Data is not received 1: Received data is ready to be read Idle line detect This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). IDLE 0: No idle line is detected 1: Idle line is detected Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new idle line occurs). ST7260xx Serial communications interface (SCI) Table 38. Bit 3 2 SCISR register description (continued) Name Function OR Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No overrun error 1: Overrun error is detected Note: When this bit is set RDR register content is not lost but the shift register is overwritten. NF Noise Flag This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. ) s t( c u d e t le 1 FE o r P Framing Error This bit is set by hardware when a desynchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both Frame Error and Overrun error, it is transferred and only the OR bit will be set. o s b O ) s ( t c u d o Parity Error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register. 0: No parity error 1: Parity error r P e 0 t e l o PE s b O 83/139 Serial communications interface (SCI) 13.3.2 ST7260xx Control register 1 (SCICR1) Reset value: x000 0000 (x0h) SCICR1 7 6 5 4 3 2 1 0 R8 T8 SCID M WAKE PCE PS PIE R/W R/W R/W R/W R/W R/W R/W R/W Table 39. SCICR1 register description Bit Name Function 7 R8 Receive data bit 8 This bit is used to store the 9th bit of the received word when M = 1. 6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmitted word when M = 1. ) s t( c u d o r P 5 Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and SCID cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled 4 Word length This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 data bits, 1 Stop bit 1: 1 Start bit, 9 data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception). e t le o s b M O ) s ( t c u d o Wake-Up method This bit determines the SCI Wake-Up method, it is set or cleared by software. WAKE 0: Idle line 1: Address mark r P e 3 let o s b O 84/139 2 PCE Parity Control Enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled ST7260xx Serial communications interface (SCI) Table 39. Bit Name 0 Function PS Parity Selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity PIE Parity Interrupt Enable This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled 1 13.3.3 SCICR1 register description (continued) ) s t( c u d Control register 2 (SCICR2) 7 6 5 4 TIE TCIE RIE ILIE R/W R/W R/W R/W Table 40. Bit ol TE O ) bs R/W 2 1 0 RE RWU SBK R/W R/W R/W s ( t c Function Transmitter Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register. u d o TIE Pr Transmission Complete Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever TC = 1 in the SCISR register. ete TCIE 5 RIE Receiver interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register. ILIE Idle Line Interrupt Enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register. 6 l o s Ob e t e 3 SCICR2 register description Name 7 o r P Reset value: 0000 0000 (00h) SCICR2 4 85/139 Serial communications interface (SCI) Table 40. Bit ST7260xx SCICR2 register description (continued) Name Function TE Transmitter Enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: - During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble (Idle line) after the current word. - When TE is set there is a 1 bit-time delay before the transmission starts. Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). RE Receiver Enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line detection. RWU Receiver Wake-Up This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in Active mode 1: Receiver in Mute mode SBK Send Break This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted. 1: Break characters are transmitted. Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word at the end of the current word. 3 ) s t( 2 1 0 13.3.4 c u d e t le o s b O ) s ( t c u d o r P e Data register (SCIDR) t e l o Reset value: undefined (xxh) SCIDR bs O o r P 7 6 5 4 3 2 1 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 R/W R/W R/W R/W R/W R/W R/W R/W Contains the Received or Transmitted data character, depending on whether it is read from or written to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 38). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 38). 86/139 ST7260xx 13.3.5 Serial communications interface (SCI) Baud rate register (SCIBRR) Reset value: 0000 0000 (00h) SCIBRR 7 6 4 3 2 1 0 SCP[1:0] SCT[2:0] SCR[2:0] R/W R/W R/W Table 41. Bit 5 SCIBRR register description Name Function First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges. 00: PR prescaling factor = 1 7:6 SCP[1:0] 01: PR prescaling factor = 3 10: PR prescaling factor = 4 11: PR prescaling factor = 13 ) s t( c u d o r P SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate generator mode. 000: TR dividing factor = 1 001: TR dividing factor = 2 5:3 SCT[2:0] 010: TR dividing factor = 4 011: TR dividing factor = 8 100: TR dividing factor = 16 101: TR dividing factor = 32 110: TR dividing factor = 64 111: TR dividing factor = 128 e t le o s b O ) s ( t c u d o SCI Receiver rate divisor These 3 bits, in conjunction with the SCP[1:0] bits, define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. 000: RR dividing factor = 1 001: RR dividing factor = 2 2:0 SCR[2:0] 010: RR dividing factor = 4 011: RR dividing factor = 8 100: RR dividing factor = 16 101: RR dividing factor = 32 110: RR dividing factor = 64 111: RR dividing factor = 128 r P e s b O t e l o Table 42. SCI register map and reset values Address (Hex.) Register Label 7 6 5 4 3 2 1 0 20 SCISR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 0 21 SCIDR Reset Value DR7 x DR6 x DR5 x DR4 x DR3 x DR2 x DR1 x DR0 x 87/139 Serial communications interface (SCI) Table 42. ST7260xx SCI register map and reset values Address (Hex.) Register Label 7 6 5 4 3 2 1 0 22 SCIBRR Reset Value SCP1 0 SCP0 0 SCT2 x SCT1 x SCT0 x SCR2 x SCR1 x SCR0 x 23 SCICR1 Reset Value R8 x T8 x SCID 0 M x WAKE x PCE 0 PS 0 PIE 0 24 SCICR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 88/139 o r P ST7260xx USB interface (USB) 14 USB interface (USB) 14.1 Introduction The USB Interface implements a low-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and DMA. No external components are needed apart from the external pull-up on USBDM for low speed recognition by the USB host. The use of DMA architecture allows the endpoint definition to be completely flexible. Endpoints can be configured by software as in or out. 14.2 ) s t( Main features c u d ● USB specification version 1.1 compliant ● Supports Low-Speed USB protocol ● Two or three Endpoints (including default one) depending on the device (see device feature list and register map) ● CRC generation/checking, NRZI encoding/decoding and bit-stuffing ● USB Suspend/Resume operations ● DMA data transfers ● On-chip 3.3V regulator ● On-chip USB transceiver e t le o r P o s b O ) s ( t c 14.3 Functional description u d o The block diagram in Figure 41, gives an overview of the USB interface hardware. r P e For general information on the USB, refer to the “Universal Serial Bus Specifications” document available at http//:www.usb.org. t e l o Serial interface engine s b O The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. DMA When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place, using DMA. At the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred. 89/139 USB interface (USB) ST7260xx Figure 41. USB block diagram 6 MHz ENDPOINT CPU REGISTERS USBDM Transceiver SIE Address, DMA USBDP data buses and interrupts 3.3V Voltage Regulator USBVCC ) s t( INTERRUPT c u d REGISTERS MEMORY USBGND e t le 14.4 Register description 14.4.1 DMA address register (DMAR) 7 6 DA15 DA14 R/W u d o s ( t c R/W 5 o s b O ) DMAR o r P Reset value: undefined (xxh) 4 3 2 1 0 DA13 DA12 DA11 DA10 DA9 DA8 R/W R/W R/W R/W R/W R/W r P e Bits 7:0=DA[15:8] DMA address bits 15-8. Software must write the start address of the DMA memory area whose most significant bits are given by DA15-DA6. The remaining 6 address bits are set by hardware. See the description of the IDR register and Figure 42. t e l o bs 14.4.2 O Interrupt/DMA register (IDR) Reset value: xxxx 0000 (x0h) IDR 7 6 5 4 3 2 1 0 DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:6 = DA[7:6] DMA address bits 7-6. Software must reset these bits. See the description of the DMAR register and Figure 42. Bits 5:4 = EP[1:0] Endpoint number (read-only). These bits identify the endpoint which required attention. 00: Endpoint 0 01: Endpoint 1 10: Endpoint 2 90/139 ST7260xx USB interface (USB) When a CTR interrupt occurs (see register ISTR) the software should read the EP bits to identify the endpoint which has sent or received a packet. Bits 3:0 = CNT[3:0] Byte count (read only). This field shows how many data bytes have been received during the last data reception. Note: Not valid for data transmission. Figure 42. DMA buffers 101111 Endpoint 2 TX 101000 100111 ) s t( Endpoint 2 RX 100000 011111 011000 010111 010000 001111 c u d Endpoint 1 TX Endpoint 1 RX o r P Endpoint 0 TX e t le 001000 000111 Endpoint 0 RX o s b DA15-6,000000 14.4.3 000000 O ) PID register (PIDR) s ( t c PIDR 7 6 5 4 3 2 1 0 TP2 0 0 0 RX_ SEZ RXD 0 R R R R R R R u d o TP3 r P e R Reset value: xxxx 0000 (x0h) t e l o s b O Note: Bits 7:6 = TP[3:2] Token PID bits 3 & 2. USB token PIDs are encoded in four bits. TP[3:2] correspond to the variable token PID bits 3 & 2. PID bits 1 & 0 have a fixed value of 01. When a CTR interrupt occurs (see register ISTR) the software should read the TP3 and TP2 bits to retrieve the PID name of the token received. The USB standard defines TP bits as: Table 43. TP bits TP3 TP2 PID name 0 0 OUT 1 0 IN 1 1 SETUP Bits 5:3 Reserved. Forced by hardware to 0. 91/139 USB interface (USB) ST7260xx Bit 2 = RX_SEZ Received single-ended zero This bit indicates the status of the RX_SEZ transceiver output. 0: No SE0 (single-ended zero) state 1: USB lines are in SE0 (single-ended zero) state Bit 1 = RXD Received data 0: No K-state 1: USB lines are in K-state This bit indicates the status of the RXD transceiver output (differential receiver output). Note: If the environment is noisy, the RX_SEZ and RXD bits can be used to secure the application. By interpreting the status, software can distinguish a valid End Suspend event from a spurious wake-up due to noise on the external USB line. A valid End Suspend is followed by a Resume or Reset sequence. A Resume is indicated by RXD=1, a Reset is indicated by RX_SEZ=1. ) s t( c u d Bit 0 = Reserved. Forced by hardware to 0. 14.4.4 Interrupt status register (ISTR) e t le ISTR 7 6 5 4 SUSP DOVR CTR ERR R/W R/W R/W ) s ( ct b O - so R/W o r P Reset value: 0000 0000 (00h) 3 2 1 0 IOVR ESUSP RESET SOF R/W R/W R/W R/W When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: These bits cannot be set by software. u d o Bit 7 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB bus. The suspend request check is active immediately after each USB reset event and its disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register) until the end of resume sequence. r P e t e l o s b O Note: Bit 6 = DOVR DMA over/underrun. This bit is set by hardware if the ST7 processor can’t answer a DMA request in time. 0: No over/underrun detected 1: Over/underrun detected Bit 5 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. The type of transfer can be determined by looking at bits TP3-TP2 in register PIDR. The Endpoint on which the transfer was made is identified by bits EP1-EP0 in register IDR. 0: No Correct Transfer detected 1: Correct Transfer detected A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 92/139 ST7260xx USB interface (USB) 0: No error detected 1: Timeout, CRC, bit stuffing or nonstandard framing error detected Bit 3 = IOVR Interrupt overrun. This bit is set when hardware tries to set ERR, or SOF before they have been cleared by software. 0: No overrun detected 1: Overrun detected Bit 2 = ESUSP End suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. ) s t( This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected c u d Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected e t le Note: o r P The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB registers are reset by a USB reset. o s b Bit 0 = SOF Start of frame. This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is seen on the USB bus. It is also issued at the end of a resume sequence. 0: No SOF signal detected 1: SOF signal detected O ) s ( t c Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid read-modify-write instructions like AND , XOR.. 14.4.5 Interrupt mask register (IMR) u d o r P e t e l o O bs Reset value: 0000 0000 (00h) IMR 7 6 5 4 3 2 1 0 SUSPM DOVRM CTRM ERRM IOVRM ESUSPM RESETM SOFM R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:0 = These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the corresponding bit description in ISTR. 93/139 USB interface (USB) 14.4.6 ST7260xx Control register (CTLR) Reset value: 0000 0110 (06h) CTLR 7 6 5 4 3 2 1 0 0 0 0 0 RESUME PDWN FSUSP FRES R/W R/W R/W R/W R/W R/W R/W R/W Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. ) s t( c u d Software should clear this bit after the appropriate delay. Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V on-chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off e t le o r P o s b Note: After turning on the voltage regulator, software should allow at least 3 µs for stabilisation of the power supply before using the USB interface. O ) Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be halted allowing at least 600 ns before issuing the HALT instruction. 0: Suspend mode inactive 1: Suspend mode active s ( t c u d o When the hardware detects USB activity, it resets this bit (it can also be reset by software). r P e Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. t e l o bs O 94/139 The USB is held in RESET state until software clears this bit, at which point a “USB-RESET” interrupt will be generated if enabled. ST7260xx 14.4.7 USB interface (USB) Device address register (DADDR) Reset value: 0000 0000 (00h) DADDR 7 6 5 4 3 2 1 0 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 = Reserved. Forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration. ) s t( Note: This register is also reset when a USB reset is received from the USB bus or forced through bit FRES in the CTLR register. 14.4.8 c u d Endpoint n register A (EPnRA) EPnRA 7 6 5 4 ST_ OUT DTOG _TX STAT _TX1 STAT _TX0 R/W R/W R/W ) s ( ct 2 1 0 TBC3 TBC2 TBC1 TBC0 R/W R/W R/W R/W so b O R/W e t le 3 o r P Reset value: 0000 xxxx (0xh) These registers (EP0RA, EP1RA and EP2RA) are used for controlling data transmission. They are also reset by the USB bus reset. Note: Endpoint 2 and the EP2RA register are not available on some devices (see device feature list and register map). u d o Bit 7 = ST_OUT Status out. This bit is set by software to indicate that a status out packet is expected: in this case, all nonzero OUT data transfers on the endpoint are STALLed instead of being ACKed. When ST_OUT is reset, OUT transactions can have any number of bytes, as needed. r P e t e l o O bs Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted data packet. This bit is set by hardware at the reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX (see EPnRB) are normally updated by hardware, at the receipt of a relevant PID. They can be also written by software. Bits 5:4 = STAT_TX[1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which are listed below: 95/139 USB interface (USB) ST7260xx Table 44. STAT_TX bits STAT_TX1 STAT_TX0 Meaning 0 0 DISABLED: transmission transfers cannot be executed. 0 1 STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. 1 0 NAK: the endpoint is naked and all transmission requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for transmission. ) s t( These bits are written by software. Hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) related to a IN or SETUP transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. c u d o r P Bits 3:0 = TBC[3:0] Transmit byte count for Endpoint n. Before transmission, after filling the transmit buffer, software must write in the TBC field the transmit packet size expressed in bytes (in the range 0-8). e t le Caution: Any value outside the range 0-8 willinduce undesired effects (such as continuous data transmission). 14.4.9 Endpoint n register B (EPnRB) EPnRB 7 6 CTRL DTOG _RX R/W e t e ol du o r P R/W O ) s ( t c 5 o s b Reset value: 0000 xxxx (0xh) 4 3 2 1 0 STAT _RX1 STAT _RX0 EA3 EA2 EA1 EA0 R/W R/W R/W R/W R/W R/W These registers (EP1RB and EP2RB) are used for controlling data reception on Endpoints 1 and 2. They are also reset by the USB bus reset. Note: s b O Note: Endpoint 2 and the EP2RB register are not available on some devices (see device feature list and register map). Bit 7 = CTRL Control. This bit should be 0. If this bit is 1, the Endpoint is a control endpoint. (Endpoint 0 is always a control Endpoint, but it is possible to have more than one control Endpoint). Bit 6 = DTOG_RX Data toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. Bits 5:4 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which are listed below: 96/139 ST7260xx USB interface (USB) Table 45. STAT_RX bits STAT_RX1 STAT_RX0 Meaning 0 0 DISABLED: reception transfers cannot be executed. 0 1 STALL: the endpoint is stalled and all reception requests result in a STALL handshake. 1 0 NAK: the endpoint is naked and all reception requests result in a NAK handshake. 1 1 VALID: this endpoint is enabled for reception. ) s t( These bits are written by software. Hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) related to an OUT or SETUP transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. c u d o r P Bits 3:0 = EA[3:0] Endpoint address. Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. Usually EP1RB contains “0001” and EP2RB contains “0010”. 14.4.10 e t le Endpoint 0 register B (EP0RB) EP0RB 7 6 5 1 DTOG RX STAT RX1 R/W R/W R/W (s) o s b 3 2 1 0 STAT RX0 0 0 0 0 R/W R/W R/W R/W R/W -O t c u 4 Reset value: 1000 0000 (80h) d o r This register is used for controlling data reception on Endpoint 0. It is also reset by the USB bus reset. P e Bit 7 = Forced by hardware to 1. t e l o Bits 6:4 = Refer to the EPnRB register for a description of these bits. s b O14.5 Bits 3:0 = Forced by hardware to 0. Programming considerations The interaction between the USB interface and the application program is described below. Apart from system reset, action is always initiated by the USB interface, driven by one of the USB events associated with the Interrupt Status Register (ISTR) bits. 14.5.1 Initializing the registers At system reset, the software must initialize all registers to enable the USB interface to properly generate interrupts and DMA requests. 97/139 USB interface (USB) 14.5.2 ST7260xx 1. Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of DMA buffers). Refer the paragraph titled initializing the DMA Buffers. 2. Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint Initialization. 3. When addresses are received through this channel, update the content of the DADDR. 4. If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB register. Initializing DMA buffers ) s t( The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They can be placed anywhere in the memory space to enable the reception of messages. The 10 most significant bits of the start of this memory area are specified by bits DA15-DA6 in registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 42. c u d Each buffer is filled starting from the bottom (last 3 address bits=000) up. 14.5.3 Endpoint initialization e t le To be ready to receive: o r P o s b Set STAT_RX to VALID (11b) in EP0RB to enable reception. To be ready to transmit: Note: O ) 1. Write the data in the DMA transmit buffer. 2. In register EPnRA, specify the number of bytes to be transmitted in the TBC field 3. Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA. s ( t c Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB (respectively) must not be modified by software, as the hardware can change their value on the fly. u d o r P e When the operation is completed, they can be accessed again to enable a new operation. t e l o 14.5.4 Interrupt handling s b O Start of frame (SOF) The interrupt service routine may monitor the SOF events for a 1 ms synchronization event to the USB bus. This interrupt is generated at the end of a resume sequence and can also be used to detect this event. USB reset (RESET) When this event occurs, the DADDR register is reset, and communication is disabled in all endpoint registers (the USB interface will not respond to any packet). Software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the STAT_RX bits in the EP0RB register to VALID. Suspend (SUSP) The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend request. The software should set the USB interface to suspend mode and execute an ST7 HALT instruction to meet the USB-specified power constraints. 98/139 ST7260xx USB interface (USB) End suspend (ESUSP) The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7 automatically terminates HALT mode. Correct transfer (CTR) 1. When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to NAK. Note: Every valid endpoint is NAKed until software clears the CTR bit in the ISTR register, independently of the endpoint number addressed by the transfer which generated the CTR interrupt. Note: If the event triggering the CTR interrupt is a SETUP transaction, both STAT_TX and STAT_RX are set to NAK. ) s t( c u d 2. Note: Read the PIDR to obtain the token and the IDR to get the endpoint number related to the last transfer. o r P When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR register is cleared. 3. Table 46. Address e t le Clear the CTR bit in the ISTR register. o s b USB register map and reset values Register name 7 6 25 PIDR Reset Value TP3 x TP2 x 26 DMAR Reset Value DA15 x 27 IDR Reset Value 28 4 3 2 1 0 0 0 0 0 0 0 RX_SEZ 0 RXD 0 0 0 DA14 x DA13 x DA12 x DA11 x DA10 x DA9 x DA8 x DA7 x DA6 x EP1 x EP0 x CNT3 0 CNT2 0 CNT1 0 CNT0 0 ISTR Reset Value SUSP 0 DOVR 0 CTR 0 ERR 0 IOVR 0 ESUSP 0 RESET 0 SOF 0 IMR Reset Value SUSPM 0 DOVRM 0 CTRM 0 ERRM 0 IOVRM 0 ESUSP M 0 RESET M 0 SOFM 0 2A CTLR Reset Value 0 0 0 0 0 0 0 0 RESUM E 0 PDWN 1 FSUSP 1 FRES 0 2B DADDR Reset Value 0 0 ADD6 0 ADD5 0 ADD4 0 ADD3 0 ADD2 0 ADD1 0 ADD0 0 2C EP0RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 0 Reset Value 0 0 0 TBC3 x TBC2 x TBC1 x TBC0 x 2D EP0RB Reset Value 0 0 0 0 0 0 0 0 (Hex.) t e l o s b O 29 r P e 1 1 O ) s ( t c u d o DTOG_RX 0 5 STAT_RX 1 0 STAT_RX 0 0 99/139 USB interface (USB) Table 46. Address (Hex.) ST7260xx USB register map and reset values (continued) Register name 7 6 5 4 2E EP1RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 Reset Value 0 0 0 0 2F EP1RB Reset Value 30 EP2RA ST_OUT DTOG_TX STAT_TX1 STAT_TX0 Reset Value 0 0 0 0 31 EP2RB Reset Value CTRL 0 CTRL 0 STAT_RX 1 0 DTOG_RX 0 DTOG_RX 0 STAT_RX 1 0 STAT_RX 0 0 STAT_RX 0 0 3 2 1 0 TBC3 x TBC2 x TBC1 x TBC0 x EA3 x EA2 x EA1 x EA0 x TBC3 x TBC2 x TBC1 x TBC0 x EA3 x EA2 x EA1 x EA0 x e t le o s b O ) s ( t c u d o r P e t e l o s b O 100/139 o r P c u d ) s t( ST7260xx Instruction set 15 Instruction set 15.1 ST7 addressing modes The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Table 47. Addressing mode groups Addressing mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset e t le byte,#5 ) s t( c u d o r P o s b The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two sub-modes called long and short: O ) ● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. ● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) s ( t c u d o r P e The ST7 Assembler optimizes the use of long and short addressing modes. t e l o Table 48. s b O ST7 addressing mode overview Mode Syntax Destination/ source Pointer address Pointer size Length (bytes) Inherent nop +0 Immediate ld A,#$55 +1 Short Direct ld A,$10 00..FF +1 Long Direct ld A,$1000 0000..FFFF +2 No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register) + 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE +1 Long Direct Indexed ld A,($1000,X) 0000..FFFF +2 Short Indirect ld A,[$10] 00..FF 00..FF byte +2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 101/139 Instruction set Table 48. ST7260xx ST7 addressing mode overview (continued) Mode Destination/ source Syntax Pointer address Pointer size Length (bytes) Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 Relative Direct jrne loop PC-128/PC+127(1) Relative Indirect jrne [$10] PC-128/PC+127 Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Bit Indirect Relative btjt [$10],#7,skip Relative btjt $10,#7,skip +1 (1) 00..FF byte +2 +1 00..FF byte 00..FF +2 00..FF 00..FF byte +3 c u d 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 15.1.1 ) s t( +2 Inherent o r P All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Table 49. NOP (s) ct WFI du HALT ete SIM ol s b O 102/139 -O Function No operation TRAP IRET o s b Inherent instructions Instruction RET e t le o r P S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication ST7260xx Instruction set Table 49. Inherent instructions Instruction 15.1.2 Function SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Table 50. Instruction 15.1.3 ) s t( Immediate instructions Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations e t le c u d o r P o s b Direct O ) In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub-modes: s ( t c Direct (short) u d o The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. r P e Direct (long) t e l o The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. s b O 15.1.4 Indexed (no offset, short, long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (no offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. 103/139 Instruction set ST7260xx Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 15.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: ) s t( Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. c u d Indirect (long) o r P The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 15.1.6 e t le o s b Indirect indexed (short, long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. O ) s ( t c The indirect indexed addressing mode consists of two sub-modes: u d o Indirect indexed (short) r P e The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. t e l o Indirect indexed (long) s b O 104/139 The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. ST7260xx Instruction set Table 51. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes Instructions Long and short instructions Short instructions only Function LD Load CP Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Addition/subtraction operations BCP Bit Compare CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations c u d e t e BTJT, BTJF ol bs SWAP O ) 15.1.7 o r P Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC CALL, JP ) s t( Shift and Rotate Operations Swap Nibbles Call or Jump subroutine Relative mode (direct, indirect) s ( t c This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Table 52. r P e Instructions Function JRxx Conditional Jump CALLR Call Relative let so Ob u d o Available relative direct/indirect instructions The relative addressing mode consists of two sub-modes: Relative (direct) The offset follows the opcode. Relative (indirect) The offset is defined in memory, of which the address follows the opcode. 15.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: 105/139 Instruction set ST7260xx Table 53. Instruction groups Group Instruction Load and Transfer LD CLR PUSH POP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC Unconditional Jump or Call JRA JRT JRF JP CALL Conditional Branch JRxx Interruption management TRAP WFI HALT IRET SIM RIM SCF RCF Stack operation Condition Code Flag modification Using a pre-byte RSP uc SWAP od r P e ) s t( CALLR SLA NOP RET t e l o s b O The instructions are described with one to four bytes. ) (s In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. t c u The whole instruction becomes: d o r PC-2 PC-1 PC P e t e l o PC+1 s b O 106/139 End of previous instruction Prebyte Opcode Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. ST7260xx Table 54. Instruction set Instruction set Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M CALL Call subroutine CALLR CLR Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A reg, M DEC Decrement dec Y reg, M HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. interrupt = 1 ) (s M e t e Pr l o s Ob reg, M 0 1 N Z C N Z 1 N Z N Z N Z 0 H I C t c u d o r P e t e l o jrf * Jump if ext. interrupt = 0 Jump if H = 1 H=1? JRNH Jump if H = 0 H=0? JRM Jump if I = 1 I=1? JRNM Jump if I = 0 I=0? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < s b O u d o C jp [TBL.w] JRA JRH ct reg, M CP JRIL C Call subroutine relative Clear ) s ( JRUGE Jump if C = 0 Jmp if unsigned >= 107/139 Instruction set Table 54. ST7260xx Instruction set (continued) Mnemo Description Function/Example Dst Src JRUGT Jump if (C + Z = 0) Unsigned > JRULE Jump if (C + Z = 1) Unsigned