STB33N60M2

STB33N60M2 N-channel 600 V, 0.108 Ω typ., 26 A MDmesh M2 Power MOSFET in a D²PAK package Features TAB 2 3 1 D²PAK D(2, TAB) Order code VDS @ TJ max. RDS(on) max. ID STB33N60M2 650 V 0.125 Ω 26 A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected Applications • • G(1) Switching applications LLC converters, resonant converters Description S(3) AM01475V1 This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STB33N60M2 Product summary Order code STB33N60M2 Marking 33N60M2 Package D²PAK Packing Tape and reel DS9930 - Rev 3 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STB33N60M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 26 A Drain current (continuous) at TC = 100 °C 16 A Drain current (pulsed) 104 A Total power dissipation at TC = 25 °C 190 W dv/dt(2) Peak diode recovery voltage slope 15 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range -55 to 150 °C Value Unit VGS ID IDM (1) PTOT Tj Parameter Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 26 A, di/dt ≤ 400 A/μs, VDS(peak) < V(BR)DSS, VDD = 400 V. 3. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 0.66 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 30 °C/W Value Unit 1. When mounted on FR-4 board of 1 inch², 2oz Cu. Table 3. Avalanche characteristics Symbol DS9930 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 5 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 450 mJ page 2/17 STB33N60M2 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current 1 µA 100 µA ±10 µA 3 4 V 0.108 0.125 Ω Min. Typ. Max. Unit - 1781 - pF - 85 - pF - 2.5 - pF VGS = 0 V, VDS = 600 V, TC = 125 °C(1) IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 13 A Unit V VGS = 0 V, VDS = 600 V IDSS Max. 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance (1) Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 135 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.2 - Ω Qg Total gate charge VDD = 480 V, ID = 26 A, - 45.5 - nC Qgs Gate-source charge VGS = 0 to 10 V - 9.9 - nC Qgd Gate-drain charge (see Figure 15. Test circuit for gate charge behavior) - 18.5 - nC Coss eq. 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS9930 - Rev 3 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 300 V, ID = 13 A, - 16 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 9.6 - ns Turn-off delay time (see Figure 14. Test circuit for resistive load switching times and Figure 19. Switching time waveform) - 109 - ns - 9 - ns Fall time page 3/17 STB33N60M2 Electrical characteristics Table 7. Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 26 A ISDM(1) Source-drain current (pulsed) - 104 A VSD(2) Forward on voltage VGS = 0 V, ISD = 26 A - 1.6 V trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs, - 375 ns Qrr Reverse recovery charge VDD = 60 V - 5.6 µC Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 30 A trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs, - 478 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 7.7 µC Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 32.5 A IRRM IRRM 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. DS9930 - Rev 3 page 4/17 STB33N60M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Normalized thermal impedance Figure 1. Safe operating area AM17906v1 ID (A) ) on D S( O Li p e r m at ite io d ni by n m th is ax a R re a is 100 10 10µs 100µs 1ms 10ms 1 Tj=150°C Tc=25°C S ingle puls e 0.1 0.1 10 1 VDS (V) 100 Figure 3. Output characteristics Figure 4. Transfer characteristics AM17907v1 ID (A) VGS =7, 8, 9, 10V 6V 60 AM17908v1 ID (A) VDS =17V 60 50 50 40 40 5V 30 30 20 20 10 0 10 4V 10 5 0 15 20 VDS (V) Figure 5. Gate charge vs gate-source voltage AM17909v1 VDS VGS (V) VDD=480V ID=26A 12 0 2 0 4 6 8 10 VGS (V) Figure 6. Static drain-source on-resistance (V) R DS (on) (Ω ) 500 0.114 400 0.112 300 0.110 200 0.108 100 0.106 AM17910v1 VGS =10V VDS 10 8 6 4 2 0 DS9930 - Rev 3 0 10 20 30 40 50 0 Q g (nC) 0.104 0 5 10 15 20 25 ID(A) page 5/17 STB33N60M2 Electrical characteristics (curves) Figure 7. Capacitance variations AM17911v1 C (pF) Figure 8. Output capacitance stored energy AM17912v1 E os s (µJ ) 12 10000 10 Cis s 1000 8 6 100 Cos s 4 10 2 Crs s 1 0.1 1 100 10 Figure 9. Normalized gate threshold voltage vs temperature AM17913v1 VGS (th) 0 0 VDS (V) (norm) 100 200 300 400 500 600 VDS (V) Figure 10. Normalized on-resistance vs temperature AM17914v1 R DS (on) (norm) ID=250µA ID=13A VDS =10V 2.3 1.1 2.1 1.9 1.0 1.7 0.9 1.3 1.5 1.1 0.9 0.8 0.7 -50 0.7 -25 0 25 50 75 100 TJ (°C) Figure 11. Normalized VDS vs temperature AM17915v1 V(BR)DSS (norm.) 0.5 -50 -25 0 25 50 75 100 TJ (°C) Figure 12. Source-drain diode forward characteristics AM17916v1 VS D ID=1mA 1.09 1.07 TJ =-50°C 1.05 1.03 1.01 TJ 0.99 TJ =150°C 0.97 0.95 0.93 0.91 -50 DS9930 - Rev 3 -25 0 25 50 75 100 TJ (°C) 0 4 IS D page 6/17 STB33N60M2 Electrical characteristics (curves) Figure 13. Maximum avalanche energy vs temperature EAS (mJ) GADG070220191439EAS 400 300 ID = 5 A, VDD = 50 V 200 100 0 -75 DS9930 - Rev 3 -25 25 75 125 TJ (°C) page 7/17 STB33N60M2 Test circuits 3 Test circuits Figure 14. Test circuit for resistive load switching times Figure 15. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 17. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 19. Switching time waveform Figure 18. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9930 - Rev 3 page 8/17 STB33N60M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS9930 - Rev 3 page 9/17 STB33N60M2 D²PAK (TO-263) type A package information 4.1 D²PAK (TO-263) type A package information Figure 20. D²PAK (TO-263) type A package outline 0079457_26 DS9930 - Rev 3 page 10/17 STB33N60M2 D²PAK (TO-263) type A package information Table 8. D²PAK (TO-263) type A package mechanical data Dim. mm Min. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 7.75 8.00 D2 1.10 1.30 1.50 E 10.00 E1 8.30 8.50 8.70 E2 6.85 7.05 7.25 e 10.40 2.54 e1 4.88 5.28 H 15.00 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R V2 DS9930 - Rev 3 Typ. 0.40 0° 8° page 11/17 STB33N60M2 D²PAK (TO-263) type A package information Figure 21. D²PAK (TO-263) recommended footprint (dimensions are in mm) Footprint_26 DS9930 - Rev 3 page 12/17 STB33N60M2 D²PAK packing information 4.2 D²PAK packing information Figure 22. D²PAK tape outline DS9930 - Rev 3 page 13/17 STB33N60M2 D²PAK packing information Figure 23. D²PAK reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 9. D²PAK tape and reel mechanical data Tape Dim. DS9930 - Rev 3 Reel mm mm Dim. Min. Max. Min. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T Max. 330 13.2 26.4 30.4 P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 page 14/17 STB33N60M2 Revision history Table 10. Document revision history Date Version 13-Sep-2013 1 Changes First release. – Modified: RDS(on) and ID values in cover page – Modified: values in Table 4 19-Nov-2013 2 – Modified: RDS(on) typical and maximum values in Table 5, the entire typical values in Table 6, 7 and 8 – Added: Section 2.1: Electrical characteristics (curves) – Minor text changes Removed maturity status indication from cover page. The document status is production data. 18-Jun-2019 3 Update Table 3. Avalanche characteristics. Added Figure 13. Maximum avalanche energy vs temperature. Minor text changes. DS9930 - Rev 3 page 15/17 STB33N60M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 D²PAK (TO-263) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 D²PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DS9930 - Rev 3 page 16/17 STB33N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS9930 - Rev 3 page 17/17