STD3PS25

STD3PS25 - STD3PS25-1 P-CHANNEL 250V - 2.1Ω - 3A DPAK/IPAK MESH OVERLAY™ MOSFET TYPE STD3PS25 STD3PS25-1 s s s VDSS 250 V 250 V RDS(on) < 2.8 Ω < 2.8 Ω ID 3A 3A 3 1 2 1 3 s s TYPICAL RDS(on) = 2.1Ω 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY GATE-SOURCE ZENER DIODE DPAK IPAK DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for lighting applications. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS CONSUMER s LIGHTING s ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (1) PTOT Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Storage Temperature Max. Operating Junction Temperature Value 250 250 ±25 3 1.9 12 45 0.36 – 50 to 150 150 Unit V V V A A A W W/°C °C °C June 2003 1/10 STD3PS25 - STD3PS25-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 2.77 100 275 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 20 V Min. 250 1 10 ±10 Typ. Max. Unit V µA µA µA ON Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250 µA VGS = 10 V, ID = 0.3 A Min. 2 Typ. 3 2.1 Max. 4 2.8 Unit V Ω DYNAMIC Symbol Ciss Coss Crss RG Parameter Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate-Input Resistance f = 1 MHz,Gate DC Bias=0 Test Signal Level=20 mV Open Drain Test Conditions VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 260 52 25 6 Max. Unit pF pF pF Ω 2/10 STD3PS25 - STD3PS25-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 125V, ID = 1.5A RG = 4.7Ω VGS = 10V (Resistive, see Figure 3) VDD = 200V, ID= 1.5A, VGS = 10V Min. Typ. 12 22 16 1.4 7.6 21 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 200V, ID = 1.5A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. Typ. 29.5 7 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (4) VSD (5) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Curren ISD = 3A, VGS = 0 ISD = 0.60A, di/dt = 100A/µs, VDD = 40V, Tj = 150°C (see test circuit, Figure 5) 143 806 11 Test Conditions Min. Typ. Max. 3 12 1.5 Unit A A V ns nC A GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 500 µA (Open Drain) Min. ± 25 Typ. Max. Unit V (4) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (5) Pulse width limited by safe operating area PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 3/10 STD3PS25 - STD3PS25-1 Safe Operating Area p-ch Thermal Impedance for Complementary pair Output Characteristics p-ch Transfer Characteristics p-ch Transconductance p-ch Static Drain-source On Resistance p-ch 4/10 STD3PS25 - STD3PS25-1 Gate Charge vs Gate-source Voltage p-ch Capacitance Variations p-ch Norm. Gate Thereshold Voltage vs Temp p-ch NormalizedOnResistancevsTemperaturep-ch Source-drainDiodeForwardCharacteristicsp-ch Normalized BVDSS vs Temperature p-ch 5/10 STD3PS25 - STD3PS25-1 Fig. 1: Switching Times Test Circuit For Resistive Load Fig. 2: Gate Charge test Circuit Fig. 3: Test Circuit For Diode Recovery Behaviour 6/10 STD3PS25 - STD3PS25-1 TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 V2 0.60 0o 2.20 0.90 0.03 0.64 5.20 0.45 0.48 6.00 6.40 4.40 9.35 0.8 1.00 8o 0.024 0o TYP. MAX. 2.40 1.10 0.23 0.90 5.40 0.60 0.60 6.20 6.60 4.60 10.10 MIN. 0.087 0.035 0.001 0.025 0.204 0.018 0.019 0.236 0.252 0.173 0.368 0.031 0.039 0o inch TYP. MAX. 0.094 0.043 0.009 0.035 0.213 0.024 0.024 0.244 0.260 0.181 0.398 DIM. P032P_B 7/10 STD3PS25 - STD3PS25-1 TO-251 (IPAK) MECHANICAL DATA DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033 H A C C2 L2 D B3 B6 A1 L = = 3 B5 B A3 = B2 = G = E L1 1 2 = 0068771-E 8/10 STD3PS25 - STD3PS25-1 DPAK FOOTPRINT TUBE SHIPMENT (no suffix)* All dimensions are in millimeters All dimensions are in millimeters TAPE AND REEL SHIPMENT (suffix ”T4”)* REEL MECHANICAL DATA DIM. A B C D G N T 1.5 12.8 20.2 16.4 50 22.4 18.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK QTY 2500 inch MIN. MAX. 12.992 TAPE MECHANICAL DATA DIM. A0 B0 B1 D D1 E F K0 P0 P1 P2 R W BASE QTY 2500 mm MIN. 6.8 10.4 1.5 1.5 1.65 7.4 2.55 3.9 7.9 1.9 40 15.7 16.3 inch MIN. MAX. 7 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574 0.618 0.641 MAX. 10.6 12.1 1.6 1.85 7.6 2.75 4.1 8.1 2.1 * on sales type 9/10 STD3PS25 - STD3PS25-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 10/10